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If this is related to preventing a competitor from selling boards with your functionality after capturing your bitstreams and then programming identical FPGAs I solved this problem by going to Fuse-based FPGAs from Actel. RAULArticle: 91076
Austin Lesea wrote: > Antti, > > Selling known bad parts is an interesting concept. > > No one has figured out how to do that. ?! - So Xilinx have no errata, on any devices ? Wow ? I'd say pretty much everyone sells bad silicon. As to selling 'bad by device' [unknown bad parts], that too has been done in Russia. NAND flash that maps bad sectors in the FAT, is also 'bad by device', so this is not a new, or novel, idea. The risk to Xilinx is of the parts being relabeled, and sold as genuine, plus all the traffic on how to get these bad xilinx devices to limp along. ie bad for the brand, plus imagine if someone (like Antti) actually got really good at this, and found that a large chunk of sales switched to the low yield El-Cheapo parts - not good for Xilinx's shareholders either.... So I cannot see it happening, but not for technical reasons. Easypath is the closest Xilinx will get. -jgArticle: 91077
Philip Freidin wrote:
> You will notice the amazing fact that unlike the rest of
> the frame that is sent LSB first, the FCS is sent MSB first.
This numbering likely comes from
the schematic in Appendix C (pg 77)
of the same document:
"The Ethernet" ver. 1.0 Sept 30, 1980
by digital|intel|xerox.
It looks to me like the author
got the circuit working first and
wrote the spec based on that.
This appendix contains some critical
hardware details missing from the formal
specification:
1. The feedback shift register should be
initialized to all ones for every
frame, and the fact that this is
logically equivalent to curious
inversions in the formal specification.
2. The input to the circuit starts at the "x0" end.
3. The magic remainder value left in the x register
for a good frame check is:
x(0 downto 31) = x"debb_20e3"
Or as it is more commonly seen in memory
x(31 downto 0) = x"c704_dd7b"
-- Mike Treseler
Article: 91078Hi Newman, > I've had this happen to me using Altera's MaxPlusII Verilog (I remember > cause I got yelled at). This was a while back, and the Quartus version > may have improved since then. You bet it has. Results are very close to Precision and Synplify. It now also has just as good a language coverage as the other two. Best regards, BenArticle: 91079
>What you have the CoolRunner will not work for the xc9500 family because >the configuration algorithms are radically different. Having written the tools from scratch starting with the logic compiler and ending with the JTAG access hardware & software, thus my design chain being 100% self supplied - I would have thought I knew that. I wonder based on what experience you thought I did not know. I offered the guy my help simply because I do have knowledge way above average on the subject and I might be of some help at some stage - he would probably know if and when. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 91080
"Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> schrieb im Newsbeitrag news:djkmeg$mdo$1@sunnews.cern.ch... >I know this isn't exactly comp.arch.cpld... > > does anyone know of a COTS solution for programming a (Xilinx) CPLD > without using PC + Windows + Impact etc etc. (a stand alone chunk of > hardware with a way for me to give it a set of bit files and a Program > button would be nice) small uclinux modules sell for less than 100EUR. it takes a few hours to get XSVFplayer to work there. I use it in desing to program the XC9572XL, the mdoule we used was from www.dilnetpc.com coldfire based, but the production has not changed to use small fpga linux modules (microblaze uclinux) www.hydraxc.com anttiArticle: 91081
Hi Bob, > I am not at all sure about the "Hardcopy" cost, since that is from > Xilinx's website too, not Altera's (as I mentioned in my post). > Xilinx's cost estimate may put Altera's product in an unfavorable > light, but it serves them right. If they want accurate information > disseminated, they should provide the information themselves. I > could find no price information anywhere on Altera's website. For Hardcopy, NRE and device price are negotiated on a per-project basis. From my (very limited) experience, $500K for the NRE is grossly exaggerated though. Best regards, BenArticle: 91082
a) No need to init the PHY - after reset it will operate cleanly b) You do not need to play with MDC and MDIO c) You do not need to send an ethernet packet to the PHY - it doesn't care what the data is d) It will be sinusoid - but it should already be running, I would imagine, as the link setup has occurred (100Mbps was autonegotiated). At least you should see some data while autonegotiation is going on, and you will see similar patterns when you transmit data. The data on the wires is a 125MHz signal, not 100MHz. For Tx to work you need only... TxEn asserted TxErr deasserted TxClk running cleanly Don't try to 'see' the TxD bits coming out on the TD pins - sending '0000' on TxD does not cause TD pins to transmit 0000; they do something much more exciting that you probably don't want to get in to.Article: 91083
The PCI Express physical layer interface is a fully defined standard, and part of the larger standard. It matters not at all what your application is. Go here: http://www.pcisig.com/specifications/pciexpress/ Get the spec Read it Interestingly, you stated you had found a device with the SSTL2 spec - that's memory :) Cheers PeteSArticle: 91084
Reading your query again, it seems you are trying to interface to an Intel device (communications controller perhaps). 1. Intel does not own the PCI Express spec (although they probably paid more than anyone else to getting it made). 2. Intel devices that claim to meet a specification generally do. (There are exceptions, but even that is noted in the data sheet). 3. You seem confused about what you are trying to do :) Cheers PeteSArticle: 91085
Hello, in the "XtremeDSP for Virtex-4 FPGAs User Guide", on Page 56 are in Table 1-13 some interesting functions mentioned, like AND and XOR and so on. Does anyone know how these functions are accomplished? Is there any documentation available which describes other more or less hidden (secret?) features of the DSP48 block? Many thanks! UdoArticle: 91086
I am looking for a program / a website / or anything that would allow me to verify Reed Solomon code that my FPGA generates. Any help will be greatly appreciated. Regards, Wojciech ToczynskiArticle: 91087
Thanks Gavin, I tried what you suggest, powering up the board before plugging in the download cable. Unfortunately, the behavior is still the same. I have contacted my local Avnet FAE and he is setting up a similar board with USB cables and getting his environment setup and working. Then I am traveling to him with my board and cables and we'll swap in my stuff one piece at a time and see if we can't identify the problem. So, to be fair Avnet is helping me get through the issue.Article: 91088
Hello, now Virtex-4 contains the two different slices, SLICEM and SLICEL, like Spartan-3,too. Same reasons? Thanks and greetings UdoArticle: 91089
Yes, same reason. The LUT-RAM / SRL16 functionality is not really "free", and we think that at least half of the LUTs do not use it. So we saved some area, and you save some money, by deleting this functionality from 50% of the LUTs. It's a typical cost/benefit trade-of... Peter Alfke, Xilinx Applications. Udo,I am still working on your question about the DSL slices.Article: 91090
Hello Peter, many thanks for your fast answer and greetings from Germany. I have forgotten one question - Virtex-4 doesn't have internal tristate buffers anymore. Why? UdoArticle: 91091
Brian Philofsky wrote:
> If you re-write the code to use these attributes, you will likely get
> what you want out of the synchronization circuit:
>
> module test(input clk, input in_sig, output reg out_sig);
>
> (* ASYNC_REG="TRUE", SHIFT_EXTRACT="NO", RLOC="X0Y0" *) reg [1:0] ss;
>
> always @(posedge clk)
> begin
> out_sig <= ss[1];
> ss <= { ss[0], in_sig };
> end
>
> endmodule
I just tried to instantiate the above module multiple times (for
different async inputs), like this:
module tsync(input clk, input in1, input in2, output out1, output
out2);
test t1(.clk(clk), .in_sig(in1), .out_sig(out1));
test t2(.clk(clk), .in_sig(in2), .out_sig(out2));
endmodule
And I got a MAP error in XST:
Section 1 - Errors
------------------
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset,
RLOC=X0Y0)
which require the combination of the following symbols into a single
SLICE
component:
FLOP symbol "t1/ss_0" (Output Signal = t1/ss<0>)
FLOP symbol "t1/ss_1" (Output Signal = t1/ss<1>)
FLOP symbol "t2/ss_0" (Output Signal = t2/ss<0>)
FLOP symbol "t2/ss_1" (Output Signal = t2/ss<1>)
There are more than two registers. Please correct the design
constraints
accordingly.
Rookie mistake, I'm sure... but I'm stuck!! Help!
Regards,
Paul.
Article: 91092Tristate buffers on metal lines slow them down and are being phased out of Xilinx devices. If you do need multiple drivers on a single line use a mux instead, they are much faster. I found 2 good threads on the same topic Thread 1 http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/33e442048fb99734/d520d67ab735e3cc?q=tristate+buffers&rnum=6#d520d67ab735e3cc Thread 2 http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/8eefcd483fbc8f4a/54eb3278571e1601?q=tristate+buffers&rnum=2#54eb3278571e1601 KunalArticle: 91093
Is there a way to: 1. Prefill the Microblaze instruction cache with program 2. Startup with caches enabled and locked Then I could put boot code in the icache which would load external ram. I would then have a bigger cache since right now my block ram is split between lmb ram and cache. Am I the only person who would find this useful? Alan Nishioka alan@nishioka.comArticle: 91094
I have a Verilog module that has been synthesized but not mapped. I would like to be able to reuse the NGC file in another design but Xilinx ISE 7 does not seem to want to read in a NGC file as one of the input files. ISE 7 also does not seem to generate a usable EDN file. What is the recommended netlist format for IP core/design reuse ? Thanks. JimArticle: 91095
Jim, Using NGC files with ISE works perfectly for me (and i guess for everybody) The method for integrating an IP in NGC form is however not obvious : - in VHDL : declare the entity WITHOUT architecture and instantiate it as usual : port map(clk => clk,etc...) ( in VERILOG : i dont know verilog, sorry ) - put the NGC file in the ISE project directory. Then when 'making' bitfile, you see a message saying : "reading <toto.ngc>.." "James Bond" <sjjmacls@dacafe.com> a écrit dans le message de news: sEB8f.7527$7h7.1329@newssvr21.news.prodigy.com... >I have a Verilog module that has been synthesized but not mapped. > I would like to be able to reuse the NGC file in another design but > Xilinx ISE 7 does not seem to want to read in a NGC file as one of the > input files. ISE 7 also does not seem to generate a usable EDN file. > > What is the recommended netlist format for IP core/design reuse ? > > Thanks. > > Jim >Article: 91096
Hi,
1. I have to get 48 bit output from one of my synthesizable block,So I
declared it as
output [47:0]Command;
reg [47:0]Command;
and the synthesis report of this block is
Selected Device : 3s50vq100-5
Number of Slices: 51 out of 768 6%
Number of Slice Flip Flops: 4 out of 1536 0%
Number of 4 input LUTs: 89 out of 1536 5%
Number of bonded IOBs: 70 out of 63 111%
Number of GCLKs: 1 out of 8 12%
2. So I used one temperory internal register and assigned to the
output, still I got the same result:
output [47:0]Command;
wire [47:0]Command;
reg [47:0]Temp;
assign Command = Temp;
Selected Device : 3s50vq100-5
Number of Slices: 51 out of 768 6%
Number of Slice Flip Flops: 4 out of 1536 0%
Number of 4 input LUTs: 89 out of 1536 5%
Number of bonded IOBs: 70 out of 63 111%
Number of GCLKs: 1 out of 8 12%
3. Then I removed the output and used only the internal register, then
I got the good result:
reg [47:0]Command;
Selected Device : 3s50vq100-5
Number of Slices: 4 out of 768 0%
Number of Slice Flip Flops: 4 out of 1536 0%
Number of 4 input LUTs: 8 out of 1536 0%
Number of bonded IOBs: 22 out of 63 34%
Number of GCLKs: 1 out of 8 12%
If use Command as only internal register then the logic is less and
its utilizing less LUTs.
If I make it as output then there is more logic and more LUTs
utilization.But I need to get the Command as
48 bit output with less LUTs utilization. Is there any other
approach to get Command as output with less logic.
Please suggest me.
Best Regards,
HimaSSK.
Article: 91097Any body knows when the Spartan-3E starter kit will be availaible from Xilinx? Website says 4th quarter. Isn't it 4th quarter already?Article: 91098
Hi, Don't happen to have an LVDS specification (EIA-644) handy and couldn't find a freebie on the www. So hopefully someone out there has one. Here's the question, I was told that section 4.4.2, & 6 have the fail-safe requirements. The issue is whether cold sparing capability is an LVDS requirement. I don't recall it being a requirement but I do want to go to the documentation to be sure. My design does have cold sparing capability, it's the right thing to do for this particular application, so that is not an issue. It is critical that the intent of the system designers, who state that they want cold sparing capability, be properly documented in the requirements (many users geographically and organizationally diverse) to avoid an oops. Having a specification buried in a third level referenced document that is not easy to obtain is a good opportunity for an oops. But if cold sparing isn't part of the EIA-644 specification, then the top level specification that the systems guys are writing needs to be updated. Thanks in advance, -- rk, Just an OldEngineer "These are highly complicated pieces of equipment almost as complicated as living organisms. In some cases, they've been designed by other computers. We don't know exactly how they work." -- Scientist in Michael Crichton's 1973 movie, WestworldArticle: 91099
Emtech wrote: > This is for an RGB LED demo display application. > > 1. There will be mixing of colours done at say 3ms intervals for > each colour to stay ithin the 10ms and take avantage of > persistance of vision. > 2. Bits accuracy in the duty cycle is not very important since > the PWM is only for brightness control. > 3. The outputs must at least be synchronized to the colour mixing > intervals, i.e. 3ms intervals. In other words, the PWM will > further divide the 3ms intervals to control brightness. > 4. These will only be used in an RGB LED display application > hence the only real importance is the 10ms refresh limit. > > Thank you for your input. Very interesting. Earlier this year I did a PWM design to control RGB LEDs for a medical testing device. The client wanted a total of 61 RGB LEDs, or 183 channels of PWM output, with 16-bit resolution and 1 ms refresh period (Yes, this means a 65.536 MHz clock). I divided this up into three Xilinx Spartan-3 FPGAs with 63 PWM output channels each in order to avoid BGA packages and simplify the overall PCB layout. Each FPGA drives 20 or 21 RGB LED chips. IIRC, it didn't quite fit into an XC3S50, so we ended up using the XC3S200. A design with less resolution or fewer channels would easily fit into the smaller chip. The PWM hardware is driven entirely by the contents of a single block RAM, and uses one of the RAM's ports to read out the data. This gives a great deal of flexibility as to how the system controller gets the intensity values into the RAM via its other port, using anything from a conventional parallel bus interface to a synchronous or asynchronous serial interface. -- Dave Tweed
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