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Arg! What did they do to the Waveform and Simulator tools?Article: 91001
Brad Smallridge wrote: > Thank you Joseph, > > I did what you suggested and did an example program. I am using LVDS inputs > and want 7:1 serdes. > > The placement seems to be somewhat what you said in that the master iserdes > gets placed right next to the _p pad. The _n pad shows a single connection > going > to the _p pad. However the slave serdes seems to be placed willy-nilly, not > in the > same tile, and sometimes mixed with a master iserdes of a different lvds > signal in > the same tile. Is there something you are doing to put the slave iserdes in > the > same tile as the master, like a constraint? I just LOC'd the IO pins. I'm verifying the pinout of a new design, so I spent a few days trying out different banks and pin choices. I looked at almost every route in FPGA editor and only ever saw the master and slave paired with the two LVDS IOs. I'm using the reference design from XAPP705; maybe other logic is forcing the placement. There might be a timing spec that can only be satisfied if the ISERDES are in the same tile. --- JoeArticle: 91002
Have you ever looked at implementing the state machine in a ROM = BlockRAM? You can have hundreds of states and still run at several hundred MHz. Pick a ROM size, feed part of the outputs directly back as inputs (remember, theBlockRAM is synchronous!) and add the condition inputs to the addresses. For exmple: 1K x 16 with 7 outputs fed back gives you 128 states with 3 additional inputs that can encode the jump condition at each state. You can conditionally (8-way) jump from anywhere to anywhere, without any restrictions. And you still have 9 freely assignable outputs for each state. Runs at 200 MHz+. Peter Alfke, Xilinx ApplicationsArticle: 91003
Ashwin, I suppose English is not your native language. Otherwise you would know that "request" is a very strong word, kind of like "command", used only by a superior (or an unfriendly institution). Adding "would" and "please" does not eliminate the air of arrogance... Of course, you did it out of lack of knowledge. PeterArticle: 91004
Hello,
I'm just starting doing partial reconfiguration through HWICAP on
xc2v4000 and confused about its coding. First things first, I must
initialize the ICAP module in EDK. But after calling HwIcap_Initialize
function, I did not get any feedbacks. Anything wrong with my code?
OPB_HWICAP provides a 16k BRAM used as a configuration memory cache
(DS280). Does anyone know how to load the partial reconfiguration
bitstream produced by ISE into this BRAM? Do I need to do
byte-swapping? Thank you so much for your help.
XStatus status;
XHwIcap * InstancePtr;
status=XHwIcap_Initialize(InstancePtr, XPAR_OPB_HWICAP_0_DEVICE_ID,
XHI_READ_DEVICEID_FROM_ICAP);
switch (status)
{
case XST_DEVICE_IS_STARTED:
xil_printf("DEVICE IS STARTED\n\n\r");
break;
case XST_DEVICE_NOT_FOUND:
xil_printf("DEVICE NOT FOUND\n\n\r");
break;
case XST_SUCCESS:
xil_printf("ICAP SUCCESS\n\n\r");
break;
case XST_INVALID_PARAM:
xil_printf("INVALID PARAM\n\n\r");
break;
default :
xil_printf("INVALID PARAM\n\n\r");
break;
}
Article: 91005How much does it cost to produce an ASIC? This is for a simple customized 8-bit CPU and 64KB of on-chip RAM. If it is already working in an FPGA, can I count on the ASIC also working? Can I just hand the VHDL/Verilog files to the fabricator? Or should I change the design to take advantage of ASIC features (like maybe gated clocks to reduce power consumption). If you have moved a design from FPGA to ASIC, how difficult was the process? What did you gain in terms of speed and/or power consumption?Article: 91006
Both Xilinx and Altera has options to move to ASIC-like implementations from FPGA designs. These chips have a lower unit cost. Xilinx calls it EasyPath Solution : http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm . Altera calls it Hardcopy http://www.altera.com/products/devices/hardcopyii/hr2-index.jspArticle: 91007
Mike Treseler wrote: > ashwin wrote: > >> 2) Is CRC implemented on only data or on whole frame? > > > The fcs field is calculated for the whole frame on transmit. > It is checked using the whole frame + fcs on receive. > Slight precision : I don't think the preamble and sof are used for the fcs. Or am I wrong ? > >> 4) If CRC is wrong, will the PHY still transmit the data onto the PC. > > > If it didn't you would never see a bad fcs. Well, the corruption could happen on the wire ;) But still, the PHY don't care. For it to not transmit invalid frames would require it to buffer the whole frame internally before sending ... SylvainArticle: 91008
ashwin wrote:
>hi Mike,
> Thanks for sending a reply for few questions on ethernet. I just
>wanted to confirm with you that , even though crc computation is wrong,
>we should be able to see the data capture in the PC right?
There are many reasons you might not see data on
your pc, but I don't think the fcs value is your problem.
> Doesnt the Ethernet PHY reject the data if the CRC is wrong?
A router might throw away a bad packet
but a phy is not that smart. FCS generation
and validation is done in the Media Access Controller.
> Because i am unable to detect the data coming out from the
> ethernet PHY on the fpga board.
Get out a scope and see if anything is wiggling.
> I would like to discuss more on a particular data sheet on DP83847
> ETHERNET PHY.
Read the data sheet again and do a little debugging first.
But post your questions here. I don't check that mail
account regularly.
-- Mike Treseler
Article: 91009
Hi,
besides the hints of Mr. Alfke there's something more you can do:
Check your Synthesis report for the number off infered adders and/or
counters.
If you find high numbers of these elements your FSM description probably
contain assignments like:
when thisstate => if something then
someoutput<= someoutput + 1;
end if;
Synthesis tools often create an adder for this assignment in each state
it is used, even if you add to the same signal.
A better approach is to create a separate counter and write:
when thisstate => if something then
couterenable <= '1';
end if;
As a rule of thumb:
Never let your statemachine do calculations.
-- Arithmetic elements slow it down.
Always use straight assignments of either constants or signals
(variables) to the FSMs outputs.
-- A FS shall control dataflow, manipulation of data should be done in
separate dedicated modules.
Check your source and
have a nice synthesis
Eilert
gkirilov schrieb:
> I designed a SM which can run at 30Mhz below my target
> frequency(that's what XST shows after synthesis (no PAR).
>
> It is a pretty big SM(a lot of states, input, output and internal
> signals) and I have to optimize it somehow. My question is what
> influences the timing so I can concentrate on it.
> I have a Mealy type SM - 2 processes:
> 1st - synch to CLK. the internal signals and outputs are assigned
> here
> 2nd - sensitive to all inputs, internel signals(from 1st process) and
> current state.
> I am using one-hot encoding for the SM.
> ideas ;)?
>
Article: 91010
backhus wrote:
> when thisstate => if something then
> someoutput<= someoutput + 1;
> end if;
>
> Synthesis tools often create an adder for this assignment in each state
> it is used, even if you add to the same signal.
I have seen no evidence of this using either Quartus or Mentor
Synthesis. A clock enable is properly inferred.
-- Mike Treseler
Article: 91011Kunal wrote: > Both Xilinx and Altera has options to move to ASIC-like implementations > from FPGA designs. These chips have a lower unit cost. > > Xilinx calls it EasyPath Solution : > http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm > . > Altera calls it Hardcopy > http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp Very interesting. The Xilinx "EasyPath" seems to be a partialy pre-programmed FPGA. The main (only?) benefit appears to be lower unit cost. There is no power or performance benefit over a standard FPGA. The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs are also much higher. It will run faster and use less power (~50%) than the same logic in an FPGA. The up-front cost for "EasyPath" is about $75,000. The up-front cost for "Hardcopy" is about $500,000. Both of these costs are from Xilinx's website. Altera's site mentions no prices. Both companies guarantee than if the design works in the FPGA, it will work the same or better in the "ASIC".Article: 91012
Peter Alfke wrote_ > No problem, not even with ten bits parallel. What do I do if I need 12? We use a lot of TI's ADS527X-ADCs, and those output 12bit-data-words over LVDS-DDR-outputs running at 420MHz and higher. Up to now we have a lot of fiddeling to do in Virtex-II Pro (see xapp774), so the ISERDES seemed like the perfect solution. Only it seems that in Master/Slave-Configuration, the maximum you can do is 10bit. Is there any way to expand this, or do I have to do this "manually", i.e. without the ISERDES, just like in Virtex-II Pro? cu, SeanArticle: 91013
Hello, ALL!
Recently I got an example of code, demonstrating some techniques, I
also need to implement in my design. The code has been developed in
Verilog and was intended to be used as a part of ASIC design. Here is
the couple lines from it:
=============================================================
// psceq0 :: Prescale Counter Equal to Zero
assign psceq0 = ( psc == 5'h0 );
// gpsc[4:0] :: Go clock prescale counter
assign gpsc = { 5 { psceq0 & p_clk == 3'h7 } } & 5'hd
| { 5 { psceq0 & p_clk == 3'h6 } } & 5'h9
| { 5 { psceq0 & p_clk == 3'h5 } } & 5'h6
| { 5 {~psceq0 } } & psc[4:0] - 5'h1;
// psc[4:0] :: Management clock prescale counter
always @ (posedge wclk or posedge rst)
begin
if ( rst ) psc[4:0] <= #TP 5'h1;
else psc[4:0] <= #TP gpsc[4:0];
end
=============================================================
The idea, demonstrated in the code is fairly simple. This is a prescale
counter with variable width, depending on the value of p_clk variable.
I tried to compile the code snippet in Xilinx FPGA and got very poor
performance. I rewrote the code in VHDL, separated load and count modes
and got almost twice as better performance, comparing to original code.
So, what is going on?
Is there any specific idea about this coding style for ASIC? I mean
every async part is developed as a veriable with Go prefix, every
trigger in design seems to have only clock, data and async reset
inputs, there is no clock-enable signals and so on.
With best regards,
Vladimir S. MIrgorodsky
Article: 91014> > The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs > are also much higher. It will run faster and use less power (~50%) > than the same logic in an FPGA. > > The up-front cost for "EasyPath" is about $75,000. > The up-front cost for "Hardcopy" is about $500,000. Are you sure? I have heard figures of less than half that, but then again my memory is not what it used to be so I could be wrong :-) Hans. www.ht-lab.comArticle: 91015
> How much does it cost to produce an ASIC? Depends on the process. For .18, expect to pay $200k. > If it is already working in an FPGA, can I count on the ASIC also working? No. Lots more things can go wrong when making an ASIC. > Can I just hand the VHDL/Verilog files to the fabricator? Depends on the fab. Some will do it, some won't. For those that don't, there are plenty of design services companies that will do it for you. > Or should I change the design to take advantage of ASIC features Depends on your performance requirements. > If you have moved a design from FPGA to ASIC, how difficult was the process? Fairly easy, but that's because I've always planned ahead, and not used many FPGA specific features. That way, the only things you need to change are memories and I/Os. > What did you gain in terms of speed Virtex II Pro -7: 150MHz - .13 ASIC - 400 MHz. > power consumption? Huge amounts. FPGAs suck current like there's no tomorrow. Cheers, JonArticle: 91016
Hans wrote: > > > > The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs > > are also much higher. It will run faster and use less power (~50%) > > than the same logic in an FPGA. > > > > The up-front cost for "EasyPath" is about $75,000. > > The up-front cost for "Hardcopy" is about $500,000. > > Are you sure? I have heard figures of less than half that, but then again my > memory is not what it used to be so I could be wrong :-) I am fairly sure about the "EasyPath" cost, since that is from Xilinx's own website. I am not at all sure about the "Hardcopy" cost, since that is from Xilinx's website too, not Altera's (as I mentioned in my post). Xilinx's cost estimate may put Altera's product in an unfavorable light, but it serves them right. If they want accurate information disseminated, they should provide the information themselves. I could find no price information anywhere on Altera's website. Anyway, here is my source of information for the cost of both products: http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/overview.htmArticle: 91017
I read about SEU characteristics of Xilinx FPGA. I'm interested in comparation of MTBF data between Spartan3, Virtex-II and especially XC2C and XPLA3 PLDs and commercial sRAM of small capacity (max 512kBy). Do you know something about this issue? If I didn't worry about SEU in my recent embedded designs with XPLA3, should I worry now when I want to use Spartan3? Regards, NebojsaArticle: 91018
"Kunal" <kunal.shenoy@gmail.com> schrieb im Newsbeitrag news:1130392414.325117.45550@g49g2000cwa.googlegroups.com... > Both Xilinx and Altera has options to move to ASIC-like implementations > from FPGA designs. These chips have a lower unit cost. > > Xilinx calls it EasyPath Solution : > http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm > . > Altera calls it Hardcopy > http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp > Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less testing at the fab. may be atually partially faulty. its only tested to customer bitstream. But the silicon is 1:1 the same as the normal FPGA anttiArticle: 91019
Hi David
Th
is is for an RGB LED demo display application.
1. There will be mixing of colours done at say 3ms intervals for each colour
to stay ithin the 10ms and take avantage of persistance of vision.
2. Bits accuracy in the duty cycle is not very important since the PWM is
only for brightness control.
3. The outputs must at least be synchronized to the colour mixing intervals,
i.e. 3ms intervals. In other words, the PWM will further divide the 3ms
intervals to control brightness.
4. These will only be used in an RGB LED display application hence the only
real importance is the 10ms refresh limit.
Thank you for your input.
Peter.
"David Brooks" <davebXXX@iinet.net.au> wrote in message
news:435d7280$0$8621$5a62ac22@per-qv1-newsreader-01.iinet.net.au...
> Can you further tell us:
> 1. What pulse repetition frequency you want
> 2. How many bits accuracy in the duty cycle
> 3. Must the outputs be synchronised?
> 4. Are they to drive model-control servos? (Those often respond not to the
> average energy in the signal, but to the actual width. You can have a very
> long interval between pulses, & still have them work).
>
> Emtech wrote:
>> I have an application where I need to implement 24 or up to 32 PWM
>> outputs (8-bit) and
>> am considering using a small CPLD to handle the PWMs instead of doing it
>> all in software.
>> This does add a CPLD to the design, but frees the micro do to other
>> things.
>>
>> Any recommendations on the CPLD & CPLD size without completing the VHDL
>> first?
>>
Article: 91020Sean Durkin schrieb: > Peter Alfke wrote_ > >>No problem, not even with ten bits parallel. > > What do I do if I need 12? > > We use a lot of TI's ADS527X-ADCs, and those output 12bit-data-words > over LVDS-DDR-outputs running at 420MHz and higher. So these are 6-bit nibbles at 70MHz. Should be easy with the ISERDES. Kolja SulimmaArticle: 91021
There are several smaller companies in the so called conversion business using structured ASICs. google <fpga asic conversion> for 137K hits and more than enough players AMI, ViaASIC, Flextronic, and also some surprises in the google list like Honeywell and epson I had long forgotten about. The active ones will show up at DAC every year. For other comments, you could also peek into John Cooleys website, lots of ASIC, EDA vendor feedback there, some very -ve. When you get interested in a particular vendor, research them thouroughly. Since you mentioned cpu porting, I saw on opencores that the OpenRISC 1200 had been ViaASIC ed so I had a look at that, they reduce it down to a single via mask. They give very little performance info for the conversion though but suggest that most of the expected speed of full std cell is obtained, maybe 20% left behind. This core like most opencores was not planned for FPGA, dates back to the free ASIC IP hubris. A design planned for BlockRam FPGA should port very well to these like minded ASICs if only the mask costs can be lowered. Their kits are 300-500K $ range for HDL in, GDS out for 1 mask. There have been some poor reviews of this SW, its perhaps still early days. Not sure how they handle production and quantities, they claim 10x reduction in FPGA costs which shouldn't be too dificult if you have the volume. One thing that seems obvious is project sharing, if ten projects share 1 mask over a full large die, you could probably get 10-20 designs out of. This is something that maybe the Mosis types should switch too rather than trying to share all masks per group. But if the 10x reduction is spread over 10 projects, back to square one. What I found interesting was their macro block, something like a 1/4 BlockRam of 128 by 32 DP with around 256 logic cells each includes a FF and handful of gates. I can see right away I would need 2-4 of these for my cpu and that gives me some useful ASIC info to compare against FPGA or other full mask flows, long before I spend any time on ASIC design. When CA wakes up, somebody from Xilinx will step up to the plate and trash every other vendor. JohnArticle: 91022
John, CA is waking up, but Xilinx does not intend to "trash every other vendor". There is room for several approaches, since there are so many variables: Up-front NRE cost, time-to-market, general risk, acess to the leading-edge technology, and reprogrammability all favor FPGAs, and that's why they are growing faster than the market. Manufacturing cost per chip, speed, and power consumption favor the other approaches. By aggressively using 90 nm technology, and by incorporating larger functions, our FPGAs have gotten significantly faster and reduced their power consumption and chip area (FIFO controller, PPC, Ethernet controller, multiplier/accumulators, SerDes etc.). There is room for more than one approach, but the prevailing wind is in favor of the FPGA. Peter AlfkeArticle: 91023
Antti, But "partially faulty" yet 99.999% tested (much better than an ASIC is able to be tested) means that any faults which are not being used, don't matter. Every Altera FPGA sold has a redundant column to replace a faulty one. So, every one they sell could have a fault. But it isn't used. And it does not affect reliability (as shown by their product qual tests). Easypath has also been fully qualified by the reliability testing that is required of any device. Austin Antti Lukats wrote: > "Kunal" <kunal.shenoy@gmail.com> schrieb im Newsbeitrag > news:1130392414.325117.45550@g49g2000cwa.googlegroups.com... > >>Both Xilinx and Altera has options to move to ASIC-like implementations >>from FPGA designs. These chips have a lower unit cost. >> >>Xilinx calls it EasyPath Solution : >>http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm >>. >>Altera calls it Hardcopy >>http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp >> > > > Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less > testing at the fab. may be atually partially faulty. its only tested to > customer bitstream. But the silicon is 1:1 the same as the normal FPGA > > antti > > >Article: 91024
Jon, Great post. One comment: the 400 MHz ASIC you propose could also "suck current like there is no tomorrow" if you decide to use all low Vt transistors, and really push the speed (look at any Intel desktop CPU chip). If you just stayed with the 150 MHz number, the current could (should) be quite small, I agree. Austin Jon Beniston wrote: >>How much does it cost to produce an ASIC? > > > Depends on the process. For .18, expect to pay $200k. > > >>If it is already working in an FPGA, can I count on the ASIC also working? > > > No. Lots more things can go wrong when making an ASIC. > > >>Can I just hand the VHDL/Verilog files to the fabricator? > > > Depends on the fab. Some will do it, some won't. For those that don't, > there are plenty of design services companies that will do it for you. > > >>Or should I change the design to take advantage of ASIC features > > > Depends on your performance requirements. > > >>If you have moved a design from FPGA to ASIC, how difficult was the process? > > > Fairly easy, but that's because I've always planned ahead, and not used > many FPGA specific features. That way, the only things you need to > change are memories and I/Os. > > >>What did you gain in terms of speed > > > Virtex II Pro -7: 150MHz - .13 ASIC - 400 MHz. > > >>power consumption? > > > Huge amounts. FPGAs suck current like there's no tomorrow. > > Cheers, > Jon >
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z