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"mvetromille" <mvetromille@gmail.com> schrieb im Newsbeitrag news:b1bb368c3bf24200aae1c08000ca3267@localhost.talkaboutelectronicequipment.com... > Hello! I instantiated SDRAM memory in an EDK project, but I don't know what > I have to do in order to boot from it. I want to store my instructions and > data into it. Does anyone can help me? > > Thank you! > Melissa > SDRAM is VOLATILE memory so you can not boot from it as it does not contain any data. you need some nonvolatile memory for booting, so you can copy this data to the SDRAM and then start execution from SDRAM anttiArticle: 90976
Bevan Weiss schrieb: > Kolja Sulimma wrote: > >> Bevan Weiss wrote: >> >>> Getting single cycle high speed multipliers is a very challenging >>> prospect, and one which much research is still ongoing. >> >> Actually, if you cannot do full custom circuit optimizations >> (e.g. because you do standard cell design or because you are using >> LUTs in an FPGA) swapping wires is the only possible structural >> optimization. All other multiplier transformations can be reduced to >> swaps. >> >> An extremely nice property of swapping wires is, that it can be done >> after placement. This is such a huge advantage that we were able to beat >> sophisticated multiplier generators with a simple greedy algorithm when >> applying it after placement: >> http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf >> > > I was referring to custom design, not the use of standard cells or > FPGAs. It is certainly obvious that if you can't design your cells from > scratch then you're just arranging the cells that you have available. What is that supposed to mean? Even if your standard cell library consists of only a NAND-gate in one size there are still many degrees of freeedom in circuit design. For many design problems there are architectures that trade off the number of cells for power or speed. Not so for single cycle multipliers. For any practicle multiplier size the number of 1-bit adders is fixed and there exists a complete set of transformations to automatically reach all possible setups even after placement. > I'm not sure if it can be reduced to swapping wires however, I am sure. RTFP. There is a proof in there. though certainly in FPGAs where the entire logic design is already laid out and > the only configuration possible is via routing changes then this is the > case. This does not make the problem any easier. Well, mapping for FPGAs is easier, but that is trivial for multipliers anyway. For placement it does not really matter a lot what the grid is and routing actually gets more difficult when you can only use a fixed set of connections. Kolja SulimmaArticle: 90977
Hal Murray wrote: > >So I'm just asking, is possible to store 16 words in a 16 words deep > >FIFO? Or "Deep N" means that I can only store N-1 words? > > It's possible, but not simple. Keeping track of 0 to 16 words > in a FIFO requires 17 states. That won't fit in 4 bits. OK. Is this true also for synchronous FIFO? In this case FIFO Generator announce a depth equal to 16Article: 90978
On a sunny day (Tue, 25 Oct 2005 20:54:32 -0500) it happened "Steven J. Hill" <sjhill@realitydiluted.com> wrote in <435EE1D8.5080205@realitydiluted.com>: >Eric Smith wrote: >> Thirty hour and several hundred dollars later, it's working great. Details in my >> blog entry: >> http://whats.all.this.brouhaha.com/?p=149 > >The only thing I did not see you try, which I am going to try next is >using Wine on my dual Opteron system to see if things will work. There is a new Wine-0.9 now on www.winehq.com Have downloaded source, but had no time to play with it yet. _________________________________________ Usenet Zone Free Binaries Usenet Server More than 140,000 groups Unlimited download http://www.usenetzone.com to open accountArticle: 90979
Ok, but how do I do this? I don't know how to manipulate SDRAM. Can you help me? Thank you! MelissaArticle: 90980
I have little bit of experience..let me know what exactly do u need... -- Parag BeerakaArticle: 90981
When I use a function that returns a boolean in a 'If' condition, ModelSim reports that "Condition Coverage ignoring this condition". Is it a limitation in ModelSim?Article: 90982
is there possobility to use 2 clock's in the same state machine and how? thank'sArticle: 90983
If the two frequencies are not synchronously related, this becomes a very tricky proposition, since you must assume any imaginable phase relationship between the two clocks. If one clock is a fraction of the other, and stays synchronous with the faster frequency, then you have no problem. Peter Alfke dimon1977 wrote: > is there possobility to use 2 clock's in the same state machine and > how? > thank'sArticle: 90984
Gray coding can deliver clockless state machines. The big question you have to ask yourself is whether the 2 clocks can each want to transition the state machine to a different state within a few nanoseconds. Do you want either clock to advance the machine? Do you want some states to transition with one clock and different states with the other clock? You really have to get straight in your mind what your real needs are before you ask us to help you get it straight. "dimon1977" <dimon1977@gmail-dot-com.no-spam.invalid> wrote in message news:CZadnTapwqBLNsLeRVn_vA@giganews.com... > is there possobility to use 2 clock's in the same state machine and > how? > thank's >Article: 90985
Gray coding is great for the glitchless decoding of counters, but it does not help in the more general case of a state machine (that is not just a counter). If the code change is more than just an increment or decrement, then multiple bits are likely to change, and the Gray decoding advantage is lost. Peter AlfkeArticle: 90986
My use of the term "Gray coding" for state machines refers the the general form of a number of states with specific coding (not one-hot) with 1 bit difference between any two state transitions. This does put strong constraints on the user to develop a scheme with the proper state coding and proper number of states to go through a sequence, change only one bit at a time, and return to the sequence with the proper state-bit coding. This was not intended to be confused with Gray code counters. "Peter Alfke" <peter@xilinx.com> wrote in message news:1130346407.681232.146020@g49g2000cwa.googlegroups.com... > Gray coding is great for the glitchless decoding of counters, but it > does not help in the more general case of a state machine (that is not > just a counter). If the code change is more than just an increment or > decrement, then multiple bits are likely to change, and the Gray > decoding advantage is lost. > Peter Alfke >Article: 90987
<james.r.lamb@comcast.net> wrote in message news:1129832667.527884.17160@g44g2000cwa.googlegroups.com... > Has anyone had any luck programming the Spartan-3 Starter board RS-232 > using C? > > I am trying to send/receive/monitor all data going over COM1 > > Thanks > You can find some examples into Xilinx site, or you could see into uart folder driver. MarcoArticle: 90988
Peter Alfke wrote:
>Gray coding is great for the glitchless decoding of counters, but it
>does not help in the more general case of a state machine (that is not
>just a counter). If the code change is more than just an increment or
>decrement, then multiple bits are likely to change, and the Gray
>decoding advantage is lost.
>Peter Alfke
>
>
>
Peter, state machines can indeed be "Gray coded" but it is not the same
as a Gray code counter. A more proper description might be a state
machine that is designed so that all the state transitions have a
hamming distance of 1, meaning that only one flip-flop changes state for
each transition. Also, each state should only have one single bit
decision variable in order for it to be reliable. This type of design is
pretty much required for async (clockless) state machines. It is fairly
easy to do for small simple machines, but can get very difficult as the
number of branches in the machine increase. It often also requires some
extra states so that any loops in the state machine can get close
without any states that have more than one bit changing state.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90989
Antti Lukats wrote:
>"mvetromille" <mvetromille@gmail.com> schrieb im Newsbeitrag
>news:b1bb368c3bf24200aae1c08000ca3267@localhost.talkaboutelectronicequipment.com...
>
>
>>Hello! I instantiated SDRAM memory in an EDK project, but I don't know
>>
>>
>what
>
>
>>I have to do in order to boot from it. I want to store my instructions and
>>data into it. Does anyone can help me?
>>
>>
>>
>
>
>
You need to design (or instantiate some one else's) SDRAM controller.
Working SDRAM is not trivial; it requires a state machine to sequence
the controls, not only to access the data, but also to refresh the
memory and even to properly initialize the memory before it can be
accessed. You can start by reading the data sheet for the particular
SDRAM that is on the board. There may be an SDRAM controller in the IP
that came with the board, perhaps in one of the example designs.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90990John_H wrote: > My use of the term "Gray coding" for state machines refers the the general > form of a number of states with specific coding (not one-hot) with 1 bit > difference between any two state transitions. This does put strong > constraints on the user to develop a scheme with the proper state coding and > proper number of states to go through a sequence, change only one bit at a > time, and return to the sequence with the proper state-bit coding. This was > not intended to be confused with Gray code counters. > We have done that, and "strong constraints on the user" is well put!. You can add dummy/extra states in many designs, to satisfy the One-Delta need, as many state paths are less time-critical. Normally a RESET is considered not needing to meet the One-Delta, tho you can arrange a dominant IDLE state to have a One-Delta reset. For the OPs question, of two clocks, it may be possible to use a CLK and CLK_EN ? -jgArticle: 90991
Kolja Sulimma wrote: > Bevan Weiss schrieb: >> Kolja Sulimma wrote: >> >>> Bevan Weiss wrote: >>> >>>> Getting single cycle high speed multipliers is a very challenging >>>> prospect, and one which much research is still ongoing. >>> Actually, if you cannot do full custom circuit optimizations >>> (e.g. because you do standard cell design or because you are using >>> LUTs in an FPGA) swapping wires is the only possible structural >>> optimization. All other multiplier transformations can be reduced to >>> swaps. >>> >>> An extremely nice property of swapping wires is, that it can be done >>> after placement. This is such a huge advantage that we were able to beat >>> sophisticated multiplier generators with a simple greedy algorithm when >>> applying it after placement: >>> http://eis.eit.uni-kl.de/eis/research/publications/papers/iccd04.pdf >>> >> I was referring to custom design, not the use of standard cells or >> FPGAs. It is certainly obvious that if you can't design your cells from >> scratch then you're just arranging the cells that you have available. > > What is that supposed to mean? > Even if your standard cell library consists of only a NAND-gate in one > size there are still many degrees of freedom in circuit design. > For many design problems there are architectures that trade off the > number of cells for power or speed. > Not so for single cycle multipliers. For any practice multiplier size > the number of 1-bit adders is fixed and there exists a complete set > of transformations to automatically reach all possible setups even after > placement. So you're saying it makes no difference if booth encoding is used, or any form of carry ripple reduction? That it's all just a rearranging of wires? Surely not, using a booth encoder requires different components to a simple ripple counter and so has broken that theory.Article: 90992
I think this thread has served the purpose of being a dire warning against mixing unrelated clocks in one state machine. A naive design will inevitably get you in trouble. Really smart designers may be able to tip-toe through the tulips... Hats off to them! Peter AlfkeArticle: 90993
Sorry I am late in responding. I have been able to get the FSL to work with the control bits. As mentioned in other posts, the FSL_Error bit is "sticky" and must be manually reset. This can be done with a macro: #define clearmatcherror asm volatile ("msrclr r12,16")
I just upgraded to EDK 7.1 and the new compiler is complaining about the FSL access macros that were working with 6.1?? Has anyone found a fix for this?
Thanks, Terry
Article: 90994Hello everyone, I am trying to transfer data between on board ethernet PHY and the PC. For that i am implementing ethernet packet generator in the fpga. The MII interface on the fpga has transmit data bus of width 4 bits. So i am sending 64 bytes of frame from the fpga with the most significand bit transmitted first. As you all know ethernet frame consists of preamble,startframe,destination ad,source ad,length/type,data,crc Is this what each block consists of preamble - 7 bytes - x"5"; startframe - 1 byte -x"5d"; destination - 6 bytes - PC mac address source - 6 bytes -- any choice of fpga mac.(any value) length/type - 2 bytes -- "0000_0000_0100_0000" data - --38 bytes -- any value crc - 4 bytes 2) Is CRC implemented on only data or on whole frame? 3) Can anyone guide me on how crc is computed? 4) If CRC is wrong, will the PHY still transmit the data onto the PC. I would request you to please answer my questions as soon as possible. thanks ashwinArticle: 90995
Thank you Joseph, I did what you suggested and did an example program. I am using LVDS inputs and want 7:1 serdes. The placement seems to be somewhat what you said in that the master iserdes gets placed right next to the _p pad. The _n pad shows a single connection going to the _p pad. However the slave serdes seems to be placed willy-nilly, not in the same tile, and sometimes mixed with a master iserdes of a different lvds signal in the same tile. Is there something you are doing to put the slave iserdes in the same tile as the master, like a constraint? Nice web site there. Thanks, Brad Smallridge aivision.com > If you need a slave ISERDES, you 'borrow' the ISERDES from the other IOB > in the tile. In that case, the other IOB has no ISERDES available. If you > have single ended inputs, you couldn't have two 7-bit ISERDES on 2 input > pads in the same tile. If you have LVDS inputs you're OK because the 2 > input pads form 1 internal signal that can feed to the 2 ISERDES in > master-slave configuration. > > It's pretty easy to see if you make up an example design, place and route > then look at the results with FPGA editor. > --- > Joe Samson (jsamson@) > PixelVelocityArticle: 90996
ashwin wrote:
> 2) Is CRC implemented on only data or on whole frame?
The fcs field is calculated for the whole frame on transmit.
It is checked using the whole frame + fcs on receive.
> 3) Can anyone guide me on how crc is computed?
Here's how it is checked
http://groups.google.com/groups?q=vhdl+crc_shift
> 4) If CRC is wrong, will the PHY still transmit the data onto the PC.
If it didn't you would never see a bad fcs.
> I would request you to please answer my questions as soon as possible.
I'm typing as fast as I can, however,
that question has increased the response time slightly.
-- Mike Treseler
Article: 90997I designed a SM which can run at 30Mhz below my target frequency(that's what XST shows after synthesis (no PAR). It is a pretty big SM(a lot of states, input, output and internal signals) and I have to optimize it somehow. My question is what influences the timing so I can concentrate on it. I have a Mealy type SM - 2 processes: 1st - synch to CLK. the internal signals and outputs are assigned here 2nd - sensitive to all inputs, internel signals(from 1st process) and current state. I am using one-hot encoding for the SM. ideas ;)?Article: 90998
I suppose you use PPC. 1. For real hardware - for booting you use the boot files from edk. They are by default there. After that you can use PPC compiler/debugger to compile and load the code in the memory and execute the program. 2. for simulation - as far as I remember - the C program is "translated" to VHDL code(binary 0 and 1) which is placed in the memory. This is the basic idea - i did this a long time ago and some of the things may be not correct. Look for tutorials (that's what I did ;) )Article: 90999
"Brian Davis" <brimdavis@aol.com> wrote in message news:1130329497.077343.277450@g43g2000cwa.googlegroups.com... > Symon wrote: >> >> He gave me these links for you, bless his cotton socks. >> > Might those be Argoogle socks? > As a Janner myself( http://en.wikipedia.org/wiki/Janner ) I think I have the answer to the local football team's problems. Plymouth Argoogle. Brin on Chelsea! Sorry, 'Bring'! :-) Best, Syms.
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Compare FPGA features and resources
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