Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
panteltje@yahoo.com wrote: > I had a look at that, and then linked to the Eclipse site, and looked > at that. > Honestly :-) if withing 10 minutes or so I cannot figure out what > exactly it does > (Eclipse) and how it works and [how it] could speed up or improve the > whole process, > then I am out of there! > IBM must have dumped it into the public domain for the same reason, and > then > they can claim 'millions of dollars donations to open source'..... Better tell Altera and Xilinx quick - after all, both of them use Eclipse as the basis for their soft cpu IDEs. In fact, better tell the java programming world that their most popular IDE is not good enough for serious use! And IBM did not "dump it into the public domain" - they re-licensed it as open source, which is a completely different thing. Big, resource-heavy IDEs may not be your thing - but if it is, there are no general-purpose IDEs to beat Eclipse, which is why even Borland are supporting it.Article: 91476
Hello, is there any way to rotate a selected group in the Symbol Editor? Thanks and greetings UdoArticle: 91477
Hal Murray wrote:
>>for ceramic packages i bet the times are over forever.
>>
>>
>
>What are military/space people using these days?
>(I thought that was the reason for ceramic packages in
>the old days.)
>
>
>
The last space project I was on (earlier this year) was to use a Virtex2
in a ceramic column grid array. It's basically a ceramic BGA with
solder columns instead of balls. I believe the reasoning behind the
columns is that they will allow more differential thermal expansion
before the stress pops the part off the board. It is still a ceramic
package, but not in a form factor that is any easier for a hobbyist to
use than a bga package, and it is a heck of a lot more expensive.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91478Has anyone been able to get the ML402's DDR SDRAM running with a MIG-generated DDR controller, as opposed to the EDK PLB DDR controller? Xilinx is unable to confirm this works... there's a thread in this group from July with some ML401 MIG questions, but no resolution. My group is interested in using the 402 in a non-SoC application, so we're sort of wondering if MIG has been proven here. Thanks!Article: 91479
gallen wrote: > Eclipse is a Java IDE. It is written in Java and it is for making Java > programs. There are extensions(C/C++, verilog, etc) that allow it to > edit other things with syntax highlighting and "intellisense," but they > are nowhere near as complete as the Java portion. > > I have tried the eclipse verilog extension. Quite frankly, it just > didn't come anywhere close to being as useful as verilog-mode for > emacs. It may be better some day, but right now, I recommend using > emacs and verilog mode. Agreed. I downloaded Eclipse because I was looking for a Verilog editor that was "better" than emacs. By "better," I mean a better indent engine. IMHO, the Verilog mode for emacs is not up to the same high level as the VHDL mode. Anyways, Eclipse was frustrating (and this is coming from an emacs bigot who climbed emacs' steep learning curve) and I couldn't figure out how to get it to do proper syntax highlighting and indenting. So I deleted it and went back to emacs. And life was better. -aArticle: 91480
On a sunny day (7 Nov 2005 20:53:56 +0200) it happened David Brown <david@westcontrol.removethisbit.com> wrote in <436fb0d4@news.wineasy.se>: >panteltje@yahoo.com wrote: >> I had a look at that, and then linked to the Eclipse site, and looked >> at that. >> Honestly :-) if withing 10 minutes or so I cannot figure out what >> exactly it does >> (Eclipse) and how it works and [how it] could speed up or improve the >> whole process, >> then I am out of there! >> IBM must have dumped it into the public domain for the same reason, and >> then >> they can claim 'millions of dollars donations to open source'..... > >Better tell Altera and Xilinx quick - after all, both of them use >Eclipse as the basis for their soft cpu IDEs. In fact, better tell the >java programming world that their most popular IDE is not good enough >for serious use! > >And IBM did not "dump it into the public domain" - they re-licensed it >as open source, which is a completely different thing. Big, >resource-heavy IDEs may not be your thing - but if it is, there are no >general-purpose IDEs to beat Eclipse, which is why even Borland are >supporting it. java... everything ten times slower. Now if it is only GUI stuff PERHAPS it makes no difference, but if anything goes through it it would explain a lot why iverilog is so fast by itself as compiler (for testing code) and in combination and those other stuff you are talking about so slow. Borland is dead right? java is half dead and slow as hell, no 'resource heavy IDE' is NOT my thing, on the contrary. That is more the domain of 'have no clue what to do' programmers. Cheers JanArticle: 91481
Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding! (begin/end case/endcase) -EliArticle: 91482
On a sunny day (Mon, 07 Nov 2005 15:28:26 -0500) it happened Eli Hughes
<emh203@psu.edu> wrote in <dkodda$1f9c$1@f04n12.cac.psu.edu>:
>Check out the Zeus Editor. www.zeusedit.com
>
>
>Is is very lost cost and now supports Verilog files with nice code
>folding! (begin/end case/endcase)
>
>-Eli
<rant>
I do not get this, I have written perhaps a million or more lines of C code,
and quite some lines of verilog code now, and I use 'joe' editor in Linux.
It has NO special mode for C, no 'syntax coloring', none of these things,
ident: yes.
It takes .0000Xms to start and has wordstar like keys (for the old CP/M guys),
Even emacs takes ages to start compared to it.
In my_view(C) if you cannot see '{' and '}' or align it, or 'wire',
or 'module' or ANY language specific word, then you are not suited
as programmer.
Now SOME programmers in C leave out all spaces: var=a+2/4*36;
Do not do that, write as a natural language, use separate lines for complicated
things, we do not have to worry about space: memory is cheaper these days.
(in the beginning when programming we even combined bits in an integer in asm,
no we use 64 bits as flag...)
I do NOT want to start a [verilog] editor war, just point out ways to less suffering.
</rant>
Article: 91483
Jan Panteltje wrote:
> On a sunny day (Mon, 07 Nov 2005 15:28:26 -0500) it happened Eli Hughes
> <emh203@psu.edu> wrote in <dkodda$1f9c$1@f04n12.cac.psu.edu>:
>
>
>>Check out the Zeus Editor. www.zeusedit.com
>>
>>
>>Is is very lost cost and now supports Verilog files with nice code
>>folding! (begin/end case/endcase)
>>
>>-Eli
>
>
> <rant>
> I do not get this, I have written perhaps a million or more lines of C code,
> and quite some lines of verilog code now, and I use 'joe' editor in Linux.
> It has NO special mode for C, no 'syntax coloring', none of these things,
> ident: yes.
> It takes .0000Xms to start and has wordstar like keys (for the old CP/M guys),
> Even emacs takes ages to start compared to it.
> In my_view(C) if you cannot see '{' and '}' or align it, or 'wire',
> or 'module' or ANY language specific word, then you are not suited
> as programmer.
> Now SOME programmers in C leave out all spaces: var=a+2/4*36;
> Do not do that, write as a natural language, use separate lines for complicated
> things, we do not have to worry about space: memory is cheaper these days.
> (in the beginning when programming we even combined bits in an integer in asm,
> no we use 64 bits as flag...)
> I do NOT want to start a [verilog] editor war, just point out ways to less suffering.
> </rant>
>
Tools are meant to make life easier. Yes you can pound nails with a
rock. You could build a house with it and get very good at it. But
then again, its also really nice to have a compressor and a framing
nailer. Both perform the same operation, but one lets you get things
done faster.
<quote>
In my_view(C) if you cannot see '{' and '}' or align it, or 'wire',
> or 'module' or ANY language specific word, then you are not suited
> as programmer.
</quote>
This is somewhat arrogant. Yes, I can use some crappy UNIX text editor.
But I choose to use something to make like life a little easier. Why
would I not want to use new tools? My vision is bad enough. I like
having things highlighted. It also makes things easier for others to
look at code that they are not familiar with.
Thats like saying that a Doctor is a a good Doctor is he Doesn't use the
same tools from 30 years ago. Ya, they worked at the time but there are
much better tools now that make operations easier.
-Eli
Article: 91484In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: > > as example VQ100 is really nice package very thin, so largest LUTs you get > in VQ100 is S3e. etc.. I realize that there are people out there that need the 1000+ pin packages that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs would come in VQ100/144 packages. Personally, I'd love to have the capacity, but I really dont need (or want) the complexity and raw bandwidth of having to deal with several hundred (or a thousand) pins... -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 91485
Tobias Weingartner wrote: > In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote: >> as example VQ100 is really nice package very thin, so largest LUTs you get >> in VQ100 is S3e. etc.. > > I realize that there are people out there that need the 1000+ pin packages > that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs > would come in VQ100/144 packages. Personally, I'd love to have the capacity, > but I really dont need (or want) the complexity and raw bandwidth of having > to deal with several hundred (or a thousand) pins... Just doesn't work that way unfortunately. The large fabric requires a large chip package to contain it. If you were to reduce the number of pin outs, the it would actually require an even larger chip package, as you would now have to add additional multiplexers etc to control the routing to the pins. It would certainly be nice to have the additional logic in a smaller chip, but sorry to say this will only happen with geometry scaling, such as transition to 90nm and possibly to 65nm in the near future.Article: 91486
Benjamin Menküc wrote: > Hi, > > I have looked in the fpga editor. My VHDL code really uses the FFs > inside the IOBs. > > However I saw, that my clock output goes directly to the pad inside the > IOB, furthermore it doesn't look like a good routing inside the FPGA. > However the lvds_clk Signal in that reaches the IOB where the clk pin is > located is named "lvds_clk_OBUF" so I guess the compiler put an OBUF on > it :) I remember that there was an OBUFG for clocks... Is it better to > use this instead? If yes, how do I implement that in VHDL? > > Antti said "use DCM to adjust phy clock phase". How do I do that in my > case? > > I have a mistake in my last post: My output definition in the entity of > the design is lvds_clk. > > Somewhere in the code I do just lvds_clk <= pixel_clk. You probably want to use an FDDRRSE (DDR Flip-flop) to forward the clock, as this means that the clock signal to the output is routed properly over global clock resources - if you are trying to route it directly out, you get messy results (local routing etc). You may also want to look at the output of your static timing analyser to determine what your output timing actually is. JeremyArticle: 91487
Tony Acquah wrote: > Hello Everyone, > I am working on designing a digital modulator that will implement QAM > on FPGA. > > The FPGA will be programmed in VHDL to modulate an input > signal(maybefrom a function generator) > > A D/A converter will convert the digital signal to an analog one that > canbe transmitted. > > Anyway, what I need now is algorithm and/or VHDL code that will carry > out the QAM on FPGA. > > Any help is greatly appreciated > > Anthony Which form of QAM do you want to use? This could be as simple as a look up table for most small inputs, I'd probably use it for 16-QAM and up to 256-QAM. Which is probably all you're going to target anyways. If this is the only thing that you'll have in the chip it's probably worth adding in some FEC coding as well. This would allow you to use TCM, and hence provide slightly better performance under noisy conditions. I note that you want to use a function generator to create the input waveforms. This would generally be a serial train of digital pulses, and perhaps a clock signal (or the clocking may be intrinsic to the digital pulses ala Manchester encoding). The serial to parallel converter is simply a shift register, which is clocked in x number of times, then read out in parallel, then clocked in an additional x times etc. There is probably a standard block for this that would be faster in most cases than a manual implementation. There is likely a standard block for the ROM to use as the QAM lookup table. And if you wanted to implement TCM then I'm sure there's some code around for a viterbi algorithm, and the convolutional generator.Article: 91488
Thanks for the friendly remarks. In case people want to know what Marketing says about the imminent S3e evaluation boards (including pictures... ) here it is: http://web/xroads/news/articles/spartan3board/index.html Cheers Peter AlfkeArticle: 91489
Bevan Weiss wrote: > Just doesn't work that way unfortunately. The large fabric requires a > large chip package to contain it. If you were to reduce the number of > pin outs, the it would actually require an even larger chip package, > as you would now have to add additional multiplexers etc to control > the routing to the pins. No, it wouldn't need any extra multiplexers. They would just not bond out as many of the pads to pins. They already do that to offer several package options for each FPGA. The problem is that you don't save any significant cost by having the same size package with fewer balls or pins. So if the die size requires a package 20mm on a side, it may as well have more than 350 balls, even if some customers don't end up using all of them.Article: 91490
"Peter Alfke" <peter@xilinx.com> writes: > Thanks for the friendly remarks. > In case people want to know what Marketing says about the imminent S3e > evaluation boards (including pictures... ) here it is: > > http://web/xroads/news/articles/spartan3board/index.html I'm guessing that it's a Xilinx internal URL? It certainly doesn't work here, even if I prepend a www.xilinx.com, or put that in place of "web".Article: 91491
Hi Anthony,
This is probably what you are not looking for, but our company's Xilinx
(TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core does come with a
PCI testbench that is probably much better than Xilinx LogiCORE PCI Ping
reference design's simple PCI testbench.
We had to develop this pretty extensive PCI testbench (Ping reference
design's testbench was a joke for our purposes.) in order for us to
stress BDS XPCI PCI IP core against Xilinx LogiCORE PCI.
BDS PCI Testbench that comes with the BDS XPCI PCI IP core consists of,
* PCI Arbiter model
* Host to PCI bridge emulator
* 32-bit and 64-bit target PCI device simulation models
BDS PCI Testbench's PCI Arbiter model can handle up to 8 PCI
initiator (master) devices.
The only limitation it currently has is that it cannot perform hidden
arbitration. (Hidden arbitration is GNT# being awarded to another device
during a transaction.)
Host to PCI bridge emulator is something similar to
microprocessor (CPU) inside a computer.
Here the designer writes series of HDL code to access the PCI bus, just
like what programmers will do when writing a program to directly access
the PCI device.
Host to PCI bridge emulator comes with the following Verilog tasks and
VHDL procedures.
Configuration_Read
Configuration_Write
Single_Read_32
Single_Write_32
Burst_Read_32
Burst_Write_32
These tasks and procedures can be called, for example, with an address
parity error and a certain bit flipped and/or certain number of wait
states inserted.
Burst_Read_32 and Burst_Write_32 are probably the most useful in this
Host to PCI bridge emulator that allows the designer initiate a long (up
to 1024 transactions) PCI transaction with user specified wait states,
parity error condition, and which bit to flip in case of a parity error
condition for each data transferred.
If the designer couples Burst_Read_32 and Burst_Write_32 with a random
number generator ($random in Verilog), it should be able to perform a
random wait state insertion test against a target device.
32-bit and 64-bit target PCI device simulation models are
target only PCI devices that can be programmed to act in certain ways.
For example, it can be programmed to perform five retries, accept only 3
data transfers, and then terminate the transaction with Disconnect
without Data. (Or Disconnect with Data.)
It can also be programmed to generate parity error every several
transfers during a read transfer with the bit being flipped specified.
32-bit and 64-bit target PCI device simulation models are very effective
when debugging an initiator device because initiators need to be able to
handle retry and wait state being inserted randomly, and still function
perfectly.
The current shortcomings of BDS PCI Testbench are the following.
* Currently cannot handle hidden arbitration
* Currently no one can guide the arbiter to behave in a certain way
* Cannot handle interrupt in the way real computers handle interrupt
* It doesn't come with a PCI protocol checker
* It doesn't come with a PCI bus monitor
* 64-bit version of Host to PCI bridge isn't ready yet
Currently, only the Verilog version of the BDS PCI Testbench is ready,
and is in the process of being ported to VHDL.
Since you mentioned that you already have Xilinx LogiCORE
PCI32, you obviously don't want the BDS XPCI PCI IP core.
Instead, we can sell (license) you the BDS PCI Testbench only without
the BDS XPCI PCI IP core.
We now have a introductory special going on for BDS XPCI32 PCI IP core
where the BDS XPCI32 PCI IP core commercial perpetual license version
normally costs $3,000 for domestic customers/$3,600 for foreign customers.
But because of the introductory special, we offer it for $2,000
domestic/$2,400 foreign.
Since you want the BDS PCI Testbench only, we can offer the BDS PCI
Testbench for $1,000 domestic/$1,200 foreign as part of the introductory
special.
In addition to that, we still offer BDS XPCI32 PCI IP core and BDS
XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) for non-commercial,
non-profit, personal use for $100 and $200, respectively.
For more information, visit Brace Design Solutions website at
http://www.bracedesignsolutions.com.
Kevin Brace
Anthony Ellis wrote:
> As a licensed user of the Xilinx PCI32 core, where does one get a more comprehensive PCI testbench (stimulus generator) than what comes with the Xilinx PING example.
>
> Thanks Anthony
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
Article: 91492
The coder is just a remapping of the input I and Q bits to the IQ
plane. It is a straight-forward mapping whch usually does not need a
table. For example, QAM64 uses 6 bit symbols. 3 bits each specify I
and Q independently. Those 3 bits take on values +/-1, +/-3, +/-5 and
+/-7. There will also need to be a nyquist filter to limit the spectral
footprint and a modulator. If desired, there may also be a
convolutional encoder preceding the symbol conversion to I and Q.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91493
Tobias Weingartner wrote:
>In article <dkmrjm$cg8$1@online.de>, Antti Lukats wrote:
>
>
>>as example VQ100 is really nice package very thin, so largest LUTs you get
>>in VQ100 is S3e. etc..
>>
>>
>
>I realize that there are people out there that need the 1000+ pin packages
>that large-scale FPGAs offer... but I do wish that 2-5 million "gate" FPGAs
>would come in VQ100/144 packages. Personally, I'd love to have the capacity,
>but I really dont need (or want) the complexity and raw bandwidth of having
>to deal with several hundred (or a thousand) pins...
>
>
>
Unfortunately, the size of the cavity in those small packages is far too
small to fit the die for the high density parts, and even if it did fit,
you may have power dissipation issues as well.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 91494
I just found this article by accident, and haven't seen this information
widely publicized:
http://www.esp2000.ro/articol.php?id_ar=2850
Summary:
There won't be a BaseX version of 8.1i. However, BaseX customers still
in-warranty will be offered an upgrade to full ISE Foundation for $1495.
Alternatively, they can transition to WebPack 8.1i with no loss of
functionality.
WebPack 8.1i will still be available at no charge, and will have all the
features that BaseX had. In particular, it will support all the
devices formerly supported by BaseX, and will also now include the
FPGA Editor, ISE Simulator Lite, and CORE Generator.
Disclaimer: that's just what I found in the article, and I have no idea
how accurate the information is.
Eric
Article: 91495I'm looking forward to see what I can play with. For the moment I'm most interested in what the expansion connectors will be (manufacturer & pinout, approximate at least). My biggest hope is that it will be .../spartan3eboard/index.html. "Peter Alfke" <peter@xilinx.com> wrote in message news:1131402065.556242.226900@g49g2000cwa.googlegroups.com... > Thanks for the friendly remarks. > In case people want to know what Marketing says about the imminent S3e > evaluation boards (including pictures... ) here it is: > > http://web/xroads/news/articles/spartan3board/index.html > > Cheers > Peter Alfke >Article: 91496
On Mon, 07 Nov 2005 15:28:26 -0500, Eli Hughes <emh203@psu.edu> wrote: >Check out the Zeus Editor. www.zeusedit.com > > >Is is very lost cost and now supports Verilog files with nice code >folding! (begin/end case/endcase) > >-Eli I use UltraEdit. Version 11.20 opens in less than 2 seconds, can open a project of about 120 files in ~25 seconds, supports about a zillion languages, including Verilog, and does syntax coloring, code folding, etc. (I even have syntax coloring for Xilinx UCF files.) At $39.95, it costs the same as Zeus. And when you report a bug, they fix it, quickly. Dollar for dollar it's the best editor I've ever used. I have no financial interest in the company; I'm just a satisfied customer. Bob Perlman Cambrian Design WorksArticle: 91497
Strange request but I'm looking for an fpga board that pretty much only has an fpga (perferably xilinx because i've only worked with xilinx so far) a prom and just a whole lot of i/o pins that are easily accessible. I've done all i can on my protoboard (digilent spartan 3 board) and now i need to move to a more finished device. Problem is designing such an intricate pcb (espically with bga) for someone who hasn't done bga stuff before but requires many i/o pins and have never done a board more than 2 layers is leaving me a little challenged. So I'm hoping a small board that will give me most of the I/O's in headers would be available, but as of yet I haven't found any. Does any know any that exsists? Thank you Keith WakehamArticle: 91498
After clicking Applications and making active one, and only one, of the many software examples for the ml403_emb_ref_mb directory, I then go to tools - update bitstream, which I believe is suppose to modify the download.bit file with the new software. Although it doesn't and when I click on download the VGA shows what it originally has and the pushbuttons stop working, so I would assume that the download.bit file that got downloaded is the original bootloop program that does nothing. So how do I make a change to one of these programs and download it? I am also getting a cryptic Nothing to be done for 'init_bram' message. Brad Smallridge aivision dot comArticle: 91499
Eric,you are right. My mistake. Just wait a few days more... Peter
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z