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>Strange request but I'm looking for an fpga board that pretty much only >has an fpga (perferably xilinx because i've only worked with xilinx so >far) a prom and just a whole lot of i/o pins that are easily >accessible. You probably want some ground pins in there too. Is the Spartan 3 big enough for your needs? It's got quite a few I/O pins available. If you need more pins, can you do some pin sharing with external logic? Either a multiplexor for input signals, or a bank of registers with clock enables for output signals. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91501
Hello, I'm trying to force a long logic delay in a Xilinx FPGA using a chain of inverters. However, these seem to get optimised out of the design. Can someone tell me how to specify that certain signals are not to be optimised? I'm using Xilinx ISE 6.3 and an XC2V250 FPGA. Regards, Dave.Article: 91502
I'm looking for some suggestions/recommendations with CPLD's and development software. I'm new to CPLD's and a couple projects of mine will involve redesigning existing "though hole" hardware using a CPLD. I've researching some Xilinx products, and believe the 9500 series will do everything I need, as my needs really aren't that great. My only issue with the ISE software is I need to recreate all the TTL IC logic from scratch, which will prove to be very time consuming. I was hoping to find a design package that would already have existing "groups" of TTL logic designed so I won't have to take as much time with the schematic design and layout. For example in ISE it took me about 15 minutes just to draw the logic to a 74LS245. Only took me 3 minutes to "wire" it up. Any recommendations on other companies, other software and your experiences with them would be appreciated. Thanks for your time. Henry GSE-Reactive.com My email is listed on the site if you wish to contact me directly.Article: 91503
Right-click on the project name and make sure 'Mark to Initialize BRAMs" is ticked. Kunal@XilinxArticle: 91504
On 7 Nov 2005 02:34:40 -0800, "nezhate" <mazouz.nezhate@gmail.com> wrote: >Hi all, >Can anyone tell me why this occurs : "when synthetizing we get a good >results (time/area) by using an adder contained in the fpga circuit and >when we use an adder that can be manually designed, we get a less >performances (time/area) " ? >Thanks. The synthesis software knows more about the target FPGA than whoever is doing the manual design. If the manual designer learnt the details of the structure of the FPGA, then the manual designer could equal the results of the synthesis software. For the case of an adder, it would be rare that the manual designer could do better than synthesis. For other more complex structures, the manual designer could do better but would require detailed understanding of the target FPGA. =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 91505
>The synthesis software knows more about the target FPGA than whoever >is doing the manual design. If the manual designer learnt the details >of the structure of the FPGA, then the manual designer could equal the >results of the synthesis software. For the case of an adder, it would >be rare that the manual designer could do better than synthesis. For >other more complex structures, the manual designer could do better >but would require detailed understanding of the target FPGA. If you are pushing the envelope at all, you probably need that detailed understanding so you can do a sanity check on the compiler. If it isn't doing a good job you may want to tweak your code so the compiler will recognize your pattern, or maybe just instantiate what you want. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91506
Hi, How can I create an IPCORE from my VHDL code. I want to be able to distribute my newly created block without given away my code. Ideas? Thanks.Article: 91507
Hi rha_x, You should consider turning your VHDL code into an EDIF netlist by synthesizing it. Kevin Brace rha_x wrote: > Hi, > How can I create an IPCORE from my VHDL code. I want to be able to > distribute my newly created block without given away my code. Ideas? > Thanks. > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 91508
When you say logic delay, do you mean you want to increase delay in the same clock or do you just want to add delays? For just delays, you can add as many flip-flops as the number of clock-delays you need. But I am guessing you need delay between two registers, right? I am wondering why do you need such a delay? Robert.Article: 91509
Do you mean you need a development board? I am using Memec-Insight board with Spartan-3 and it has a 160 connector. There are probably 140 pins available for i/o. Robert.Article: 91510
I thought gVim was the editor of choice!Article: 91511
You are exactly right. I'm a researcher doing error control experiments and I need to find a way of making an arbitrary delay between registers. Any ideas how I can do this? Ideally I want to build a 32-bit wide bus between registers where each bit line has approximately the same (long) delay. I want to make a fake critical path. Regards, Dave. <robertncsu@gmail.com> wrote in message news:1131423585.021801.150580@g49g2000cwa.googlegroups.com... > When you say logic delay, do you mean you want to increase delay in the > same clock or do you just want to add delays? > > For just delays, you can add as many flip-flops as the number of > clock-delays you need. But I am guessing you need delay between two > registers, right? > > I am wondering why do you need such a delay? > > Robert. >Article: 91512
I notice that the Xilinx PCI32 core for Spartan 3 does not map the tristate enable FF's for the AD(x) lines to IOB's. Is there a good reason for this? The only adantage I can see for this is to try and force the AD(x) data FF's to contain the newest data before the IOB's are enabled. Anthony.Article: 91513
You should be able to. You'll probably have to code your own application though. You can readback that data through a JTAG interface, or even internally, using OPB-HWICAP core. There is a tool called JBITS, but I'm not sure if it supports V2, and it is written in java. regards, alonzo.Article: 91514
Article: 91515
Another reason may be to stagger the enable into four groups to control the amount of simulateous switching outputs?Article: 91516
mughat wrote: > Intellectual Property. http://www.acronymfinder.com/af-query.asp?String=exact&Acronym=ip&Find=Find Regards, AllanArticle: 91517
>You are exactly right. I'm a researcher doing error control experiments and >I need to find a way of making an arbitrary delay between registers. Any >ideas how I can do this? Ideally I want to build a 32-bit wide bus between >registers where each bit line has approximately the same (long) delay. I >want to make a fake critical path. There is some way to keep logic that the compiler is smart enough to discard. I forget how to do it. How about putting some dummy logic in there? Say an AND gate. Connect the other side of the gate to something like an input pin so the compiler can't outsmart you. Then go into the floorplanner and adjust the spacing to get the sort of delays you like. Maybe iterate adding more dummy gates. You might need to put a pipeline register right next to the dummy input to the AND gate to make sure it doesn't become the long path. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 91518
On Mon, 7 Nov 2005 23:42:57 -0500, "Dave Roberts" <anon@anon.com> wrote: >You are exactly right. I'm a researcher doing error control experiments and >I need to find a way of making an arbitrary delay between registers. Any >ideas how I can do this? Ideally I want to build a 32-bit wide bus between >registers where each bit line has approximately the same (long) delay. I >want to make a fake critical path. > >Regards, > >Dave. > ><robertncsu@gmail.com> wrote in message >news:1131423585.021801.150580@g49g2000cwa.googlegroups.com... >> When you say logic delay, do you mean you want to increase delay in the >> same clock or do you just want to add delays? >> >> For just delays, you can add as many flip-flops as the number of >> clock-delays you need. But I am guessing you need delay between two >> registers, right? >> >> I am wondering why do you need such a delay? >> >> Robert. >> > You should use primitives, and check out "Optimize instantiated primitives". I think you should alos LOC or RLOC the primitives, to have more control over the delay -- ZaraArticle: 91519
On Mon, 7 Nov 2005 17:20:40 -0800, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >After clicking Applications and making active one, and only one, of the many >software examples for the ml403_emb_ref_mb directory, I then go to tools - >update bitstream, which I believe is suppose to modify the download.bit file >with the new software. Although it doesn't and when I click on download the >VGA shows what it originally has and the pushbuttons stop working, so I >would assume that the download.bit file that got downloaded is the original >bootloop program that does nothing. So how do I make a change to one of >these programs and download it? I am also getting a cryptic Nothing to be >done for 'init_bram' message. > >Brad Smallridge >aivision dot com > I detected soem time ago that, at least on EDK/ISE 7.1, the bram init values are not updated automatically. You need to Tools/Clean/Bits inside the EDK, compile the program, and then Update Bitstream with Processor Data -- ZaraArticle: 91520
Hi all,
I have created my own ip core by ise and the "create/import peripheral" function in edk. When I created the ip core I added FIFO and User Logic S/W Register of the IPIF Services in it. After creating the ip core, I can see many funtions of the drivers aumatically created by edk. For example, DTW_DRIVER1104_mWriteReg, DTW_DRIVER1104_mReadReg, DTW_DRIVER1104_mResetWriteFIFO, DTW_DRIVER1104_mWriteFIFOFull, DTW_DRIVER1104_mWriteToFIFO and so on.
Then I want to use such functions to write some data to the registers and fifo. The programme is as follows,
DTW_DRIVER1104_mWriteSlaveReg2(BaseAddress, R_Num); DTW_DRIVER1104_mWriteSlaveReg3(BaseAddress, T_Num);
/* test whether the register write is right*/ R_Num1=DTW_DTIVER1104_mReadSlaveReg2(BaseAddress);
//put the lpcc parameters of two models in fifo //set the parameters DTW_DRIVER1104_mResetWriteFIFO(BaseAddress);
//write the lpcc parameters of the Reference model for(i=0;i<R_Num;i++) { //test whether the fifo is full if(!DTW_DRIVER1104_mWriteFIFOFull(BaseAddress)) //write data in the fifo DTW_DRIVER1104_mWriteToFIFO((BaseAddress+i*4), RModel_Data[i]); }
//write the lpcc parameters of the test model for(j=0;j<T_Num;j++) { //test whether the fifo is full if(!DTW_DRIVER1104_mWriteFIFOFull(BaseAddress)) //write data in the fifo DTW_DRIVER1104_mWriteToFIFO((BaseAddress+R_Num*4+j*4), TModel_Data[j]); }
//wait for a moment for the data is ready wait(1000);
//set the en signal (write in register0) to 1 to start the ip core to compute DTW_DRIVER1104_mWriteSlaveReg0(BaseAddress, en_s);
However, I couldn't get the right results. I don't know why. Is it because that I didn't write to the register and the fifo in the right way. Shall I have to set some control regs or do some initial operation before I write to the registers and fifo.
Who knows? Please help me. It is urgent.
Thank you very much.
Athena
Article: 91521
Hello all
I want to multiply two signed 8-bit numbers and pick 8 bits from the result.
My code is like this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
Port ( k : in std_logic_vector(7 downto 0);
x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(7 downto 0));
end test;
architecture beh of test is
signal kx : std_logic_vector(15 downto 0);
constant Offset : integer := 4;
begin
kx <= signed(k)*signed(x);
y <= kx(Offset+7 downto Offset);
end beh;
How can I avoid getting these warnings:
WARNING:Xst:646 - Signal <kx<15:12>> is assigned but never used.
WARNING:Xst:646 - Signal <kx<3:0>> is assigned but never used.
Article: 91522Is it possible to drive global clock routing networks with an internal signal on a Virtex-E FPGA? I am trying to develop data/strobe enoding on an Virtex-E FGPA. It is required that data and strobe signals are XORed to obtain a clock signal. Then this clock signal will be fed to other logic in the FPGA. Therefore I need to use the XORed signal to use as a clock signal. Thanks for your replies.Article: 91523
Hi, Jered, I tried months before to use MIG007 generating a DDR controller for ML310, failed and the xilinx support did not help to get through. I modified everything to fit ml310 kit and when I download the generated testbench, nothing happened in the DDR. You can discuss with me by: xjf77(at)yahoo.com. regardsArticle: 91524
WTec wrote: > Hello all > > > > I want to multiply two signed 8-bit numbers and pick 8 bits from the result. > > > > My code is like this: > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > entity test is > > Port ( k : in std_logic_vector(7 downto 0); > > x : in std_logic_vector(7 downto 0); > > y : out std_logic_vector(7 downto 0)); > > end test; > > > > architecture beh of test is > > signal kx : std_logic_vector(15 downto 0); > > constant Offset : integer := 4; > > begin > > kx <= signed(k)*signed(x); > > y <= kx(Offset+7 downto Offset); > > end beh; > > > > > > How can I avoid getting these warnings: > > > > WARNING:Xst:646 - Signal <kx<15:12>> is assigned but never used. > > WARNING:Xst:646 - Signal <kx<3:0>> is assigned but never used. They're just warnings, and quite valid ones, so I'm not sure why you want to get rid of them. If you're not going to use the high order bits, then why calculate them? Surely kx should only be from 7+Offset downto 0 That would get rid of the first warning, though may produce one about kx not being of sufficient size for the 8x8 result (or some other such warning).
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