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CMOS wrote: > here we go again...showing off stupidity.... > Well he has been your only reply, so perhaps you should just humor him some and leave his comments be. Other than that, he wasn't far off. I2C is a shared interface, usually using open drain/collector pull-down connections. So it will require the use of a tri-state output buffer. You will simply set the output value to always be a low value (ie always pulling low) and the only signal that will be controlled for the pin is the output enable. Both pins should be bi-directional, to be capable of operating in either master/slave mode, and to tolerate clock stretching. So as long as you assign the output signals from your I2C module to tri-statable pins everything should be ok. Is that what you're after?Article: 90626
"Benjamin Menküc" <benjamin@menkuec.de> schrieb im Newsbeitrag news:dj19v2$7hj$04$1@news.t-online.com... > Peter Alfke schrieb: > > You are running at 66 MHz, and you think Virtex2 is too slow? Are you > > kidding? > > Did you ever use the fine phase adjust capability in the DCM, where you > > can move the clock in 256 increments? > > Peter Alfke > > > > Hi Peter, > > the lvds clock is 7*clk. I want to run at 85 MHz in the end, that would > be 595 MHz. > > regards, > Benjamin and that would be no big deal either. check out xapp265 85*7 means 1) output clock is 85MHz 2) highes clock on chip is 300MHz as you use DDR io flops :) for external lvds serdes 1) make sure data flops are on IOB 2) use DCM to adjust phy clock phase given [1] and [2] you dont need any timing constraints on the phy output path, as the IOB clocked outputs have very little skew and DCM adjust your clock to the best timeslot anttiArticle: 90627
Hi, I am a FPGA newbie. Here's my question: How do you count the gates in Xilinx FPGA? I have a XC3S400 board, which is supposed to have 400K gates. But when I synthesize the following code, the synthesizer report 68 LUTs were used, compared to total of 7168 LUTs, I would say that about 1% of the 400K gates, which is about 4000 gates, were used to synthesize my code. How ever, my following code only uses 150 "AND" gates and 142 "XOR" gates, why does it take XC3S400 take 4000 "gates" to handle my code? Is there any setting trick need to be done in the synthesizer or in the code? //===============Verilog code=======================// module GFMul(z,y,x); output [7:0] z; input [7:0] y; input [7:0] x; reg [7:0] z; //entry: reg[7:0] t; always @(y or x ) begin t[0]=((x [0]&y [0])^(x [1]&y [7])^(x [2]&y [6])^(x [3]&y [5])^(x [4]&y [4])^(x [5]&y [3])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [1])^(x [7]&y [5])^(x [7]&y [6])^(x [7]&y [7])); t[1]=((x [0]&y [1])^(x [1]&y [0])^(x [2]&y [7])^(x [3]&y [6])^(x [4]&y [5])^(x [5]&y [4])^(x [6]&y [3])^(x [6]&y [7])^(x [7]&y [2])^(x [7]&y [6])^(x [7]&y [7])); t[2]=((x [0]&y [2])^(x [1]&y [1])^(x [1]&y [7])^(x [2]&y [0])^(x [2]&y [6])^(x [3]&y [5])^(x [3]&y [7])^(x [4]&y [4])^(x [4]&y [6])^(x [5]&y [3])^(x [5]&y [5])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [4])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [1])^(x [7]&y [3])^(x [7]&y [5])^(x [7]&y [6])); t[3]=((x [0]&y [3])^(x [1]&y [2])^(x [1]&y [7])^(x [2]&y [1])^(x [2]&y [6])^(x [2]&y [7])^(x [3]&y [0])^(x [3]&y [5])^(x [3]&y [6])^(x [4]&y [4])^(x [4]&y [5])^(x [4]&y [7])^(x [5]&y [3])^(x [5]&y [4])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [2])^(x [6]&y [3])^(x [6]&y [5])^(x [6]&y [6])^(x [7]&y [1])^(x [7]&y [2])^(x [7]&y [4])^(x [7]&y [5])); t[4]=((x [0]&y [4])^(x [1]&y [3])^(x [1]&y [7])^(x [2]&y [2])^(x [2]&y [6])^(x [2]&y [7])^(x [3]&y [1])^(x [3]&y [5])^(x [3]&y [6])^(x [3]&y [7])^(x [4]&y [0])^(x [4]&y [4])^(x [4]&y [5])^(x [4]&y [6])^(x [5]&y [3])^(x [5]&y [4])^(x [5]&y [5])^(x [6]&y [2])^(x [6]&y [3])^(x [6]&y [4])^(x [7]&y [1])^(x [7]&y [2])^(x [7]&y [3])^(x [7]&y [7])); t[5]=((x [0]&y [5])^(x [1]&y [4])^(x [2]&y [3])^(x [2]&y [7])^(x [3]&y [2])^(x [3]&y [6])^(x [3]&y [7])^(x [4]&y [1])^(x [4]&y [5])^(x [4]&y [6])^(x [4]&y [7])^(x [5]&y [0])^(x [5]&y [4])^(x [5]&y [5])^(x [5]&y [6])^(x [6]&y [3])^(x [6]&y [4])^(x [6]&y [5])^(x [7]&y [2])^(x [7]&y [3])^(x [7]&y [4])); t[6]=((x [0]&y [6])^(x [1]&y [5])^(x [2]&y [4])^(x [3]&y [3])^(x [3]&y [7])^(x [4]&y [2])^(x [4]&y [6])^(x [4]&y [7])^(x [5]&y [1])^(x [5]&y [5])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [0])^(x [6]&y [4])^(x [6]&y [5])^(x [6]&y [6])^(x [7]&y [3])^(x [7]&y [4])^(x [7]&y [5])); t[7]=((x [0]&y [7])^(x [1]&y [6])^(x [2]&y [5])^(x [3]&y [4])^(x [4]&y [3])^(x [4]&y [7])^(x [5]&y [2])^(x [5]&y [6])^(x [5]&y [7])^(x [6]&y [1])^(x [6]&y [5])^(x [6]&y [6])^(x [6]&y [7])^(x [7]&y [0])^(x [7]&y [4])^(x [7]&y [5])^(x [7]&y [6])); z =(t); end endmodule //===============Resource Utilization================// Resource Usage Report for GFMul Mapping to part: xc3s400tq144-4 LUT2 17 uses LUT3 9 uses LUT4 42 uses I/O primitives: 24 IBUF 16 uses OBUF 8 uses I/O Register bits: 0 Register bits not including I/Os: 0 (0%) Mapping Summary: Total LUTs: 68 (0%) Thanks!Article: 90628
jerryzy@gmail.com wrote: > Hi, > I am a FPGA newbie. Here's my question: > How do you count the gates in Xilinx FPGA? I have a XC3S400 board, > which is supposed to have 400K gates. But when I synthesize the > following code, the synthesizer report 68 LUTs were used, compared to > total of 7168 LUTs, I would say that about 1% of the 400K gates, which > is about 4000 gates, were used to synthesize my code. How ever, my > following code only uses 150 "AND" gates and 142 "XOR" gates, why does > it take XC3S400 take 4000 "gates" to handle my code? Because in FPGA you don't count space in "gates" ... so don't try ... just use the Slice/LUT/FF count . The gate count given is more a commercial argument to me. And you use many more than you anticipated because in a FPGA when you don't always use all the resources inside a LC/LE to their full potential so those are wasted ... SylvainArticle: 90629
jerryzy@gmail.com wrote: > Hi, <snip> > //===============Resource Utilization================// > Resource Usage Report for GFMul > > Mapping to part: xc3s400tq144-4 > LUT2 17 uses > LUT3 9 uses > LUT4 42 uses > I/O primitives: 24 > IBUF 16 uses > OBUF 8 uses > > I/O Register bits: 0 > Register bits not including I/Os: 0 (0%) > > Mapping Summary: > Total LUTs: 68 (0%) This does nicely show that whoever writes this report software, really SHOULD fix the reporting, so it is more usefull than the nonsense 0% for 68 LUTs. These are large devices, and often small benchmarks are used, so common sense (Surely) would say, report % usage with a decimal point ? eg > Total LUTs: 68 (0.949%) -jgArticle: 90630
When there is a binding error.. this usually points to a connection problem. Typical things to look for are std_logic vrs std_ulogic ints unsigned vrs signed. This part is very much like OOP where the compiler is looking for a component with the exact same connections. The ieee sometimes does the conversion for you so it can be hidden sometimes. (if you use std_logic_unsigned you will find you can add an integer to a std_logic_vector for example) Simon <pinod01@sympatico.ca> wrote in message news:1129574626.908253.227130@g44g2000cwa.googlegroups.com... > Hi All, > > The specific error here was resolved by including the altera_mf > library into my test bench VHDL code. I also needed to include the USE > altara_mf.altera_mf_components.all into the VHDL code. > > Unfortunately when it does compile, there is another error that > appears which is bizarre. The Modelsim error is 3473 as follows: > > # ** Warning: (vsim-3473) Component 'a_graycounter2' is not bound. > # Time: 0 ns Iteration: 0 Region: > /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp onent > File: D:/My > Documents/University/Masters_Project/VHDL_Coding/Prestore_FIFO/vosq0_prestor e_fifo.vhd > > The error by Modelsim is described as follows: > # The specified component has not been explicitly bound and no default > # binding has been found for it. This means that your VHDL design does > # not include a component configuration for the specified component > that > # indicates which entity/architecture to use for that component. It > also > # means that no entity of the specified name containing ports and > generics > # matching those in the component declaration was found when searching > all > # visible libraries for a default binding. Simulation will continue, > but > # no VHDL code will be executed for the unbound component. > # > # To fix this problem, either put a component configuration in your > VHDL > # design that specifies which entity/architecture to use for this > component > # or compile an entity of the same name as the component and containing > # ports and generics matching those in the component declaration along > # with at least one architecture for the entity into a library that is > # visible at the time the component is being elaborated. You may need > # to add a library use clause before the entity containing the unbound > # component in order to make the library and component visible. > > > When I go and view the VHDL code that was generated by the Quartus > megawizard for the FIFO, it seems that the VHDL code for my FIFO > appears to have the instantiation of all the libraries including the > one that I described above, which dictates that the entity/architecture > code should be detectable by Modelsim during the compile process. I'm > confused to why this is not happening? Is there another library that > I missed? > > Just so it's clear my VHDL testbench also includes the following: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE std.textio.ALL; > USE ieee.std_logic_unsigned.ALL; > USE ieee.std_logic_arith.ALL; > > LIBRARY lpm; > USE lpm.lpm_components.all; > > LIBRARY altera_mf; > USE altera_mf.altera_mf_components.all; > > > Regards > Pino > > > > Subroto Datta wrote: > > The lpm_widthu parameter need sto be calculated & set by MegaWizard based on > > the size > > of FIFO chosen by the user. > > > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > > > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a > > > value. > > > > The design should be modified through the scfifo MegaWizard and should not > > changed manually. > > > > Hope this helps, > > Subroto Datta > > Altera Corp. > > > > <pinod01@sympatico.ca> wrote in message > > news:1129005330.788003.36580@g47g2000cwa.googlegroups.com... > > > To all, > > > > > > I have been attempting to load a lpm component into a Modelsim > > > project and when I get my test bench compiled and I try to simulate, I > > > get the following error. Note that vosq0_prestore_fifo (my own name) > > > is an instantiated VHDL LPM component from Altera Quartus software > > > using their scfifo function. Below shows the log window. The fatal > > > error is shown below and is detailed because for some reaoson I don't > > > know where to declare a value for the LPM_WIDTHU variable? I had > > > thought that this was already defined? Your help would be appreciated. > > > > > > Cheers > > > Pino > > > > > > # Loading work.vosq0_prestore_fifo(rtl) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > > > # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl) > > > # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > > > # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl) > > > # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body) > > > # Loading > > > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn) > > > # Refreshing > > > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > > > # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > > > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a > > > value. > > > # Time: 0 ns Iteration: 0 Instance: > > > /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp onent/scfifo14 > > > File: > > > QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/alte ra_mf.vhd) > > > # FATAL ERROR while loading design > > > > > > >Article: 90631
Peter,
I'm just trying to understand you. You are right - FIFO's width is
groups of bits and not bytes, but let me ask you what kind of problem
you can see. For example:
1. memory size is 2048 words of n bits
2. read and write addresses width have 12 bits
3. full indication is generated when fifo is filled up to 2047 (or 2048
in a case of it is generated with delay of 1 write clock cycle)
4. Now, suppose FIFO is filled up to 2048 (not 2047) and fill
indication is activated - no write cycles are allowed
i. within a next read operation, full indication is stay high and
fifo is filled up to 2047
ii. after additional read operation full indication is cleared
Why do you think, there is better to use almost full with latency of 1
to 3 clock cycles, but not real full indication, which works properly.
Article: 90632I've used a parallel cable 3 (home built) on Spartan 2/e's.. but they don't work above that.. defiantly not on Spartan 3's .. voltages are all wrong. I would strongly recommend you don't be so cheap and buy the USB downloader! "Klaus Bickert" <kfb@mpe.mpg.de> wrote in message news:ee90993.10@webx.sUN8CHnE... > Sorry, had been on conference last week. Parallel port is on a laptop, JTAG is 3.3v powered, connects to CESYS.com Xv2ddr module (Xc2v1000-456-5 plus xc18v04 prom) all run on 3.3. IMPACT gives me only a (nonexistent) multilink as choice, par3/4 are grayed out. Installation record says parallel cables drivers installed, no further details. IMPACT doesn#t recognize cable II in config-detect. Somethings wrong or missing in setup. How do I postinstall old cables ? no choice in installing from cd. Ciao, klausArticle: 90633
well if it can't be taught in schools.. shouldn't the schools get a student to write a better one ?? Simon "backhus" <nix@nirgends.xyz> wrote in message news:dj21rf$m1h$2@hermes1.rz.hs-bremen.de... > Hi John, > ...and I spent so much time with that nasty data2mem tool... :-( > > But it's good to hear that an alternative and more straightforward > solution exists, even if it's limited to XILINX. > > The bad thing is that it can't be taught in VHDL courses unless it is > supported by many (at least the important) tool vendors. Until then we > have to deal with questions like that of Robert. > > I hope this feature finds it's way into VHDL 20xx and will be supported > by more tool vendors much earlier. > > Thank you John for the information. (And to the XILINX programmers as > well. It's the first positive feature of the 7.1 version up to now IMHO.) > > Eilert > > John McCluskey schrieb: > > I read this thread about initializing FPGA memory with some interest. > > Well over a year ago, I asked the XST developers in Grenoble to add > > support for File I/O during VHDL elaboration. This actually works in ISE > > 7.1! You can write a VHDL function that opens a file (using the TextIO > > package), reads data out of it, and returns an array that can be used to > > initialize a signal array that has memory inferred on it. > -- snip > -- sorry, needed to cut to old postArticle: 90634
Austin, seems that Xilinx is always one step in advance! I'm impressed to see how many people in this newsgroup uses Xilinx. well done, Francesco Austin Lesea wrote: > All, > > http://tinyurl.com/clzqh > > Details the latest readouts for actual single event upsets for Virtex 4, > and Spartan 3. > > The improvements (6 times fewer upsets for Virtex 4, and 2.4 times fewer > upsets for Spartan 3 as compared to Virtex II) shows our commitment to > making this a non-issue for our customers. > > Make sure you demand from you ASIC/ASSP/FPGA vendor reports on their SEU > susceptibility! This is not an area where you should take this for > granted. Reducing SEU susceptibility is not something the foundry > builds in to their process; it is something that takes time and effort > on the part of IC designers to implement, and more time and effort to > verify. > > For a vendor to claim "oh, we do what Xilinx does..." is completely > insufficient. We certainly are not telling anyone how we did this (6X > improvement): just that we have done this. > > The only other company that we are aware of with a "Rosetta"-like > program (work with foundry on process; design, simulation, and analysis > by IC designers; measurements in neutron and proton beams; actual > atmospheric testing in multiple locations at multiple altitudes) is Cypress. > > Imitation is the sincerest form of flattery. > > Additionally, Cypress has a good book on the effects of cosmic ray > neutrons and protons on memories. > > http://tinyurl.com/72mvw > > For more details, contact your FAE. They have materials accessible to > them for customer presentations on this issue. > > AustinArticle: 90635
i need help for a Simple PWM Spartan 3, i dont know how to activate the spartan3 board helpArticle: 90636
Has anyone looked at interfacing a Cyclone II or Stratix II with the 1Gsps, 8 bit A/D from National Semiconductor (ADC081000) ? I'm looking for a reference design that will save me time rather than creating my own...Article: 90637
Eric wrote: > I'm working with the Virtex-II Pro FPGA. Is there a way that we can run > VHDL code for FPGA in PowerPC405 cores? Do you mean that you want to combine a ppc core with your own vhdl code? There are two ways to combine your code with a ppc project: 1. Use your vhdl as the top level (with ise as the build tool). Build a ppc project with edk and embed it as a block in your top level project. 2. Use edk as the top level build tool. Write your vhdl as modules in the pcores directory (copy the format from xilinx supplied cores). Install these and build with edk. Alan Nishioka alan@nishioka.comArticle: 90638
Jim Granville wrote: > Dave Pollum wrote: > > Jim Granville wrote: > > <Peter's stuff snipped> > > > >>Interesting - so for sustained thru-put on these, you are best to avoid > >>going empty, which probably means two operating modes : fastest, and > >>clean-out-the-last-byte(s) > >>I see some uarts have WDOGs in their fifos, that allow simpler streaming > >>code, and they generate a time-content interrupt, as well as the normal > >>threshold one. > >> Timeout is normally some multiple CHAR times, so the end of message > >>chars are dealt to without needing polling. > >> > >>-jg > > > > We upgraded a Zilog Z8530 serial port to a Z85230 serial port, because > > the Z85230 has deeper FIFOs. The 85230's recv port has an 8-byte FIFO > > vs the 8530's 3-byte FIFO. I had hoped that the CPU would be > > interrupted a lot less using the 85230. The 85230 can be set-up to > > interrupt when 1 char is recv'd or when there are 4 bytes in the recv > > FIFO (half full). This sounded really great and even worked quite > > well, until I discovered that when there _3_ bytes in the FIFO and the > > chip is set-up to interrupt when half-full, that the chip does not > > interrupt until another byte is received, even if that's minutes later. > > ARGH, WIPA! > > > > BTW what's a "WDOG"? > > Sorry, cryptic mode... WDOG = WatchDog = monostable timer, that > retriggers on every incomming CHAR, and times-out after some user > defined CHAR pauses. > Purpose is to catch exactly the PITA you describe :) > > -jg "Watch Dog" - I sorta thought that's what you meant, but I wasn't sure. Thanks for the explanation. And "WIPA" was a brain fart. I meant PITA. Good grief! -DaveArticle: 90639
Thanks Eilert. It worked!! Hurray! I am surprised why Xilinx does not have proper documentation for this tool. I mean, of course, the documentation for data2mem is pretty good in that it explains what it does and what are the options. However, there are no examples. I did find one example BMM file in a data2bram document. However, I would hope they improve the one on data2mem. Thanks again. Robert.Article: 90640
Just to add: I thought the syntax for data2mem in the documentation was misleading. Or may be its me. There it says: data2mem -bm|bd infile.[bmm|elf|mem] [options] This lead me to think that I should give EITHER a bmm or a mem file as input, as opposed to both which are required.Article: 90641
Hello, Okay, I want to latch all my data that goes to the lcd (via the external lvds serializer). Or should I use a FF? I need something that takes the data on rising edge and has it available on the output on the next rising edge with enough sample and hold time. Is it possible to do that with the IOB or do I have to build a latch in VHDL? Sorry for my basic questions :=) PS: In theory my rising and falling edge thing should work, why is it so bad? Is it not possible to set a timing contraint so that a process that is triggered by rising edge has every output available on falling edge? regards, BenjaminArticle: 90642
Hi Antti, see my answer to Symon. How do I set my outputs to have an FF in the IOB? Is a DCM already neccessary to adjust clock phase at 85 MHz? If I remember correctly I have to use a special pin on a clock net to do phase correction with a DCM, I am not sure if this is the case in my design. Maybe I can change that for the next version. regards, BenjaminArticle: 90643
On a sunny day (18 Oct 2005 05:47:00 -0700) it happened "Robert" <robertsolanki@gmail.com> wrote in <1129639620.226637.259200@g49g2000cwa.googlegroups.com>: >Thanks Eilert. It worked!! Hurray! > >I am surprised why Xilinx does not have proper documentation for this >tool. I mean, of course, the documentation for data2mem is pretty good >in that it explains what it does and what are the options. However, >there are no examples. I did find one example BMM file in a data2bram >document. However, I would hope they improve the one on data2mem. > >Thanks again. > >Robert. > Yes any documentation without examples is worthless irritating shit. That is why I started adding examples in the 'application -h' output these days.Article: 90644
Thanks Alan. I'm hoping to port an OS to the system, and eventually be able to run VHDL components in ppc. I'll try the methods you suggested. Thanks again.Article: 90645
The carry chains in current Xilinx FPGAs are insufficient for comparison logic. I propose some changes for future chip designs: First, if this can be done on a Stratix 2 carry chain, please state how. We are going to do a LT or GT comparison. The plan for LT: chop the thing into 2 bit chunks for the most significant chunk: if (a < b) switch the chain high if (a > b) switch the chain low if (a == b) passthrough repeat for next most significant chunk tie the bottom of the chain low So you see the problem? I can't force the chain high or low at run time and still allow for passthrough. I can only do one or the other.Article: 90646
Hi there,
has anyone used Xilinx' floating point core with a Virtex2 Pro?
I get the same strange error in ISE the whole day and I don't know whats
going wrong:
ERROR:NgdBuild:604 - logical block
'simple_multiply_1/blk00000003/blk00000005' with type 'fpmulE24mw_8ew' could
not be resolved. A pin name misspelling can cause this, a missing edif or
ngc file, or the misspelling of a type name. Symbol 'fpmulE24mw_8ew' is not
supported in target 'virtex2p'.
I read all the database articles, all basically saying that a netlist is
missing.
All generated FP Core files are in the ISE project directory (also the .ngc
file), the synthesize task also finds that file ("Reading core
<floating_point_v1_0.ngc>").
I slowly start to believe that my installation of ISE is corrupt, hmm...
Thanks for any help,
Simon
Article: 90647This excellent website discusses fast division: http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/DiviRa.htm I was able to build the tail object so that it used the carry chain hardware in a Virtex2 (through K-maping the logic table). Unfortunately, the triple head and double head are not nearly as easy. Has anyone done any work to make the triple head use the carry chain logic? If it's not possible, we should look at changing the slice layout in future chips. This is one of those parts that uses way more than its fair share of slices. My quick implementation of the triple head used two 3-bit adders and a 6bit wide 16 input mux. I recognize that on a Stratix2 those adders could both be done in fewer luts, but I'm still left with a 6x16 lookup table.Article: 90648
Jerry - we've designed (are designing) several LSI RapidChips. Here's some comments on your posting: - Costs are pretty out there. You need to get to a Rapid Ready Netlist using the LSI tool flow (LSI RapidWorx). Depends where you are coming from on how hard that is. If it's an FPGA design, expect to re-map the memories, re-do the I/Os, maybe change some IP, re-verify. If it's a clean design it's a case of designing for the technology. - You'll pay; LSI NRE ($50-200K depending on chip chosen) for Netlist to chip. Synplicity tool costs ($20K or so) and that should be it. RapidWorx is free. You'll need Synopsis primetime for STA - if you haven't got it that can be pricey, or you can pay someone to do it for you on an hourly rate - Layout is easy as long as you follow the rules - so, one iteration. The rules cover things like max speed (typically 250MHz) and getting the RTL through the design rule checker (Tera Systems, Teraform tool). The rules can be broken, but that's when physical becomes trickier and you can expect to pay some additional NRE - Device delivery schedule.....won't lie to you here, LSI is still putting chips through a new tool flow and we've run into several gotcha's that delayed things. By now hopefully things are cleaned up (they've done about 50 chips). But don't believe their 'as easy as an FPGA' hype - it isn't. Learning the tools takes sometime.....the tools still have some bugs. Working with someone who's done it before is a huge benefit. - Synplicity does a 'placed netlist' synthesis with pretty accurate timing.....except, one design we did had a massive fan out on the AMBA bus. We warned the end customer but he went ahead anyway. The final layout tool threw in a whole bunch of buffers and that screwed things up compared to Synplicity results. Otherwise the match has been very accurate. - Detailed place and route time - very dependent on the size / complexity of the chip. But very fast compared to an ASIC 6-8 weeks is a good rule of thumb - Test scan is built into the chip by LSI so you should have no worries there. You hand off RTL, they add clocks, scan chains etc. No need to worry about test coverage, signal integrity (as long as you follow the rules) - Paying distributor - LSI uses Arrow (in North America) to deal with most customers who aren't Cisco etc. Arrow has a design center and will do most (not all) of the post Netlist engineering. So yes, you pay them. But they are highly professional and experienced. Unless you're a high volume big guy in which case you might deal direct. >From experience I'd rather deal with Arrow any day. LSI ARE sticklers and can be a real pain to work with. Feel free to Email me with any questions or you can talk directly to one of our engineers (within reason, we have to make a living to!)Article: 90649
Benjamin Menk=FCc skrev: > Hello, snip > > PS: In theory my rising and falling edge thing should work, why is it so > bad? Is it not possible to set a timing contraint so that a process that > is triggered by rising edge has every output available on falling edge? assuming the clock 50/50 duty cycle that should be the same as constraining it to twice the frequency ;)=20 -Lasse
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