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To all, I have been attempting to load a lpm component into a Modelsim project and when I get my test bench compiled and I try to simulate, I get the following error. Note that vosq0_prestore_fifo (my own name) is an instantiated VHDL LPM component from Altera Quartus software using their scfifo function. Below shows the log window. The fatal error is shown below and is detailed because for some reaoson I don't know where to declare a value for the LPM_WIDTHU variable? I had thought that this was already defined? Your help would be appreciated. Cheers Pino # Loading work.vosq0_prestore_fifo(rtl) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl) # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl) # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl) # Loading C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body) # Loading C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn) # Refreshing C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a value. # Time: 0 ns Iteration: 0 Instance: /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_component/scfifo14 File: QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/altera_mf.vhd) # FATAL ERROR while loading designArticle: 90351
Hi All. I have a test routine that successfully compiles in iVerilog. I process my verilog source as follows: /usr/local/bin/iverilog -Wall -g2 -tvvp -o./test.sim ./test; /usr/local/bin/vvp ./test.sim -lxt2 Now I have the lxt2 formated output in the file ./test.sim My question is: How go I get GTKwave to accept and display this output? Every time I click GTKwave->File->Open the program just aborts and exits. I have tried without success cut & pasting too. Can anyone kindly offer some assistance please? Any assistance greatly appreciated. ------my---email---is---really---grahame---@---wildpossum---dot---com------ Cheers GrahameArticle: 90352
Grahame Kelly wrote: > Hi All. > > I have a test routine that successfully compiles in iVerilog. > I process my verilog source as follows: > > /usr/local/bin/iverilog -Wall -g2 -tvvp -o./test.sim ./test; > /usr/local/bin/vvp ./test.sim -lxt2 > > Now I have the lxt2 formated output in the file ./test.sim > > My question is: > > How go I get GTKwave to accept and display this output? > Every time I click GTKwave->File->Open the program just aborts and exits. > I have tried without success cut & pasting too. > > Can anyone kindly offer some assistance please? There are different versions of GTKwave available. I recommend trying 1.3.72 from here: http://home.nc.rr.com/gtkwave/gtkwave-current.tar.gz Regards, AllanArticle: 90353
Ray Andraka wrote: > I'm still mulling over replacing my aging system. Looks like a lot of > the newer workstation class processors are 64 bit processors, either P4 > or AMD 64. I've seen several notes stating that you should check to see > if your applications will run on 64 bit systems before buying one. Not > sure if this is going to be a problem. I want to buy as much performance > as I can, but can't afford to not have the non-CAE stuff work > I need to run, at a minimum: > Xilinx, Altera, Actel FPGA tools, > Synplify, Modelsim, Aldec > Matlab w/ simulink > MS office, Quickbooks > Acronis (disk imaging back up) > virus protection (don't care who's) > adobe acrobat > > Am I going to have problems using one of the 64 bit workstations for > this? We had some problems with Modelsim on 64 bit versions of Windows. (USB keyed licenses didn't work.) Installing a different version of XP fixed that. I assume you've read this benchmark thread: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/66e3c146f2984752/ Regards, AllanArticle: 90354
<happydude32905@gmail.com> schrieb im Newsbeitrag news:1128979440.818254.180270@g44g2000cwa.googlegroups.com... > Dear Google Group Members, > > Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I > understand that one must use component declarations in VHDL for the VIO > core, and therefore also for the ICON and ILA modules > > The following is a component declaration for the ICON core when using > the Xilinx Chipscope Pro Core Generator and the radio button "Enable > Unused Boundary Scan Ports (Only if necessary)" is not selected. > > --------------------------------------------------------------- > component icon > port > ( > control0 : out std_logic_vector(35 downto 0) > ); > end component; > -------------------------------------------------------------- > > My question is how does Xilinx ChipScope 6.3.03i communicate with the > core? There are not inputs to the core, only an output > std_logic_vector bus. the BSCAN primitive has internal connections to the JTAG pins, those are shown in the bscan primitive. control0 is actually not output only vector, bit 3 is reverse direction, that causes sometimes problems in the synthesis. using VIO is real simple, just use the icon (as above) connect the control from icon to vio, your signal to vio and that it. Antti PS gforge.openchip.org I think there is verilog source code of 3rd party VIO output compatible core take a look if you want to know the internalsArticle: 90355
Ray/Allan, I am running a dual 3GHz P4 with 3GB RAM with XP x64. ISE 7.1.03i works no problem. As does Office etc.. Pretty much everything works but some things need a little persuasion. Also, Acrobat is not supported the last time I checked. Also, compatible virus scanners are limited (Avast is one however). I have been able to get Modelsim running under x64 using a USB dongle based license. Firstly, to install Modelsim, I needed to restart in diagnostic startup mode (start->run->msconfig to do this). The problem with the USB dongle is that Macrovision don;t seem to have got around to x64 yet. However: Based on the info at http://tinyurl.com/7dzpv, I got a USB wireless network adapter (http://tinyurl.com/cyots) and then used a driver directly from the chipset manufacturer (Ralink) which supports x64 (that was the tricky part) to install it. http://www.planetamd64.com/index.php?showtopic=6301 http://catalog.belkin.com/IWCatProductPage.process?Product_Id=179211 For the driver: http://www.ralinktech.com/supp-1.htm Driver: 11g-RT2500 USB 2005/07/26 Drv2.0.3.0 XP x64 Before installing, follow the instructions starting on p7 of: <http://www.ralinktech.com.tw/drivers/Windows/Software%20Release%20Note%20RT2500USB%20STA%20072205.pdf> to add a line to the .inf file so that the Ralink section has a USB\VID_050D&PID_7050 entry: [Ralink.NTamd64] ; DisplayName Section DeviceID ; ----------- ------- -------- %Ralink.DeviceDesc% = RALINK.ndi, USB\VID_148F&PID_2570 %Ralink.DeviceDesc% = RALINK.ndi, USB\VID_050D&PID_7050 I then got my Modelsim disti to rehost my license to the MAC of the USB network stick and hey presto I am in business and can move my license about... I like my system though - it flies and now everything works as it should. Cheers, DaveArticle: 90356
ahhh.. one of the problems with the concept is the market is too small so it limits the availability. The other is each company has its downloader program... part of the IDE so you really need to integrate to that. Most of the JTAG money is spent on production test which tends not to focus on this market. There are a few hobby versions the price is sharp but the support is based upon what they want to use. I think the integration factor tends to make the vendor specific versions a little more friendly. If you shop around, you can sometimes get a demo board that comes with a programmer ... I got a free-bee parallel Altera one doing just that. Simon "Waage" <chris@ednainc.com> wrote in message news:1128961788.990405.9620@g47g2000cwa.googlegroups.com... > > Let me clarify why I am looking for a 3rd party JTAG programming > solution. > Being relatively new to FPGA design, I am trying to determine if there > is a vendor > non-specific option available. In other words are there solutions out > there that support > JTAG programming for Xilinx, Altera, and others? > > Thanks, Chris >Article: 90357
lpm_widthu will be a generic in the scfifo .. if you look at the entity for the scfifo it should show the available generics. <pinod01@sympatico.ca> wrote in message news:1129005330.788003.36580@g47g2000cwa.googlegroups.com... > To all, > > I have been attempting to load a lpm component into a Modelsim > project and when I get my test bench compiled and I try to simulate, I > get the following error. Note that vosq0_prestore_fifo (my own name) > is an instantiated VHDL LPM component from Altera Quartus software > using their scfifo function. Below shows the log window. The fatal > error is shown below and is detailed because for some reaoson I don't > know where to declare a value for the LPM_WIDTHU variable? I had > thought that this was already defined? Your help would be appreciated. > > Cheers > Pino > > # Loading work.vosq0_prestore_fifo(rtl) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_mf_components > # Loading work.vosq0_prestore_fifo_dcfifo_dsu(rtl) > # Loading work.vosq0_prestore_fifo_a_gray2bin_fl6(rtl) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.a_graycounter(behavior) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_common_conversion(body) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altera_device_families(body) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > # Loading > C:/altera/modeltech_ae/altera/vhdl/altera_mf.altsyncram(translated) > # Loading work.vosq0_prestore_fifo_alt_synch_pipe_lb5(rtl) > # Loading work.vosq0_prestore_fifo_dffpipe_lb5(rtl) > # Loading > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_common_conversion(body) > # Loading > C:/altera/modeltech_ae/altera/vhdl/220model.lpm_counter(lpm_syn) > # Refreshing > C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > # Loading C:/altera/modeltech_ae/altera/vhdl/altera_mf.scfifo(behavior) > # ** Fatal: (vsim-3350) Generic 'lpm_widthu' has not been given a > value. > # Time: 0 ns Iteration: 0 Instance: > /tb_sopc_memory_rw_vhdl/write_fifo_vosq0/vosq0_prestore_fifo_dcfifo_dsu_comp onent/scfifo14 > File: > QuartusIIVersion4.0(C:/Modeltech_6.0/win32/../altera/Vhdl/src/altera_mf/alte ra_mf.vhd) > # FATAL ERROR while loading design >Article: 90358
Hi, I would like to convert signal at 12volt to a 3.3v for connecting it to input pin of a spartan3 fpga. And then convert 3.3v output of spartan to 12 v , I'm not really use with designing board, I looked around but I did'nt achieve to find a lot of information. Should I use buffer with gain?? However does someone know where I could find information and teach about this kind of stuff like designing board... thanks for your answer regards kclArticle: 90359
you can't concat there.. you have to do it to another variable first Simon "Georgios Sidiropoulos" <me00569@cc.uoi.gr> wrote in message news:ee90b4d.0@webx.sUN8CHnE... > Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);Article: 90360
Sylvain Munaut wrote: > I'm looking for some example on how to use the USER1,2 functions in a > spartan 3 (examples on virtex2/4 or others are welcomed). I know how to > instanciate the component but that's about it. I searched xilinx site > but didn't found any real example ... > ... I think this TechXclusive can help You: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=krs_blockRAM Regards SandroArticle: 90361
>What do you experts think of the following entity I wrote? It’s purpose is >to eliminate metastability of the q signal. I'm not an expert, but I think I understand the issues. Whenever I see "eliminate" and "metastability" in the same sentence, I assume somebody doesn't understand metastability. It's like quantum mechanics. A lot of very smart people have worked on it. You are better off trusting them rather than inventing kludges - at least until you really understand what they have discovered. One of the problems with shooting down proposals like this is that it takes time. After a while the experts get tired of that. This one is easy on two grounds. First: >d: 00000X111111X00000X111111X00000 (X = meta stable bit-level) >From the initial state it need to interpret two neighbor samples as ones, >only then it gives a one on the q output. Then after that to get a zero on >the q output it must interpret two neighbor samples as zeros, then it gives >a zero on the q output. You need a gate that can detect 3 states: 0, X, and 1. They don't make them. Second: The other problem is that the best fix for metastability is to wait longer. You need time above the normal setup times. The more the better. The probability of badness decays exponentially with the excess time. Putting a gate in there reduces the excess time by the prop time of the gate. You are much better off to just use the old fashioned 2-FF synchronizer. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90362
>As has been said before, it's normally safe to make sure the MTBF is (say) >double the length of time you wanna be at your present company. Don't forget to scale by the number of units you might ship and the cost of a failure. Does your PC crash? Does your server trash its database? Does your space probe head for the wrong planet? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 90363
I think I have found what I need : a level shifter for TTL to CMOS should work fine "kcl" <KCLO4[no_spam]@free.fr> wrote in message news:difs7s$sm3$1@netnews.hinet.net... > Hi, > > I would like to convert signal at 12volt to a 3.3v for connecting it to > input pin of a spartan3 fpga. And then convert 3.3v output of spartan to > 12 v , I'm not really use with designing board, I looked around but I > did'nt achieve to find a lot of information. > Should I use buffer with gain?? > > However does someone know where I could find information and teach about > this kind of stuff like designing board... > > thanks for your answer > > regards > > kcl >Article: 90364
Description of the problem: I use a spartan 3-400 FPGA. A clk_100 (100 MHz), generated by a DCM is coming out of the FPGA and is used as an input for the phase shift DCM (clk100_fs). This construction is made to eliminate board skew. When I measure the clk100_fs it is not what I expect. (the phase shift is not according to the spec) When I change the input of the phase shift DCM to the clk_100 internal it is working correctly. I don't know what the problem is? Can you do only a phase shift with a clock which is generated by a DCM?Article: 90365
Grahame Kelly schrieb:
...
>
> /usr/local/bin/iverilog -Wall -g2 -tvvp -o./test.sim ./test;
> /usr/local/bin/vvp ./test.sim -lxt2
>
> Now I have the lxt2 formated output in the file ./test.sim
>
The ./test.sim is not the lxt2 file. It is the compiled verilog code
the simulator uses.
You need to specify the lxt2 file inside of your verilog code and what
variables should be put in it.
Look for the system function $dumpfile and $dumpvars from the verilog
languange.
Something like this would dump all your variables to the file test.lxt:
initial begin
$dumpfile("test.lxt");
$dumpvars;
end
Then you can open it with:
gtkwave test.lxt
> My question is:
>
> How go I get GTKwave to accept and display this output?
> Every time I click GTKwave->File->Open the program just aborts and exits.
> I have tried without success cut & pasting too.
>
> Can anyone kindly offer some assistance please?
You might also consider starting it from command line. Then you see any
error message it produced.
Hope that helps.
Guenter
Article: 90366depends on how long you want the TTL gate to live :-) "kcl" <KCLO4[no_spam]@free.fr> wrote in message news:dig01u$pod$1@netnews.hinet.net... > I think I have found what I need : a level shifter for TTL to CMOS should > work fine > > > "kcl" <KCLO4[no_spam]@free.fr> wrote in message > news:difs7s$sm3$1@netnews.hinet.net... > > Hi, > > > > I would like to convert signal at 12volt to a 3.3v for connecting it to > > input pin of a spartan3 fpga. And then convert 3.3v output of spartan to > > 12 v , I'm not really use with designing board, I looked around but I > > did'nt achieve to find a lot of information. > > Should I use buffer with gain?? > > > > However does someone know where I could find information and teach about > > this kind of stuff like designing board... > > > > thanks for your answer > > > > regards > > > > kcl > > > >Article: 90367
Hi, I have a problem with ModelSim XE II 5.6a. I can't execute any simulations beyond behavioral, because ModelSim doesn't find the vital 2000 library, though it is physically present. Here is the significant part of the error messages: -----SNIP----- # ** Error: (vcom-19) Failed to access library 'vital2000' at "vital2000". # No such file or directory. # ** Error: (vcom-19) Failed to access library 'vital2000' at "vital2000". # No such file or directory. # ERROR: C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim/vcomponents/_primary.dat(12): Library vital2000 not found. # ERROR: C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/simprim/vcomponents/_primary.dat(13): Unknown identifier: vital2000 -----SNAP----- I can't import the library, because the File->Import->Library command ends with "KernelUnknownError" after selecting the library. Any ideas what to do? Thanks in advance for all hints, JörgArticle: 90368
He hasn't received a reply but he did find an answer to his question. I was wondering what other people could recommend. Thanks, DerekArticle: 90369
"kcl" <KCLO4[no_spam]@free.fr> wrote in message news:dig01u$pod$1@netnews.hinet.net... > I think I have found what I need : a level shifter for TTL to CMOS should > work fine No, a typical TTL input is not designed to work with 12V input signals. Depending on what you are actually trying to achieve you might want to take a look at RS-232 transceivers. /MikhailArticle: 90370
HI! I'm a noob here. I have to estimate and confront the area occupied by a LUT 4:1 and the area occupied by an FF. Can I count required gates? How many gates need a 4:1 LUT? and a FF? Thanks in advance! ClaArticle: 90371
Assuming the desired bus speed is Conventional PCI @ 33MHz via PCI-X slot, does one have to assert and then deassert PCIXCAP the same way as M66EN? Both pins are grounded. Is there anything else that must be done to achieve PCI Mode @ 33MHz?Article: 90372
On 11 Oct 2005 07:03:34 -0700, "DerekSimmons@FrontierNet.net" <DerekSimmons@FrontierNet.net> wrote: >He hasn't received a reply but he did find an answer to his question. I >was wondering what other people could recommend. [for 12V <-> FPGA level shifters] For the input side of things, I would have thought that RS-232 receivers were a pretty good idea - they tolerate +/-15V on their inputs, and can easily be got for 5V or 3.3V on the logic side. Don't forget they are usually inverting. On the output side, it depends what you're trying to drive. If you're OK with simply sinking current, most power MOSFETs these days will switch on hard with only 3V on their gates: source to ground, gate to logic, drain to 12V output is good - you can easily control an amp or more of current on the 12V side this way, with nothing more than a single FET per output. Zetex and Intersil have plenty of devices that will fit the bill. There's also the trusty old ULN2803 octal Darlington output drivers, and various similar devices. Think carefully, though, about where the return ground current (through the FET source) is likely to flow. You don't want it finding random paths around your logic PCB. The big problem with all of this, in my experience, is that anyone trying to interface logic to 12V or 24V is probably playing around with industrial stuff. In that world, you can reliably assume that the electrical environment on the high-voltage side is totally crap. Sharing this filthy ground or power with your precious little 3.3V FPGA is asking for trouble. Inputs are quite likely to suffer significant voltage spikes, lots of nasty noise from horrible switches and motors and spark gaps and welding equipment and all that brutal stuff that you find around a typical industrial environment. Plant electricians have little patience with namby-pamby electronics and can be trusted to connect 110V AC to your sensing inputs, just for a giggle, to see how good your protection circuits really are. Logic designers are not welcome in a world where electrical connections are made with a quarter-inch wrench. If you're in the automotive world for your 12V, then it's just as bad. Remember that load dump effects can cause +/- 60V transients on power and control wires. Take a look at CANbus transceiver chips from Philips and others (82C251 rings a bell, but someone better check - it's been a long time...) to see how bulletproof it's possible to make 'em. Optical isolation *always* sounds like a good idea if you are in a dirty environment. Just don't expect it to be small or cheap :-( Just in case anyone asks: no, this is not simply pen-and-paper cynicism. Been there, got it wrong, got the burn-marks to prove it. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 90373
Let's assume I have a global clock running at 80 MHz and a 2 bit counter running from this clock, which generates a 20 MHz clock enable signal. Now I'm going to put a lot of combinatorial logic between two registers, which are clocked from the 80 MHz clock and enabled with the 20 MHz CE signal. How can I constrain this design so that it is not being placed and routed for 80 MHz? Is there a way to apply any sort of timing constraint to the clock enable signal / net? TIA, Stephan FlockArticle: 90374
Input signals (12 V driving into your 3.3V FPGA) are not the problem. Unless your signals are superfast (which they most likely are not) just insert a series resistor of, say, 10 kilohm. That, in conjunction with the internal clamping diode to Vcco, takes care of any high voltage up to tens of volts, and slows you down only by about 100 ns. Good idea for any input in the "industrial" world. The output side requires some kind of high-voltage driver. And observe Jonathan's warnings! Peter Alfke, Xilinx Applications
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