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Did you resolve this problem?? How??Article: 89876
These questions have probabaly been asked several times but here goes. I have a software background and want to learn FGPA programming. A friend of mine says that Verilog is the language to learn. I am interested in a recommended book to learn verilog. Another friend of mine said that the Altera tools are much better than Xilinx. Also one of the sales people (Xilinx Rep) I talked with say that the Spartan 3E is a better value than the Cyclone II parts. I am looking for pointers in any of these areas from people who actually use these tools and parts. I dont want to solicit a religous war, but I do want to know some opinions. Thanks in advance. KyleArticle: 89877
They used t have an Alliance version that had everything IIRC except XST. It was about $1000 dollars cheaper than the full system. I looked on their online store, and I did not see it, so I don't know if it exists anymore.Article: 89878
A port of eCos to the PowerPC embedded in Virtex-II Pro and Virtex-4 FX FPGAs exists. This could be your approach as proof of concept. Many other embedded OS have been ported to PowerPC and MicroBlaze. See http://www.xilinx.com/products/design_resources/design_tool/grouping/embedded_os.htm for a list of those. - Peter Ram wrote: > Dear Xilinx, > > Would you **please** consider investing money/effort into an eCos port to > Microblaze? > > Altera has sponsored a company to do an eCos port to NIOS-II and I'm > seriously considering using it. I realize that uCLinux for Xilinx exists, > but it is still being developed and has footprint/requirements larger than > many applications need. > > Please take into consideration the fact that sometimes a working proof of > concept is required before others within a company are willing to fully > support or fund a project. Something like eCos would allow me to do my > proof of concept, on my own time, and have the basis for a real product > when I'm done. > > The cost of entry is only my time and the development hardware we have > already purchased -- there are nothing else my company would need to spend. > An approach like this is much easier to sell than asking for money > up-front. > > And before someone points out it would be faster (in terms of > time-to-market) using an existing a closed-source RTOS that's been ported > to Microblaze, for some of the projects I or my company want to do, we're > trying to keep them open-source so we can build a community around it and > allow users to customize and add their own features. Most RTOS vendors > have strict policies on source code and/or licensing. > > Finally, consider that an eCos Microblaze question has come up multiple > times on the eCos mailing lists, even very recently. I am therefore, not > the only person who would want this. > > Sincerely, > Ram.Article: 89879
Hello all, I hadnt added a constraint file to my design hence the whole confusion. Thanks to Ed and all . Its working now. NiteshArticle: 89880
Hallo, I would buy a notebook. But I'm not sure about the model. I have seen some "desktop replacements" from my collegues with AMD Athlon 64 Mobile. They have a great performance for synthesis, mapping, placing, etc. Turion processors have the same performance? MarcoArticle: 89881
Kyle wrote: >These questions have probabaly been asked several times but here goes. >I have a software background and want to learn FGPA programming. Try not to think of it as programming. You are designing hardware. Hardware can be very parallel. Think having several memories and reading from all of them at the same time. Think of having several calculation units (like adders), and using them for different calculations at the same time. Hardware works well when pipelined. If A, B and C are fetched from memories, rather than trying to do A+B*C in one clock cycle it would probably make sense to fetch B and C on one clock cycle, multiply B*C and fetch A on the next, do the addition on the next, and save the result on the fourth clock. Notice that it takes four clocks to get the first answer, and the same hardware can repeat the calculation a clock cycle later. Software is (usually) doing exactly one thing at a time. >A friend of mine says that Verilog is the language to learn. Over half of the FPGA designs are in VHDL. Both VHDL and Verilog are not ideal languages for hardware design, however VHDL both allows for higher levels of abstraction and better low level control than Verilog. Of course, the choice of languages is rarely based on the merits of the languages. VHDL is harder to learn, and easier to master. Verilog is easier to learn, and harder to master. The area under the learning curve is about the same. In terms of employment, right now Monster.com for the USA, "Verilog and FPGA" came up with 105 hits, and "VHDL and FPGA" came up with 148. It is the reverse in the ASIC world. Of course, I don't know where you are. Some locations and some industries are heavy on Verilog, some are heavy on VHDL. You need to learn the local language, what ever that is. Your friend might have the correct answer for where you are. >Another friend of >mine said that the Altera tools are much better than Xilinx. Maybe yes, maybe no, this week. Xilinx and Altera are kind of like Coke and Pepsi, or VHDL and Verilog. At times in the past decade, Altera was leading. Right now, I'd say that Xilinx has both better parts, and the better tools. Next week, that might change. For most designs, both parts will do fine. For most designs, both tool sets will do fine. If you learn how to design well with one family, it will be easy to learn to design with the other family. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 89882
Hi all, I might be getting a Xilinx development board soon. I downloaded the free Web ISE toolkit from Xilinx. I am considering puting Xilinx's LogicCORE PCI IP core into it. I'm very new to this. So I'm looking for advice from the community. Will this LogicCORE come as a particular file that I can drop into my design? I would be writing the rest of my design in verilog. I presume the LogicCORE would not be in verilog but some pregenerated block that I can add in. I presume I would synthesize my verilog and then before the PAR stage, I would need to place this pregenerated block in order to get the final bit file. Is this correct? I'm trying to understand the various manuals but it's confusing. They talk about using a CORE Generator IP Update, manual installation and directly downloading. I think the first two are relevant to me but I don't see CORE Generator in Web ISE. Is this something that's feasible with Web ISE or would I need to purchase the full ISE? Thanks! GHHArticle: 89883
Brandon wrote: > I agree with Andy Peters. > > My company uses subversion (SVN) for all development. I recommend it > highly. The server and clients can be installed on nix and windows > (maybe others?). It has the ability to handle tags and branching. > Merging is very simple using the Tortoise SVN client gui. > > I think SVN beats all the other options to a pulp. It is insanely easy > to setup basic functionality too. > We too will be moving to Subversion sooner or later. Out of curiosity, do you use separate repositories for different projects, or do you have them all in one? And how do you access the server locally (svn or http protocol)? There are several options when setting up Subversion, so I'm trying to figure out which would make most sense from the start.Article: 89884
Hi,
when using Xilinx par 7.1.03i and implementing some logic on a Xilinx
XC31000, I get a warning regarding the routing of my main clock that I
don't understand. Could someone give an explaination as well as a way
to avoid it?
WARNING:Route - CLK Net:s_clk_120MHz
may have excessive skew because 5858 CLK pins
failed to route using a CLK template.
Many thanks, Eric.
Article: 89885Hi All, I'm interested in how a D flip flop can be made such that the Set and Reset signals can be configured as either synchronous or asynchronous. Does anyone have any ideas how Xilinx implement their async/sync CLB flip flops? Do they use asynchronous flips flops with a wrapper of logic so that the set and reset signals can be 'made' synchronous? (The only solution I've come up with so far). Or is there some lower level flip-flop design that allows a switch between sync and async set and reset? BTW, this is for an ASIC implementation, rather than an FPGA design. Anyone any ideas? Thanks Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 89886
We typically create a new repository for different projects so that only certain individuals have access to certain projects, since someone could very well delete files from a head revision. We also have a 'sandbox' repository that everyone has access to for testing and such. We use http. Our SVN server is installed on a dedicated linux box, although it was originally installed on an coworker's workstation when we first started out. I also know it's possible with http to setup a vpn connection to a SVN server, but we've yet to convince our uptight IT ppl that it would not be a security compromise.Article: 89887
thanks ,Ram,I got it.Article: 89888
The compilers work under a dos shell. No is not a Ansi C compiler, Small C is a compiler that was very popular in the '80. On my website you can download the user manual, that is incomplete, but may give you an idea about the potentiality of the compiler. FrancescoArticle: 89889
To all,
I'm generating an SOPC design in Quartus using the builder and have
created a custom master, slave and used a sdram controller. The VHDL
file that gets generated is a bit confusing to me, as it contains all
the arbitration logic associated in interconnecting everything
together; however, there are area's in the file that show up as "insert
code here", and I'm not sure if this is the testbench file, or the
behavioural file that represents the sopc design? I'm starting to
develop my own test bench to connect the sopc design to an external
memory model i got from a vendor. I'm curious to know whether I have
to do this, or if the file that was geneated from SOPC buidler
represents the test bench. The documentation on the files generated on
the Altera website are still a bit vague on exactly what to do and how
to do it.
Cheers,
Pino
Article: 89890Hi Group, I need to edit a program loaded in a CPLD.I can read a JDEC file from the CPLD.How can I convert that file into a readable program which I can edit? ThanksArticle: 89891
Hi, I have to initialise an SDRAM with an LUT (48MB). I have the LUT in .dat format. Is there anyway I can do this with the Xilinx ISE tool? I can do writes continuously but I'd like to know how to access the file in the first place. I read somewhere that I need a different IDE for it..that too only for RAM blocks. what does that mean? I am new to this field so if this question has been asked before please do point me in the right direction (I've done a good search already). ThanksArticle: 89892
Subhasri krishnan wrote: > Hi, > I have to initialise an SDRAM with an LUT (48MB). I have the LUT in > .dat format. Is there anyway I can do this with the Xilinx ISE tool? I > can do writes continuously but I'd like to know how to access the file > in the first place. I read somewhere that I need a different IDE for > it..that too only for RAM blocks. what does that mean? > > I am new to this field so if this question has been asked before please > do point me in the right direction (I've done a good search already). > > Thanks I think you're confusing build-time and run-time tools. ISE lets you build your FPGA project into code that can be loaded in the FPGA including any internal (distributed or block RAM) memory initialization. External memory needs to be loaded at run time by the FPGA. File access for this depends on how your system is connected to the computer containing the file. There are probably tools for this if you're using one of the development boards and the embedded processor design kit. Perhaps this (EDK) is the "different IDE" you're referring to?Article: 89893
Yes I understand that the external memory needs to loaded through the FPGA. I am not using any development boards but I am using a chip that has been designed to work as a special purpose processor. I was wondering on how to access the 48MB data and convert it into bitstream to be loaded into the FPGA through the JTAG port. Please do suggest some way I can do this.Article: 89894
I know that Xilinx has a SystemACE format for tasks such as this, but it may require you to use an embedded processor. It is impossible, though, to convert your LUT data into a bitstream as the FPGA can't store that much data.Article: 89895
Hi Alan, I believe there is a generic Nios clone called Manik (see http://www.niktech.com), just contact them to see if they can synthesis it to a ProASIC. Other cores with good support (gcc/Linux) are the excellent Leon2/3 core and the OR1200 from Opencores. If you really want 16 bits you can look at my 8088 core (http://www.ht-lab.com/hardware/APABoard/APABoard.html). It requires as a minimum an APA450 and runs at about 16MHz. You can also wait until Actel releases the ProASIC + ARM core :-) Hans www.ht-lab.com <amyler@eircom.net> wrote in message news:1127915110.847546.293070@g14g2000cwa.googlegroups.com... > Can anyone recommend a 16-bit microprocessor core to use in an Actel > ProAsic+ device. > > I'm familiar with Altera Nios and would like to find something similar > in complexity, performance, and ease of use (compiler, monitor etc). > > Any suggestions? > > Alan Myler >Article: 89896
Andrew Greensted schrieb: > Hi All, > > I'm interested in how a D flip flop can be made such that the Set and > Reset signals can be configured as either synchronous or asynchronous. > > Does anyone have any ideas how Xilinx implement their async/sync CLB > flip flops? > > Do they use asynchronous flips flops with a wrapper of logic so that the > set and reset signals can be 'made' synchronous? (The only solution I've > come up with so far). > > Or is there some lower level flip-flop design that allows a switch > between sync and async set and reset? > > BTW, this is for an ASIC implementation, rather than an FPGA design. > > Anyone any ideas? Thanks > Andy Basically for any flip-flop with synchronous reset you can add one or two pull down transistors at the right place to add asynchronous reset. The resulting flip-flop now has both reset options and you configure it by connecting the reset signal to either. A few ways to do that are shown in detail in Xilinx patent US000006501315B1. Kolja Sulimma Kolja SulimmaArticle: 89897
abhi wrote: > Hi Group, > > I need to edit a program loaded in a CPLD.I can read a JDEC file from > the CPLD.How can I convert that file into a readable program which I > can edit? Some may have a read protection. In the other cases you can read the JTAG. How to convert this into a readable diagram or code I wouldn't know. Theoretically it would be possible. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 89898
What is the system frequency ? What are input data and coefficients widths ? Which Xilinx component is targeted ? --------------------------------------------- -- TechwaY -- TechwaY Partners -------------------------------------------Article: 89899
Andrew Greensted wrote:
> Do they use asynchronous flips flops with a wrapper of logic so that the
> set and reset signals can be 'made' synchronous? (The only solution I've
> come up with so far).
>
> Or is there some lower level flip-flop design that allows a switch
> between sync and async set and reset?
For many FPGAs the async reset is built-in
to the base flop while sync reset is synthesized
from the logic cell resources. Synthesis
will also tie off any unused async inputs.
-- Mike Treseler
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Compare FPGA features and resources
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