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One more problem with ISE XST. In Synthesis Constraint file (.xcf) you can not use wildcards.Article: 89851
Hi all i am trying to generate an internalo clock for the apex20ke device which has to be implimented using quarus tool can you help me out in this at the earliest.... please thanks in advanceArticle: 89852
Frank van Eijkelenburg wrote: > Does anyone have experience with running the plb bus at 125 MHz and > using the ipif interface? The last EDK I worked with was 3.2, and I was using a Virtex 2 Pro, but "back then" it said in the documentation (the PDF you get when you open the documentation in the graphical editor) that the maximum frequency for the PLB is 100MHz, so I never even tried going faster. Don't know where the restriction comes from, though, i.e. if it has something to do with the FPGA fabric not being fast enough (in that case a V4 should be better) or the CoreConnect-IP... cu, SeanArticle: 89853
Sean Durkin wrote: > Frank van Eijkelenburg wrote: > >>Does anyone have experience with running the plb bus at 125 MHz and >>using the ipif interface? > > The last EDK I worked with was 3.2, and I was using a Virtex 2 Pro, but > "back then" it said in the documentation (the PDF you get when you open > the documentation in the graphical editor) that the maximum frequency > for the PLB is 100MHz, so I never even tried going faster. > > Don't know where the restriction comes from, though, i.e. if it has > something to do with the FPGA fabric not being fast enough (in that case > a V4 should be better) or the CoreConnect-IP... > > cu, > Sean Documentation for PLB bus indicates a frequency between 141 MHz and 194 MHz (for a virtex 2 pro -7). Documentation for the IPIF interface indicates a frequency between 101 MHz (using all services) and 189 MHz (for a virtex 2 pro -6). This is documentation that belongs to edk 7.1. Since the used ipif interfaces in my design won't use special services (only burst support is used), I expect it shouldn't be any problem?! FrankArticle: 89854
Can anyone recommend a 16-bit microprocessor core to use in an Actel ProAsic+ device. I'm familiar with Altera Nios and would like to find something similar in complexity, performance, and ease of use (compiler, monitor etc). Any suggestions? Alan MylerArticle: 89855
We are able to fetch an entire project from pvcs into any root folder &
rebuild the project, by setting up our working folders & matching pvcs
folders. We let Active-HDL put stuff where it wants to. Synplicity can be
setup to use relative paths (for example ..\src\Subsystem1) in its project
file. Xilinx ISE 7.1 can use relative paths to reference the Synplify .edf
file (..\Synplify\rev_1\foo.edf). The xilinx cores .xco & .edn must be in
the Xilinx folder. Note that if you're using any Xilinx symbols within
Active-HDL block diagrams, ISE must be setup to search the appropriate vlib
folder from the Active-HDL install folder. Assuming you're using just the
working library, a structure might look like this:
MyWorkspace (MyWorkspace.aws)
+-MyDesign (MyDesign.adf, MyDesign.lib, fsm.set, bde.set, compilation.order)
+-compile (vhdl generated from .bde & .asf)
+-src (your vhdl code)
+-Subsystem1
+-Subsystem2
+-XilinxCores (.vhd files from CoreGen)
+-Synplify (Synplify .prj & .sdc files)
+-Xilinx (Xilinx .ise, .ucf, .ipf file, along with .xco & .edn files
from CoreGen)
Hope this helps.
-Paul
<assaf_sarfati@yahoo.com> wrote in message
news:1127883427.597511.41890@g47g2000cwa.googlegroups.com...
> Paul wrote:
>> Neil,
>>
>> We use PVCS for version control with our VHDL, and it works just fine.
>> The
>> only tricky part is figuring out what files (beyond the vhdl) that your
>> tool
>> really needs to recreate a particular version, such as constraints,
>> cores,
>> and project setting files. Since we use 3 different tools (Active-HDL /
>> Synplicity / Xilinix ISE), it took a while to figure out which files
>> store
>> which configuration information to truly recreate a project from pvcs. I
>> would recommend creating the pvcs project folders to exactly mirror your
>> fpga working folder structure.
>>
>> -Paul
>> QuadTech
>>
> Can you tell us a little more? I am just starting a big new FPGA
> project, using the same set of tools, in a company which doesn't
> have a methodology for FPGA version control.
>
> How can you save a project in a way that a "get all" command prepares
> the entire environment? I'd like to be able to get all project files
> to any random root folder and be able to work immediately.
>
> I've already seen some problems:
> * ISE, Synplicity and Active-HDL have their own project files; if
> the source-files are not in the tool's project folder-tree, the
> project file records the absolute path to the file. How do you
> change your project/version root-folder without manually enering
> all files again in all tools?
> * CoreGen creates net-lists in its own folders; you have to
> manually copy them to the ISE root folder.
>
Article: 89856Hi I want to implement a 32 tap decimation filter in xilinx with reloadable coefficients. I would like to get a decimation filter structure suitable for me. can use maximum 1 multiplier and 3 BRAMs how can i get a structure for the same Suggestions are welcome rgds bijoyArticle: 89857
Thanks all for your feedback. There's a huge difference in pricing between Xilinx and the third party tools. It's great to get some opinions to help narrow down the choice a bit. ChrisArticle: 89858
I agree with Andy Peters. My company uses subversion (SVN) for all development. I recommend it highly. The server and clients can be installed on nix and windows (maybe others?). It has the ability to handle tags and branching. Merging is very simple using the Tortoise SVN client gui. I think SVN beats all the other options to a pulp. It is insanely easy to setup basic functionality too.Article: 89859
Nitesh wrote: > I tried the ILA tutorial example exactly the way given in the document. > I tried the vio. No luck either. > "waiting for core to be armed,slow or stopped clock " > I tried the same stuff on a windows machine.Still no luck. I get the > same result. > Have you double checked that you have an active clock in the FPGA? If you connect the clock in the system to an asynchronous VIO input does it toggle? EdArticle: 89860
Interesting. Tell us more about it. Is it Linux? Is it YAK? Is it C++? Is it ANCII? Stuff like that. And what are you doing with it? Just curious. Brad SmallridgeArticle: 89861
Are you using "T!" (Trigger Now and Display Buffer Data Samples) button or ">" (Apply Settings and Arm Trigger) button. As well on what are you triggering (what signals)? If it is the clock then I would recommand to change that because the clock is too fast to be caught by Chipscope. I'm using the Multimedia board with 27 MHz as my clock. My trigger is not my clock it's some data signal. However I have my clock as one of my output data and all I see is a constant '0' on the clock signal output hence Chipscope can't catch it. Hope I'm clear and hope this helps. Peace, MohArticle: 89862
Nitesh wrote: > I have a working design where I can see the ouput on the leds .I am > using a ML310 board . > The design doesnt seem to work when I try to load it through chipscope > pro. > When I use a ILA core into my design and try to load the design on to > the system it always says that "Waiting for Core to be armed, slow or > stopped clock": > I saw the chipscope pro answer record which says that this is due to > clock. The answer record is correct. Ever use an HP logic analyzer in state mode and forget to connect the clock input? You get a similar error message. Make sure that the ILA clock signal connects to the same clock used by the logic, and also ensure that it's actually running. -aArticle: 89863
And if you do port the open source decoder, libac3/liba52, be sure to heed the (GPL) license. cheers, aaron ps. would anyone be interested in an RTL AC3 decoder on commercial terms? I could probably crank one out in a few months part time.Article: 89864
The async input on VIO doesnt toggle when I map it to clock. It is because of the clock , I am sure about that but I cannot figure out why. The system clock is ok since other designs which I download using XPS work fine. I have gone through most of the documentation files but nowhere The problem is only when I configure through chipscope analyzer. Does anyone have any idea... NiteshArticle: 89865
assaf_sarfati@yahoo.com wrote:
> Paul wrote:
> > Neil,
> >
> > We use PVCS for version control with our VHDL, and it works just fine. The
> > only tricky part is figuring out what files (beyond the vhdl) that your tool
> > really needs to recreate a particular version, such as constraints, cores,
> > and project setting files. Since we use 3 different tools (Active-HDL /
> > Synplicity / Xilinix ISE), it took a while to figure out which files store
> > which configuration information to truly recreate a project from pvcs. I
> > would recommend creating the pvcs project folders to exactly mirror your
> > fpga working folder structure.
> >
> > -Paul
> > QuadTech
> >
> Can you tell us a little more? I am just starting a big new FPGA
> project, using the same set of tools, in a company which doesn't
> have a methodology for FPGA version control.
>
> How can you save a project in a way that a "get all" command prepares
> the entire environment? I'd like to be able to get all project files
> to any random root folder and be able to work immediately.
You have to be smart about how you create your projects in the first
place.
> I've already seen some problems:
> * ISE, Synplicity and Active-HDL have their own project files; if
> the source-files are not in the tool's project folder-tree, the
> project file records the absolute path to the file. How do you
> change your project/version root-folder without manually enering
> all files again in all tools?
Certainly in ModelSim and ISE, you can specify relative paths as you
add files to the project. Sometimes I forget and have to manually edit
the ModelSim project file to make the paths to the sources relative.
Once it's done, though, it sticks.
Active-HDL sorta drove me bonkers, as it has its own way of organizing
things and I never did figure out how to convince it to use my
particular source tree format.
Here's how I set up my projects:
projroot\
\src\ top level for synthesizable source code
\moduleA some convenient synthesizable module
\moduleB another module
\testbench\ test bench sources, project file, scripts
\modelA behavioral testbench model (an SRAM, perhaps)
\modelB another simulation model (PCI core, maybe)
\fitter\ FPGA constraint, project, build, Makefiles
\synth\ synthesis-tool scripts, project etc files
\docs\ READMEs, theory, explanations, requirements,
etc
Some points:
The src directory and its subdirectories contain only synthesizable
sources.
Both moduleX and modelX are entities that are shared among many
designs. (My nomenclature is that a "module" is synthesizable code you
put in a chip, whereas a "model" is a behavioral simulation model.)
They're in their own subdirectories because they are added to the
design using Subversion's externals properties. In other words,
they're not part of the chip project's trunk/branch, but rather they're
other "projects" (in the repository) unto themselves. (The smart
developer externals a read-only tag for these modules/models; this way
if you build a chip using version "A" of a module and someone comes
along and updates it to version "B," you don't get the wrong files,
especially if you need to go back to an older design and check out the
sources used to make it.)
I keep all testbench VHDL sources, .do files, simulation Makefiles and
project files in the testbench directory. These are kept in version
control. Temporary files, .WLF files and the work directory are not
kept in version control, for obvious reasons.
The fitter directory is where FPGA fitter/P+R tool scripts, constraint,
project and Makefiles are kept. Most of the tools have improved such
that they handle relative paths well and anything that copies a source
file to the fitter directory is BROKEN. Obviously, the tools spit out
a lot of temporary files and report files and create "work"
directories. All you need to keep in the version control repository is
the stuff needed to actually build the chip: constraint files, source
list files, etc. Buried somewhere in the tool documentation should be
a list of the various files used and created by the tool. I do NOT
normally keep final build results (.bit, .mcs, whatever) in the
development trunk.
Now, when it comes time to release something, you "tag" it. In
Subversion, this is simply a cheap copy, so it doesn't cost any disk
space. My repo is set up such that tags, once created, are read-only
(tags can't be modified). What I do is to add (literally "svn add")
the fitter build results (.bit, .mcs, whatever is used to actually
program the parts) to the trunk, do an "svn copy" to create the tag
from my working copy, then "svn revert" to remove the build results
from source control in the working copy (it doesn't delete the files
but it removes them from revision control).
I should point out that Makefiles (I build under Cygwin) are a G-dsend,
although I tend to live in the GUI until I'm sure things are meeting
timing.
So the great thing about all of this is that I can check out a whole
design by doing, say:
svn checkout svn://svnserver/repos/projA/trunk .
and it grabs everything required to simulate and build the current
development version of projA and stuffs it into the current directory.
I've found it convenient to have a "skeleton" project in the
repository. The skeleton has all of the directories already set up.
You simply do a copy on the repository:
svn copy svn://svnserver/repos/skel svn://svnserver/repos/projB
to create a new "project" within the repository. You then check out
projB and work as usual.
> * CoreGen creates net-lists in its own folders; you have to
> manually copy them to the ISE root folder.
CoreGen is stupid in that regard. When I use it, I create the CoreGen
project in a temporary directory, extract the files needed, and copy
them to the source directory. If I know that I am going to reuse that
Core, I simply put it into the repository as its own project, and add
it to a chip's source as an external. For example, I have the
PicoBlaze processor source in the repository as its own project.
-a
Article: 89866Brandon wrote: > I think SVN beats all the other options to a pulp. It is insanely easy > to setup basic functionality too. I'm a software engineer and I have selected Subversion for my company's development. One thing Subversion has over some other free tools is that it does directory versioning. This is a good thing(tm).Article: 89867
Andy Peters wrote: > > Certainly in ModelSim and ISE, you can specify relative paths as you > add files to the project. Sometimes I forget and have to manually edit > the ModelSim project file to make the paths to the sources relative. > Once it's done, though, it sticks. > Versions of ISE through 6.3 handled relative paths quite well. And the project file was plain text, another handy thing for making sure what was going on and making changes. With ISE 7.1, I no longer seem to be able to use relative paths. If you know how to, please let me know! And some bonehead decided to make the project file into some binary format. Arggh!Article: 89868
I am new to FPGA design and have a basic question regarding using 3rd party tools with Xilinx devices. I know that ISE WebPack is free but it only supports a few designs. So if you are working with a device that is not supported by WebPack and you are using 3rd party tools for synthesis and such do you still need to purchase Xilinx's place and route tools and programming tool (iMPACT)? Or can you get those pieces for free? Thanks, ChrisArticle: 89869
I got the playxsvf executable code... i had some questions regarding that.. Can this code be used to configure Virtex II Pro xc2v7? I was successfull able to convert the bit file to the svf format... but the svf2xsvf executable file doesnt seem wo work... i am trying to congigure Virtex II Pro on an Avnet board... which has a chain of devices.. do i have to worry about setting the bypass registers of the other deivces to '1' or does the C code take care of this?Article: 89870
Hi! springzzz@gmail.com wrote: > I've got some trouble on installing ise7.1 webpack on the debian linux > system, when I run the .sh file from the command line ,I got following > error: > Cannot register service: RPC: Unable to receive; errno = Connection > refused I had this same problem. You need to install "portmap" Try (as root) apt-get install portmap Then try to run the Xilinx installer. See this page for the other packages you might need to install: http://lug.wsu.edu/node/204 Ram.Article: 89871
Hi, Just wondering if someone can give me a ballpark/estimate pricing of the V2-Pro / V4-FX devices compared with a Spartan-3 or a V4. If you want to e-mail me privately and not post in the ng, I'm fine with that. For a project I am working, I want a uP + FPGA + decent OS. I'm looking at Microblaze, but I know the uCLinux port to it isn't very mature yet. I know that the Linux port to PowerPC is very mature and there are other free OSes available for PPC. Regards, Ram.Article: 89872
Dear Xilinx, Would you **please** consider investing money/effort into an eCos port to Microblaze? Altera has sponsored a company to do an eCos port to NIOS-II and I'm seriously considering using it. I realize that uCLinux for Xilinx exists, but it is still being developed and has footprint/requirements larger than many applications need. Please take into consideration the fact that sometimes a working proof of concept is required before others within a company are willing to fully support or fund a project. Something like eCos would allow me to do my proof of concept, on my own time, and have the basis for a real product when I'm done. The cost of entry is only my time and the development hardware we have already purchased -- there are nothing else my company would need to spend. An approach like this is much easier to sell than asking for money up-front. And before someone points out it would be faster (in terms of time-to-market) using an existing a closed-source RTOS that's been ported to Microblaze, for some of the projects I or my company want to do, we're trying to keep them open-source so we can build a community around it and allow users to customize and add their own features. Most RTOS vendors have strict policies on source code and/or licensing. Finally, consider that an eCos Microblaze question has come up multiple times on the eCos mailing lists, even very recently. I am therefore, not the only person who would want this. Sincerely, Ram.Article: 89873
Synplify Pro now has a "message window" that sorts all the notes, warnings and such in groupings. There is a filter included to ignore those messages we all "know" aren't of any help. It's better than trying to look through the log but it's still not the best interface. Cartainly an improvement, however. "Simon Peacock" <simon$actrix.co.nz> wrote in message news:433a65a9@news2.actrix.gen.nz... > The one main complaint I have with symplify is the number of warnings and > messages it generates... I like to check them off and say "that's ok" ... > "that's unnecessary" etc .. but I haven't found a way to turn the > unnecessary ones off. > > Typically this happens on some of my standard modules which might have > unused pins or internal blocks which are going to be optimized out, but will > leave a signal or two (which will also be optimized away). > > Altera fixed this with the 'if_used' attribute in AHDL... but that's gone by > the wayside since AHDL isn't supported any more. > The other annoying one is where ROMS are generated and it optimizes columns > out as they aren't unique ... something's you just don't care about :-) > > SimonArticle: 89874
Hi all, can anybody provide me the information about paralle FIR filter structures or any useful links. my e-mail ID : luck4you@gawab.com thanx in advanse
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