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Hi I am a need of help to get back something that could be considered 'my life' - its actually a content of an 60GB IBM Deskstar HD (I know those are known to be bad!) - this HD contains a lot of my projects from what I do not have backups. In the matter of fact I used that HD to hold old backups from older disks. The disk drive started todo the famous clicking sound last week. I have asked for quote to restore some folder from the HD from an UK based company, the prelim quote was 275 UKP (I only asked to recover on directory so final quote may be higher). I can not spend such a sum at the moment. So if anyone feels like ready to help then I accept any donations - the only thing I can promise in return is that I will burn 1 DVD with the recovered files (in unedited form, all of them!) and send it to anyone who donates 10+ USD for the 'antti-recovery' project ! http://wiki.openchip.org/index.php/Main_Page not all projects I wanted to be donated have been uploaded, some of them are possible on the malfunctioning harddisk :( Please dont ask what is on the disk, it used to be main HD in my workstation, and it holds also copies from at least 2 older hard disks. Antti PS to explain the (again) - for about 6 years ago I did over-work brain-overheat (ended up for 1 month in hospital and had to re-learn to speak and walk!), my mom did blame my PC in that and BURNED it. So I lost the last version of an commercial RISC compiler (amongst other projects) that I was selling for profit for many years. Well there was something that survived that burn, a girl I had met a few weeks earlier is now my wife and we have 3 kids. PPS the HD I need to be recovered has a restored backup of that compiler, and also some CD to HD backups.Article: 89926
Hi My decimation filter input data rate : 8.832 M Samples/sec clock frequency can go upto 35.328 x 2 input clock available is 35.328 MHz we can use DCM available in xilinx to increase the clock frequency. (presently i am using 35.328 x 2 Mhz) input data and coefficient width = 16 xilinx part : spartan-3 xc50K device 144 TDFP, speed grade -4 thanks regards bijoyArticle: 89927
"Subhasri krishnan" <subhasri.krishnan@gmail.com> schrieb im Newsbeitrag news:1128003125.870713.34210@z14g2000cwz.googlegroups.com... > Hi, > I have to initialise an SDRAM with an LUT (48MB). I have the LUT in > .dat format. Is there anyway I can do this with the Xilinx ISE tool? I > can do writes continuously but I'd like to know how to access the file > in the first place. I read somewhere that I need a different IDE for > it..that too only for RAM blocks. what does that mean? > > I am new to this field so if this question has been asked before please > do point me in the right direction (I've done a good search already). > > Thanks > www.xess.com they have an application that preloads an SDRAM connected to FPGA with binary image. That sdram content can be later used by the FPGA real application that needs it, the SDRAM goes into self refresh and maintains its content when CLK is stopped. Xess has I think all source code needed for this kind of applciatio available for downloads AnttiArticle: 89928
Hi all,
I am developing a hardware in which I need large size MUX. I need a
240 to 1 byte multiplexer. I tried to code it but observed the
following problems.
1. I tried the straight forward way. Using the AND and OR gates. This
is simple as I have to use simple "generate" functions in verilog.
But the problem is that I could neither simulate nor synthesize the
design. In the modelsim (V 6.0a) it just stop responding when I tried
to load the design. And in the Xilinx ISE also its not working. In case
of ISE first it shows strong activity and loads the processor and takes
up loat of memory. But after some time it just not working ; ISE is
showing activity but the processor usage is almost '0' and after
some 4 hrs it showed only 60% progress. If I reduce the size of the
inputs it just works fine and gives output in few minuts.
2. Then I tried the case statement and I written 240 cases. In this
case also xilinx is not working.
I am using Windows XP on AMD machine. Version of the ISE is 6.0. And if
I reduce the number of cases to 120 it gives proper output.
I confused about the low activity of the Xilinx. Why its not loading
the processor. Is it because of the problem in the OS. I hope the
method 2 will work with the synthesizer.
Please advice me on this issue. And please let me know about any usual
ways to generate this type of huge MUX.
The output of the Xilinx is given below.
Started process "Synthesize".
=========================================================================
* HDL Compilation
*
=========================================================================
Compiling source file "../test/test.v"
Module <test_mux> compiled
No errors in compilation
Analysis of file <test_mux.prj> succeeded.
=========================================================================
* HDL Analysis
*
=========================================================================
Analyzing top module <test_mux>.
WARNING:Xst:905 - ../test/test.v line 23: The signals <in> are missing
in the sensitivity list of always block.
Module <test_mux> is correct for synthesis.
Set property "resynthesize = true" for unit <test_mux>.
=========================================================================
* HDL Synthesis
*
=========================================================================
Synthesizing Unit <test_mux>.
Related source file is ../test/test.v.
Unit <test_mux> synthesized.
=========================================================================
* Advanced HDL Synthesis
*
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis
*
=========================================================================
Optimizing unit <test_mux> ...
***### Program stoped the processor loading here###***
Article: 89929Hi we are looking for one serious beta tester for our PLD2HDL conversion tool (Xilinx Coolrunner XPLA3 support). Please inquire in private. The current version of the tool seems to be quite accurate, as example the synthesis of the vhdl converted from Xilinx Cable IV readback (XCR3384) reports 3 UCT, 1 GCK, 39 I/O's, 117 FF's and 230 MC useage what to our knowledge is pretty accurate. We run of course our own test suite on the tool as well, but 3rd party testing can always help to find more bugs and/or issues than inhouse testing. AnttiArticle: 89930
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag news:1128076170.901183.12350@z14g2000cwz.googlegroups.com... > Hi all, > I am developing a hardware in which I need large size MUX. I need a > 240 to 1 byte multiplexer. I tried to code it but observed the > following problems. you better think in terms of luts, and code an hierarchial tree, that should sysnthesize without anyproblem. We have defenetly synthesized way wider MUXes AnttiArticle: 89931
"G.H. Hardy" <gh_hardy@yahoo.com> schrieb im Newsbeitrag news:1127979432.883293.86390@g49g2000cwa.googlegroups.com... > Hi all, > > I might be getting a Xilinx development board soon. I downloaded the > free Web ISE toolkit from Xilinx. I am considering puting Xilinx's > LogicCORE PCI IP core into it. I'm very new to this. So I'm looking for > advice from the community. the ip core is an ngc netlist you get lots of (also verilog) wrappers for it to help instantiating it. Antti you can also use some free PCI ip core that comes with source code, there are several available.Article: 89932
Hi we have one desing (several PCBs tested) where we witness sever problem configuring the XC2S200 and/or XCF02s, on one workstation running ISE 6.3 all works with Cable IV, from that PC also download with CS 6.3 and 7.1 works. from any other computer with ISE 7.1 we have (almost) never been able to program the FPGA or JTAG or get the XCF to be programmed properly. The JTAG Status readback is mostly all 0's when using impact 7.1, again there are no problem when using ISE 6.3 tools. We are testing with different PCs and cables (both IV and platform USB). The FPGA config design is pretty standard XC2S200 + XCF02s in the same chain, M0=M1=M2=GND Anybody having similar issues? Antti ps to Austin, YES I will file webcase on this.. but I hope for solution before the webcase can respond, the issue has cost us now 4 man-days already.Article: 89933
Ok .. but is it easy to simulate? And if we code it in a hierarchial tree will it take more area than required. Please give little more details in this.Article: 89934
"vssumesh" <vssumesh_asic@yahoo.com> schrieb im Newsbeitrag news:1128080413.197839.108730@g47g2000cwa.googlegroups.com... > Ok .. but is it easy to simulate? And if we code it in a hierarchial > tree will it take more area than required. Please give little more > details in this. > one slice (2 LUTs + MUX) can implement 4:1 mux so you mux down by 4, than again by 4 as much as needed 256 to 1 MUX: if you take 256 signal then 1 LUT level reduces it to 64 (64 slices) the second to 16 (16slices) the 3rd to 4 (4 slices) and the last to 1 signal (1 slice) ==85 slices this is the smallest LUT based mux whatever you write in HDL the same amount of LUTs is required AnttiArticle: 89935
Hi all, I have a question on POR(Power on reset generation ) using FPGA. My FPGA does not have a external Power ON reset , i am planning to generate a Power ON reset in the FPGA only.Is it really feasible to do this in an FPGA, and use this as the reset for my logic. Any suggestions appreciated?? Regards, PravArticle: 89936
<praveen.kantharajapura@gmail.com> schrieb im Newsbeitrag news:1128081435.932402.259660@g44g2000cwa.googlegroups.com... > Hi all, > > I have a question on POR(Power on reset generation ) using FPGA. > My FPGA does not have a external Power ON reset , i am planning to > generate a Power ON reset in the FPGA only.Is it really feasible to > do this in an FPGA, and use this as the reset for my logic. > Any suggestions appreciated?? > > Regards, > Prav > sure its possible. it is maybe not always as good as external reset circuit but for most cases its ok. the FPGA actually does release itself from reset during powerup configuration, if needed you can delay it to generate a longer reset AnttiArticle: 89937
I'm not sure if this is VHDL or Modelsim issue (other than operator
issue), so I'm posting in both groups. It looks like too simple a case
to ask someone online, but I've been scratching my head too long on
this. I'm relatively new to VHDL (and Modelsim as well).
In a testbench, I'm doing a simple signal generation :
- assert 'sig1' at a rising edge of a free running clock at some point
- deassert 'sig1' at the next rising edge
- and on the 3rd edge, do some checking, and so on...
However, the simlation waveform shows that 'sig1' is asserted from 2nd
to 3rd clock edge, instead of being asserted from 1st to 2nd edge.
What am I doing wrong? I've included both snippets from the testbench
and the debug output. I expected 'sig1' asserted from 314 to 318ns.
Simulation waveform shows assertion from 318 to 322 ns instead. Any
help would be appreciated.
# ---------------- in a test bench -------------------
# Wait for a rising edge, and bring 'sig1' high
wait until rising_edge(clk);
write (L, string'("1st rising edge : " & image(now)));
writeline (output, L);
sig1 <= '1';
write (L, string'("1st rising edge (again) : " & image(now)));
writeline (output, L);
# Wait for the next rising edge, and bring 'sig1' low
wait until rising_edge(clk);
write (L, string'("2nd rising edge : " & image(now)));
writeline (output, L);
sig1 <= '0';
# Wait for the 3rd rising edge
wait until rising_edge(clk);
write (L, string'("3rd rising edge : " & image(now)));
writeline (output, L);
# ---------------- debug output -------------------
# 1st rising edge : 314 ns
# 1st rising edge (again) : 314 ns
# 2nd rising edge : 318 ns
# 3rd rising edge : 322 ns
Article: 89938
fastgreen2000@yahoo.com wrote:
> I'm not sure if this is VHDL or Modelsim issue (other than operator
> issue), so I'm posting in both groups. It looks like too simple a case
> to ask someone online, but I've been scratching my head too long on
> this. I'm relatively new to VHDL (and Modelsim as well).
>
> In a testbench, I'm doing a simple signal generation :
> - assert 'sig1' at a rising edge of a free running clock at some point
> - deassert 'sig1' at the next rising edge
> - and on the 3rd edge, do some checking, and so on...
>
> However, the simlation waveform shows that 'sig1' is asserted from 2nd
> to 3rd clock edge, instead of being asserted from 1st to 2nd edge.
>
> What am I doing wrong? I've included both snippets from the testbench
> and the debug output. I expected 'sig1' asserted from 314 to 318ns.
> Simulation waveform shows assertion from 318 to 322 ns instead. Any
> help would be appreciated.
>
Not seeing more of your testbench, it is difficult to diagnose, but
maybe, your "free-running clock" is something like this:
process
begin
loop
clock<='1';
wait for x ns;
clock<='0';
wait for x ns;
end loop;
end process;
In this case you feel like there is a rising edge at the beginning of
the process, but it will not be found by your wait statement, as the
level is "already there" when you start waiting.
I know this is not the strict answer, but I would trace the instant you
begin your wait. From your debug output, I think it is possible that you
start waiting at 310 ns, so that the clock has "already changed".
Hope this helps you
Article: 89939fastgreen2000@yahoo.com wrote: > However, the simlation waveform shows that 'sig1' is asserted from 2nd > to 3rd clock edge, instead of being asserted from 1st to 2nd edge. > What am I doing wrong? Try it again with the signal assignments before the waits. -- Mike TreselerArticle: 89940
> A few ways to do that are shown in detail in Xilinx patent > US000006501315B1. > Thanks for the tip. For anyone else who stumbles across this thread and is interested, the patent can viewed at: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1=6501315.WKU.&OS=PN/6501315&RS=PN/6501315 You need to search for patent number: 6501315Article: 89941
Additionally to all the remarks made by others, have you noticed that
in
when rw_2 =>
if ram_counter_w = "11111111111111110" then
next_state <= rw_3;
else
next_state <= rw_1;
end if;
the length of the literal is only 17 bits ?
Should of course be 18 => the comparison is never true with 17 bits.
Article: 89942
Yes, I'm doing just that for creating clock, and your post shed some
light on what I wasn't paying attention to, but...
I'm still confused. In the following testbench code, shouldn't it wait
for a certain rising edge (whatever time it might correspond to), and
assert 'sig1', at the time reported by 'now'? What I see is 'sig1' get
asserted one clock after that.
line 1 : wait until rising_edge(clk);
line 2 : write (L, string'("1st rising edge : " & image(now)));
line 3 : writeline (output, L);
line 4 : sig1 <= '1'; -- I see this signal go high at 'now' + 1
more clock cycle??
-- note that lines 2,3,4 are
occuring after the rising edge.
Article: 89943Sure thing. But when I do that, I expect the signal assertion duration has shifted as well. I can fiddle the code to do whatever I want it to do, but I'm trying to figure out why it mismatches with my expected behavior... maybe I wasn't clear in my original posting...Article: 89944
vssumesh wrote: > Ok .. but is it easy to simulate? And if we code it in a hierarchial > tree will it take more area than required. Please give little more > details in this. Also try to think about whether you really need a random accessible mux in your case. For example if you allways need the inputs in the same order you can load all of them into a shift register and shift them out. Kolja SulimmaArticle: 89945
For all the hardened FPGA addicts and please excuse the sales push. If anyone is interested in our lower spec Broaddown2's BD2-400, BD2-1000 then we are having a stock clearance next week. Details will follow on our website shortly but pricing will be GBP£160 (BD2-400) and GBP£190 (BD2-1000) only while stock lasts. Our MINI-CAN boards now have an uprated spec for those intersted in these boards. Details to follow on the website but essentially you get a XC3S1000 now in the FPGA hole. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.ukArticle: 89946
fastgreen2000@yahoo.com wrote:
> Yes, I'm doing just that for creating clock, and your post shed some
> light on what I wasn't paying attention to, but...
>
> I'm still confused. In the following testbench code, shouldn't it wait
> for a certain rising edge (whatever time it might correspond to), and
> assert 'sig1', at the time reported by 'now'? What I see is 'sig1' get
> asserted one clock after that.
>
> line 1 : wait until rising_edge(clk);
> line 2 : write (L, string'("1st rising edge : " & image(now)));
> line 3 : writeline (output, L);
> line 4 : sig1 <= '1'; -- I see this signal go high at 'now' + 1
> more clock cycle??
> -- note that lines 2,3,4 are
> occuring after the rising edge.
>
So you tell me that now is printed as 314 ns, but sig1 rises at 318 ns?
If that is so, it is unexpected for me too!
Article: 89947Subhasri krishnan <subhasri.krishnan@gmail.com> wrote: > I have to initialise an SDRAM with an LUT (48MB). I have the LUT in This should be possible with XMD (a Xilinx-Tool). At least I've seen a JPEG-example uploading the jpeg to sdram by issueing a few commands in a gui-wrapped terminal (iirc XMD). Perhaps this may help you, if not I could ask the one showing me this jpeg-example for detailed information. -- mail: adi@thur.de http://adi.thur.de PGP: v2-key via keyserver Nichts gegen eine bessere Hälfte, aber schöner sind zwei jüngere Viertel!Article: 89948
If you can boil down what you are seeing to under 20 lines of code, and post the 20 lines, I think people will be in a better position to identify the issue. -NewmanArticle: 89949
Hello all, Anybody knows when we can expect LFXP3 & LFXP6 in regular distributor channels? Thanks, M.
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Threads starting:
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