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> The ML401 is a great board, and great value, but the > rgb output just sucks. I am interested in this problem. What do you mean the RGB sucks? There is a real RGB chip on the board right? Is there something wrong with that chip? I read on the Xilinx web site that some of the analog gnds are mixed up with the digital gnds. Is it possible to lift these pins and ground them to the right places and improve the RGB output? Brad Smallridge aivision.comArticle: 90001
suppose I want calculate the log2(N) were N is an integer valued generic or constant parameter in my design, now, lets say i would like to use log2(N) as an upper bound in a for ... generate statement, is there a way to do this? I dont want the log2(N) to be synthesized into my hardware, i just want to use the result in a loop -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 90002
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11jtqvs3d0mbbc3@corp.supernews.com... >> The ML401 is a great board, and great value, but the >> rgb output just sucks. > > I am interested in this problem. What do you mean the > RGB sucks? The video out has asynchronous resonant spikes running through it. The spikes are about 100 mV p-p, and have a resonant frequency of about 250 MHz, with about 6 half-cycles present. There is also about 15 mV p-p of pixel clock and harmonics. > > There is a real RGB chip on the board right? > Is there something wrong with that chip? I don't think so. It's a fine chip that I've used in many designs. > > I read on the Xilinx web site that some of the analog gnds > are mixed up with the digital gnds. Is it possible to lift these > pins and ground them to the right places and improve the > RGB output? I have not tried that. It's often tricky to get a decent, low-impedance alternative ground. > > Brad Smallridge > aivision.com PeteArticle: 90003
> > The video out has asynchronous resonant spikes running > through it. The spikes are about 100 mV p-p, and have a > resonant frequency of about 250 MHz, with about 6 half-cycles > present. > > There is also about 15 mV p-p of pixel clock and harmonics. > Hard to believe when Xilinx tells us that they are signal integrity leader... (Sorry, just could not resist ;-) ThomasArticle: 90004
Hi Peter, Peter Ryser wrote: > A port of eCos to the PowerPC embedded in Virtex-II Pro and Virtex-4 FX > FPGAs exists. This could be your approach as proof of concept. Thank you for your suggestion. What concerns me is the cost of a V2-P or a V4-FX -- I doubt we could meet a reasonable target price for a potential consumer-oriented product. Thus, it would also be unreasonable to invest a significant amount of time in a SOPC product that we could not get to market. > Many other embedded OS have been ported to PowerPC and MicroBlaze. See > http://www.xilinx.com/products/design_resources/design_tool/grouping/embedded_os.htm > for a list of those. Thank you, but I have seen this and most of the other pages related to EDK/Microblaze/V2P. There aren't any other Open Source RTOSes listed there for Microblaze (besides John Williams's uCLinux), unless I've missed something. I suppose these days, without huge customers beating the doors of companies making requests, everything else is scattered to the wind... Ram.Article: 90005
I thought we were finished with you. That didn't last very long did it. After you threw such a retarded fit on here, I would think you would be embarassed to come back on here. You threw a big temper tantrum like I would expect from a 10 year old girl. Then I see that you came right back on not too much later. Dork Antti Lukats wrote: > as topic says. > any device in any package as chip only (can be bga as long as its not bare > die) or soldered on board (that can be partially non functional) as long as > jtag pins are connected to accessible points. > > can somebody help? > I can pay as private person (but can not place order). > > AnttiArticle: 90006
The same theory works anywhere.. in the case of an entity.. you put the type in a header and use the "library" string :-) I use the same thing in entities, processes and generates. Simon "Karthikeyan Subramaniyam" <karthiks@toNomOucShsPemAi.coMm> wrote in message news:dhltb0$rsg$1@home.itg.ti.com... > Simon > he's asking about how to use multi-dimentional arrays in port > declaration. not for signal/variable declaration. > > Rgds, > Karthik > > > Simon Peacock wrote: > > first you create a type.. then assign it... > > type v_typ is array (2 downto 0) of std_logic_vector(11 downto > > 0); > > signal v: v_typ > > > > now you can access it as > > v(i)(j) <= -- something > > > > Simon > > > > > > > > "eeh" <eehobbyist@yahoo.com.hk> wrote in message > > news:1128136736.906033.205550@z14g2000cwz.googlegroups.com... > > > >>Hi, > >> > >> > >>I am just beginner of VHDL. I want to define a 2 dimensional input > >>variable in entity. I think the syntax is something like this: > >> > >>v : in std_logic_vector(2 downto 0)(11 downto 0); > >> > >>Please advice. Thanks! > >> > > > > > > > > -- > Karthikeyan Subramaniyam, > Verification Engineer, > TooMuch Semiconductor Solutions Pvt. Ltd. > www.toomuchsemi.com > A Bangalore based startup specialising on services in EDA & Verification.Article: 90007
who the F*** designed your web site.... I know putting frames around product briefs lets you keep your logo.. but that's almost 2/3's of the screen gone... Simon translated: fire your web designer :-) "Antti Lukats" <antti@openchip.org> wrote in message news:dhm897$gms$05$1@news.t-online.com... > "Pete Fraser" <pfraser@covad.net> schrieb im Newsbeitrag > news:11jqt4dj0bhh71b@news.supernews.com... > > I'm doing a proof of concept that requires high quality video out. > > Either RGB or composite is fine (both would be great). > > > > Spartan III or V4 preferred, with add-on modules OK. > > > > The ML401 is a great board, and great value, but the > > rgb output just sucks. > > > > Anyone got any recommendations? > > http://www.hydraxc.com > > its not on the website yet, but there is base board for it that can be used > standalone with following specs > > Chrontel CH7301 for DVI or RGB out > V4 (SF363) can be fitted with LX15, LX25 or FX12 > 2 DDR2 memories > header for micron camera > header for char LCD > rs232 uart > > > > there is no composite out though, if you need that then xilinx multimedia > board has it, also several other boards are available > > Antti > > > > >Article: 90008
> > I measure a CLK2X/8 which should be 38.88MHz, but it is > actually half of that and the locked pin is not active. > My Xilinx Spartan-3 Starter Kit, with -ES silicon, has exhibited similar DCM problems whenever the design uses the SRAM I/O pins. Pin count/slew/drive settings for the SRAM buses are well within the published SSO limits for the part, but the DCM's on the left side of the chip unlock once the SRAM lines ( mostly on the left side ) start toggling. Changing the DCM update attribute to FFFF, changing the 2x DCM feedback to CLK0, and switching to CLKFX instead of CLK2X all failed to eliminate the problem. The only thing that helped was LOC'ing the DCM's to the right side of the chip: attribute loc : string ; attribute loc of DCM1 : label is "DCM_X1Y0"; attribute loc of DCM2 : label is "DCM_X1Y1"; Also, check out Answer Record 19827 and the S3 errata. BrianArticle: 90009
Kolja Sulimma wrote:
>vssumesh wrote:
>
>
>>Ok .. but is it easy to simulate? And if we code it in a hierarchial
>>tree will it take more area than required. Please give little more
>>details in this.
>>
>>
>Also try to think about whether you really need a random accessible mux
>in your case. For example if you allways need the inputs in the same
>order you can load all of them into a shift register and shift them out.
>
>Kolja Sulimma
>
>
you can get better pipelined performance by decoding the selects before
the first level then combining the first level outputs in an OR tree.
You can also use the carry chains, or if using virtexII the horizontal
or chains with this method to help reduce the size of the logic. This
is for a random selection sequence. As Kolja said,, a shift register
might be a better choice if you can constrain the selection order. If
it is to read back registers that you've written into a design, you can
use a block ram as a shadow for the registers and read back the block
RAM. Finally, if you can afford the latency, you can get better place
and route results by going with a linear structure.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90010I'm glad Antti is back. I noticed of late that there looks to be a lot more people asking questions than providing answers. Antti helped out a lot of people with thoughtful answers. I personally would like to say, Welcome Back Antti! -NewmanArticle: 90011
Dork, don't play school-mistress. If Antti wants to come back, we should welcome him. He has given us much more help than you and many others ever did. We all have our idiosyncracies, and Antti has more than the average... But we should be glad to have him back. Life was less interesting without him. Peter Alfke, from home. seannstifler69@hotmail.com wrote: > I thought we were finished with you. That didn't last very long did it. > After you threw such a retarded fit on here, I would think you would be > embarassed to come back on here. > > You threw a big temper tantrum like I would expect from a 10 year old > girl. Then I see that you came right back on not too much later. > > Dork > > > Antti Lukats wrote: > > as topic says. > > any device in any package as chip only (can be bga as long as its not bare > > die) or soldered on board (that can be partially non functional) as long as > > jtag pins are connected to accessible points. > > > > can somebody help? > > I can pay as private person (but can not place order). > > > > AnttiArticle: 90012
Xilinx is number one. Might as well start using the dominant number one company. zoharl3@gmail.com wrote: > Hi, > I'd like to learn programming a micro chip. > I've heard the Altera is popular. > Which one should I specifically deal with, and how do I build a burner > (programming it) for it? (I need a circuit diagram) > > ThanksArticle: 90013
Francis I used to run this little script (below) after running ProjNav. There are other options to data2bram that help verify the correct data is going to the right bram. This worked with ISE6_2. -Newman ####################################################################### # This script runs data2bram to populate BRAMs with program information. # This is automatically generated by LibGen. # ####################################################################### echo Initializing BRAMs with program information ... echo Inserting executable image data2bram -bm implementation/system_bd -bt projnav/system -bd ppc405_i/code/executable.elf tag bram1 -o b projnav/download.bitArticle: 90014
Hi everyone, Now that I've got the Xilinx Web-tools running reasonably well under Linux, I'm noticing that sch2vhld, which converts a schema-drawing into vhdl, is spending almost all of its time waiting. It's not using the CPU, disk or network at all. This happens both when called from the command line directly, or from within ISE. This causes sch2vhdl to take about 4 minutes to convert just one small schematic, on a 1.4GHz Centrino CPU. And my current design consists of 6 schematics... The other tools (xst, mapper etc.) actually use the CPU and work with a normal speed. Does anybody know how to encourage sch2vhdl to actually get on with the job at hand? Regards, Paul Boven.Article: 90015
In article <1128269691.418736@blaat.sara.nl>,
Paul Boven <p.boven@chello.nl> writes:
|> Hi everyone,
|>
|> Now that I've got the Xilinx Web-tools running reasonably well under
|> Linux, I'm noticing that sch2vhld, which converts a schema-drawing into
|> vhdl, is spending almost all of its time waiting. It's not using the
|> CPU, disk or network at all. This happens both when called from the
|> command line directly, or from within ISE. This causes sch2vhdl to take
|> about 4 minutes to convert just one small schematic, on a 1.4GHz
|> Centrino CPU. And my current design consists of 6 schematics...
|> The other tools (xst, mapper etc.) actually use the CPU and work with a
|> normal speed.
|> Does anybody know how to encourage sch2vhdl to actually get on with the
|> job at hand?
I haven't used it,so no help here. But you can find out what it is doing by
starting it with strace (only syscalls) or ltrace (library-calls).
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 90016
Hi Georg, everyone,
Georg Acher wrote:
> Paul Boven <p.boven@chello.nl> writes:
> > Does anybody know how to encourage sch2vhdl to actually get on with the
> > job at hand?
time sch2vhdl -family spartan3 -flat -w -suppress main2.sch
Release 7.1i - sch2vhdl H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
real 3m8.969s
user 0m2.564s
sys 0m0.740s
Ah, great. So it took over 3 minutes to do 3 seconds of CPU work.
> I haven't used it,so no help here. But you can find out what it is doing by
> starting it with strace (only syscalls) or ltrace (library-calls).
I've done that: mostly it's waiting for children it just started that
aren't doing much either, given the fact that there is no CPU load
whatsoever while sch2vhdl runs. The block below keeps recurring.
stat64("/tmp/xil_Q0lm0J", 0xbf98aa7c) = -1 ENOENT (No such file or
directory)
stat64("/tmp", {st_mode=S_IFDIR|S_ISVTX|0777, st_size=4096, ...}) = 0
lstat64("/tmp/xil_qOGSpj", 0xbf989b30) = -1 ENOENT (No such file or
directory)
stat64("/tmp/xil_qOGSpj", 0xbf98aa7c) = -1 ENOENT (No such file or
directory)
open("/tmp/xil_qOGSpj", O_WRONLY|O_CREAT, 0666) = 4
close(4) = 0
unlink("/tmp/xil_qOGSpj") = 0
vfork() = 13059
rt_sigaction(SIGCHLD, {SIG_DFL}, {SIG_DFL}, 8) = 0
waitpid(13059, [{WIFEXITED(s) && WEXITSTATUS(s) == 0}], 0) = 13059
--- SIGCHLD (Child exited) @ 0 (0) ---
Regards, Paul Boven.
Article: 90017Hi, If you are considering purchasing a Xilinx FPGA-based PCI development board, and is planning to use it for personal use, I recommend purchasing a personal version of BDS XPCI PCI IP core. BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core developed by Brace Design Solutions. BDS XPCI32 PCI IP core is available for as little as $100 for non-commercial, non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200. Since the pricing starts at only $100, it is ideal for HDL learners, FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or student graduation projects. BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which allows the user to simulate the design extensively on an HDL simulator like ModelSim before firing up the FPGA. VHDL support is currently poor, but VHDL porting of reference designs and PCI testbench should be available in a month. BDS XPCI PCI IP core officially supports the following PCI boards. - Insight Electronics Spartan-II 150 PCI (Already discontinued) - Insight Electronics Spartan-II 200 PCI Development Kit http://www.memec.com/uploaded/SpartanII200PCI.pdf BDS XPCI PCI IP core "unofficially" supports the following PCI boards. - Avnet Xilinx Spartan-3 Evaluation Kit http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf - Enterpoint Broaddown2 Development Board http://www.enterpoint.co.uk/moelbryn/broaddown2.html So with BDS XPCI PCI IP core, almost anyone can make their own PCI device for about $400 to $500. ($300 to $400 for the board + $100 for BDS XPCI32 PCI IP core) For commercial users who want to modify a Xilinx LogiCORE PCI or want to convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL. For more information, visit Brace Design Solutions website at http://www.bracedesignsolutions.com. Kevin Brace G.H. Hardy wrote: > Hi all, > > I might be getting a Xilinx development board soon. I downloaded the > free Web ISE toolkit from Xilinx. I am considering puting Xilinx's > LogicCORE PCI IP core into it. I'm very new to this. So I'm looking for > advice from the community. > > Will this LogicCORE come as a particular file that I can drop into my > design? I would be writing the rest of my design in verilog. I presume > the LogicCORE would not be in verilog but some pregenerated block that > I can add in. I presume I would synthesize my verilog and then before > the PAR stage, I would need to place this pregenerated block in order > to get the final bit file. Is this correct? > > I'm trying to understand the various manuals but it's confusing. They > talk about using a CORE Generator IP Update, manual installation and > directly downloading. I think the first two are relevant to me but I > don't see CORE Generator in Web ISE. Is this something that's feasible > with Web ISE or would I need to purchase the full ISE? > > Thanks! > GHH > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 90018
Hello Broaddown2 customers, Those users considering purchasing Broaddown2 Development Board for personal projects might also want to consider purchasing BDS XPCI PCI IP core to accelerate the development. BDS XPCI PCI IP core is a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core developed by Brace Design Solutions. BDS XPCI32 PCI IP core is available for as little as $100 for non-commercial, non-profit, personal use, and the same 64-bit version BDS XPCI64 PCI IP core (Includes BDS XPCI32 PCI IP core) goes for $200. Since the pricing starts at only $100, it is ideal for HDL learners, FPGA beginners, FPGA hobbyists, computer hardware enthusiasts, or student graduation projects. BDS XPCI PCI IP core comes with a PCI testbench for Verilog HDL which allows the user to simulate the design extensively on an HDL simulator like ModelSim before firing up the FPGA. VHDL support is currently poor, but VHDL porting of reference designs and PCI testbench should be available in a month. BDS XPCI PCI IP core officially supports the following PCI boards. - Insight Electronics Spartan-II 150 PCI (Already discontinued) - Insight Electronics Spartan-II 200 PCI Development Kit http://www.memec.com/uploaded/SpartanII200PCI.pdf BDS XPCI PCI IP core "unofficially" supports the following PCI boards. - Avnet Xilinx Spartan-3 Evaluation Kit http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx%20Spartan-3%20Evaluation%20Kit%20-%20Brief%20022504F.pdf - Enterpoint Broaddown2 Development Board http://www.enterpoint.co.uk/moelbryn/broaddown2.html So with BDS XPCI PCI IP core, almost anyone can make their own PCI device for about $400 to $500. ($300 to $400 for the board + $100 for BDS XPCI32 PCI IP core) For commercial users who want to modify a Xilinx LogiCORE PCI or want to convert a design that uses Xilinx LogiCORE PCI to an ASIC (FPGA to ASIC conversion), BDS XPCI PCI IP core is also available in Verilog HDL RTL. For more information, visit Brace Design Solutions website at http://www.bracedesignsolutions.com. Kevin Brace John Adair wrote: > For all the hardened FPGA addicts and please excuse the sales push. > > If anyone is interested in our lower spec Broaddown2's BD2-400, BD2-1000 > then we are having a stock clearance next week. Details will follow on our > website shortly but pricing will be GBP£160 (BD2-400) and GBP£190 (BD2-1000) > only while stock lasts. > > Our MINI-CAN boards now have an uprated spec for those intersted in these > boards. Details to follow on the website but essentially you get a XC3S1000 > now in the FPGA hole. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 90019
Hi Antti, Glad to see you back! > Altera used to make so much noise here, that I could not belive my eyes > seing Stratix-II GX devices at Altera website, and no posting about Altera > being the greatest at c.a.f. !!! Personally, while not directly working for Altera, I'm pretty occupied with a six-week old son who unfortunately has inherited my aversion to sleep (instead of my wife's addiction to it) ;-) I guess Altera's a bit quiet because there's no huge news - the Virtex4 vs Stratix2 war is now fought in the field instead of the press, Quartus II version 5.1 isn't out yet (but soon, my friend, soon) and neither are Stratix2GX and Hardcopy2 (but which will give FaultyBits - er - EasyPath a run for its money very soon). Best regards, BenArticle: 90020
Another option for a Spartan 3 board can be found at www.dulseelectronics.com. There are also a number of tutorials there for beginning with Xilinx ISE Webpack. Philip Nowe "Kutaj Vamor" <kv> wrote in message news:43366eea$0$21885$afc38c87@news.optusnet.com.au... > Dear FPGA and VHDL Experts, > > I am new to FPGA and VHDL. I would like to learn VHDL and start > experimenting FPGA. I beleive I learn faster and better by experimenting. > What would you recommend for beginners like me to getting started with > VHDL and FPGA experimentation ? > Which SW (for WinXP and/or Fedora Linux ) for VHDL? > Which start-up experimentation board for FPGA? > Which URL, books etc for easy to start experiment? > > Many thanks for your help. > > Kutaj Vamor > > > > >Article: 90021
I am currently designing an RLDRAM-II controller in a Xilinx Virtex-II Pro with the following specifications: Device = MT49H8M36FM-5 Array = 1 device deep x 4 devices wide (8 Meg x 144) Speed = 175 MHz Mode value = 388 hex Configuration = 1 (RC = 4, RL=4, WL=5) Burst length = 4 Address bus = nonmultiplexed DLL = enabled Impedance matching = external On-die termination = enabled The design works well except for one major problem. When reading a four data-phase burst, the third and fourth data-phase contains identical data. The value for phase three is duplicated in phase four. If the written data is A-B-C-D, the read data will be A-B-C-C. This symptom is permanent and identical over the entire width and depth of the memory space. There is reason to believe that the problem is not caused by an incorrect write sequence, because random data in memory after power-on is read back with the same symptom (identical data in third and fourth data-phase). The problem is probably not caused by data capture either, because I am observing the read data just after the input flip-flops (using Xilinx ChipScope). I have been delaying the read clock (QK) over one clock period in 300 ps intervals and can never see the correct data sequence. Have you seen this problem earlier? Are the RAM devices in an invalid state? Can an incorrect initialization sequence cause this kind of behavior? I have implemented the initialization sequence according to the data sheet. Thanks in advance. Best regards Elling Diesen VMETRO asa Oslo, NorwayArticle: 90022
You can have a look at the CORDIC algorithm. Its got a good way of calculating log of a number . NiteshArticle: 90023
Hi,
I've tried to assign pins in PACE for a verilog module like this (I
selected a spartan 3 fg456 package):
module test_top(clkin, datain, dataout);
input clkin;
input datain;
output dataout;
always @ (posedge clkin)
dataout <= datain;
endmodule
In the Design Object List from PACE, the drop down list of the Loc
column has only bank numbers (e.q BANK0, BANK1, ...) and no pin names
(e.q. A10, B11, ...).
Do you have any idea why this happens?
Thank you,
Adrian
Article: 90024I dont fully understand what you are suggesting. But it seems to me that you are advicing a pipelined operation. But that is not possible in the design. It is a completely random MUX. The task is to take data from a 240 byte register and to arrange that into a 64 byte wide data bus (simultanious)(each output byte can take data from any of the 240 registers). And the selection bits are direct to each mux. That is 240 bit selction lines into each MUX. I tried to implement it with the LUT but it gave the same result. I am ready to wait for days but the ISE is simply giving up. If i reduce the output by 32 it is giving the output. >" You can also use the carry chains, or if using virtexII the horizontal >or chains with this method to help reduce the size of the logic." Please give me little more details on this. I tried to to implement normal ANDing and then ORed all the bits. Sumesh
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