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Simon Heinzle wrote: > First of all, thanks for the reply! > > Could these 'standard' libraries be used for timing analysis, e.g. for a > core gen normally used for ASICs (to get a rough but more meaningful timing > analysis than without any information)? No. But: Your asic synthesis tool probably supplies a minimal example library. (Our design compiler here for example has an AND-OR-NOT library with only three cells) You can generate the core from that and then export the resulting netlist as VHDL. Then you can add entities for the three cells and run the result through WebPack. (Free download) The result will be exact in the sense that the circuit really operates in an FPGA at the resulting frequency. But of course your core generator likely has made some design decisions that are really suboptimal for FPGAs. Kolja SulimmaArticle: 90201
> Zarawrote: On Wed, 05 Oct 2005 19:16:02 -0500, > mvetromille@gmail-dot-com.no-spam.invalid (Melissa Vetromille) wrote: > > > You must create a new chipscope icon with Disable Boundary Scan > Component Instance. hta will give you an Icon with more ports than > usual, these ports must be connected to the corresponding ports of the > opb_mdm component (use Show ports with default connections when > connecting ports) I don't know how to disable the boundary scan component instance. I tryied to do this, but it was unsuccessfull. Could you help me again? Thank you!Article: 90202
Hi All Is it possible to send test vectors through Chipscope to the FPGA via JTAG and then get outputs to verify the functionality of the desgin configured? Can anyone please explain? AnujaArticle: 90203
Newman wrote: > aholt...@gmail.com wrote: > > The Xilinx website isn't too clear with respect to the evaluation EDK > > included with the Spartan-3 starter kit. Does anyone know if it is time > > limited or feature limited? Can I run the reference microblaze designs > > with it? Also, does anyone know if the starter kit will ship with > > ISE/EDK 8.1i when it itself ships? Thanks! > > > > cheers, > > aaron > > Aaron, > IIRC, the Spartan 3 Eval kit shipped with a 60 day eval EDK 6_3 back > in Feb 2005. It also came with a 60 day ISE6_3 eval. I have no > information what they ship now. > > -Newman Thanks. One other thing, do the discs come with the linux binaries as well? cheers, aaronArticle: 90204
aholtzma@gmail.com wrote: > Newman wrote: > > aholt...@gmail.com wrote: > > > The Xilinx website isn't too clear with respect to the evaluation EDK > > > included with the Spartan-3 starter kit. Does anyone know if it is time > > > limited or feature limited? Can I run the reference microblaze designs > > > with it? Also, does anyone know if the starter kit will ship with > > > ISE/EDK 8.1i when it itself ships? Thanks! > > > > > > cheers, > > > aaron > > > > Aaron, > > IIRC, the Spartan 3 Eval kit shipped with a 60 day eval EDK 6_3 back > > in Feb 2005. It also came with a 60 day ISE6_3 eval. I have no > > information what they ship now. > > > > -Newman > Cannot remember exactly, because I do not use the Linux versions, but if I had to take a guess, I would say yes. -Newman > Thanks. One other thing, do the discs come with the linux binaries as > well? > > cheers, > aaronArticle: 90205
Adding a new microblaze in a EDK project is ok, I already now this but.. For me it is easier to have two different EDK included in ISE. I want to instantiate multiple EDK (as component) connected to my IP made in ISE. Will be easier in ISE because I have a lot of pins. Is it still possible? Zara wrote: > Francis St-Pierre wrote: > >> When I try to use more than one embedded system in ISE, it says: >> Only one source of type 'XPS FILE' is allowed in a project. >> Why can't I add more than one system.xmp file to ISE? >> >> I need two embedded systems because the hardware and software in each >> one are different. And I can not put the two EDK projects in only one >> because my VHDL Top Level in ISE will instantiate the first EDK >> project only once and the other several times. I want to create a >> multiembedded design. ISE should be able to have several embedded >> systems; that is not normal! >> >> I also tried to add a EDK project system.xmp in a ISE project >> created(export to ProjNav) with another EDK project. But it can not >> work because the two EDK project have "system" for name as >> sub-module. I try to put "system_something" as sub-module name, but >> EDK always export it as "system" name. >> >> How to have multiple EDK projects in ISE? >> >> >> Francis St-Pierre >> >> École Polytechnique de Montréal >> http://www.grm.polymtl.ca/~stpierre/ > > > I have tried to add a new microblaze within the same EDK project, and it > seems to work. (EDK 7.1.02i)Article: 90206
Hi kedar, > I am doing some work targeted to StratixGX family for me RTL or gate > delay simulation is a must. > > Can i do a post synthesis simulation in Modelsim for stratix GX Family > using the synthesis output design.vho file from QuartusII. > But this simulation should include gate delays specifically. > > as like in Xilinx I can do a pre Map simulation which gives gate > delays. Modelsim has the option to use a so-called SDF backannotation file to use the gate (and wire) delays. Quartus generates the delay backannotation file as <yourdesign>.sdo. For more info, look up SDF in the Modelsim manual. Best regards, BenArticle: 90207
pulse train can be sent using vio but it is limited to length of 16. I think it is because of SRLs being use in vio? any one any idea?Article: 90208
Marco wrote: > Hallo, > I have made a clock divider (1 MHz) with a counter connected to system clock > (50 MHz). > This counter has a threshold which goes high on the last count. > This pulse drives some blocks as a clock enable (the clock input of these > blocks is connected to system clock). > Every block is falling edge sensitive. > > The pulse drives also a FSM where every state send high/low 4 signals. > > In this way there is no gating clock, but now pulse signal has high load. > > I can't use DCM because of the too low out frequency. > > What could I do to reduce load and skew? > > The only way is to add a BUFG? I assume that you'd be using a BUFG for your clock? You probably want to do that, if you aren't already. Simplest way to do what you want (I think) is to replicate your clock enable signal (or use a bufg, I guess) - what synthesis tool are you using? Some of them, at least, do this automatically. JeremyArticle: 90209
Hi Austin, [snip] > Seems like a simple problem to me: choose H2 and have a potentially > career limiting experience, or choose EasyPath and go home happy every > night.... FPGA's are often touted as high-cost (sorry, A, A, L and X are) risk-mitigating devices versus ASIC. EasyPath users would indeed be the types who find the risk/delay involved with saving money by going to any kind of ASIC completely unacceptable but are running enough volume to recover the NRE charge for Easypath. HC2 is supposed to sit between standard cell and FPGA (much closer to standard cell, I'll give you), which should find some high-volume customers with fast time-to-market and pricing requirements that are too tight for EasyPath but are not comfortable with standard-cell risk and development time. If you're making a flat-panel TV, a single cent saved in item cost is easily recovered in NRE, signal integrity testing etc. Unfortunately these cents are also saved by using crappy connectors, bad crystals, flaky switches etc, but that's not the issue here. People in Purchasing do take these risks... The markets for both solutions are different. One sort-of compelling thing about HC2 on the engineering side, by the way is this: have you ever designed an ASIC from a nice and user-friendly GUI? With Quartus you can... Oh, and I know someone who was fired for choosing IBM... Best regards, BenArticle: 90210
"Marco" <marcotoschi@nospam.it> wrote in message news:di2she$iji$1@news.ngi.it... > Hallo, > I have made a clock divider (1 MHz) with a counter connected to system > clock (50 MHz). > This counter has a threshold which goes high on the last count. > This pulse drives some blocks as a clock enable (the clock input of these > blocks is connected to system clock). > Every block is falling edge sensitive. > Why are you using the falling edge? Your 50MHz clock should come from a BUFG and only use one edge (either rising or falling) in all the places it goes. So, the counter and the 'blocks' you mention should all use the same edge. Is that what you are doing? > > The pulse drives also a FSM where every state send high/low 4 signals. > > In this way there is no gating clock, but now pulse signal has high load. > > I can't use DCM because of the too low out frequency. > > What could I do to reduce load and skew? > The enable signal will be automatically buffered by the Xilinx routing. As long as you've told the timing analyser that your main clock is going at 50MHz, you don't have to worry about 'load' (or fanout as it's often called) or skew. To send a 1MHz signal out of the FPGA, as you mentioned in your other thread, you might like to consider also generating a 2MHz enable from your 50 MHz counter, as well as the 1MHz one, to toggle the IOB flip-flop. > > The only way is to add a BUFG? > > Many Thanks in advance and sorry for my terrible english > Marco Toschi > Ciao, SymsArticle: 90211
Bill wrote: > As I wrote before, the input signal is synchronous to a 1.8 MHz clock and I > want to synchronize it to a 24 MHz clock. ... > After reading the XAPP094 I found a new way to qualify the signal to be > synchronous to 24 MHz. (se VHDL listing below). ... > How it works: The input signal is first sampled at the rising clock edge > (sample a) then again on falling clock edge (sample b). If the two samples > (a and b) are the same then I change the output signal on the next rising > edge to the value of a. ... > What do you all think about this solution? Not a good solution. This would actually increase the likelyhood of failure without decreasing worse case delay. Instead of a full cycle of delay for the input register(s) to settle, you only allow a half a cycle worse case, minus the delay of your comparitor. Thus the register after the comparison logic is far more likely to have a bogus signal (improper level or set-up time) as its input. Better to just use a full clock cycle (when sufficiently slow for registers which have been properly characterized by the technology vendor) between registers with no fan out or significant routing delay between them. Or, *if* the technology is fast enough for a half clock cycle of flip-flop resolution time to easily exceed your desired reliability level (after subtracting maximum clock jitter and worse case duty cycle asymmetry, etc.), then if you need a faster response, you might consider using just a half clock delay without any gating (comparison logic, etc.). But this is riskier because of the larger number of factors which could cut into you timing margin. IMHO. YMMV. -- rhn A.T nicholson d.O.t C-o-MArticle: 90212
Subhasri krishnan wrote: > please tell me what should i do now to set it right? should i read > something or should i check for something? why does it detect so many > devices when i have only one FPGA in there? > ....thanks > I've seen this happen with a dodgy JTAG cable. JeremyArticle: 90213
Hello: Has anyone actually gotten the master functionality in the PLB IPIF to work correctly? I have been making slave peripherals without a problem. I have an application where I am trying to directly transfer 64-bit data from my peripheral to DDR ram. This problem came about as the PowerPC in the Virtex II pro requires 2 bus reads and writes to move 64-bit data around. I have the problem that I hneed to stream multiple channels of data into my DDR Ram and CPU intervention would be just too slow. Here is my hardware setup: I have the Digilent VirtexII Pro develop board with a 512MB DIMM Installed. (This memory has been verfied to work with extensive memory tests). The DDR RAM starts at address 0x000000000. Here is my problem. I used the create peripheral wizard to create a simple PLB peripheral is User SW register support and simple master support. I could find very little documentation on the master interface except for a timing diagram on a Master Burst read and write operation. I have very simple logic the upon a trigger (write to one register) will initiate a state machine to start a master operation. I give the master attachment static addresses for where the data is and where needs to end up. I always get the Bus2IP_MstLastAck signal indicating that everything is all done but the data never gets transfered. I try to verify the operation by looking at my target address to see if data ever makes it (which it doesn't) Does anyone out there have any experience with this? Also, I notice that IPIF master operations always take 2 transactions. If I want to write to a location, it first does a local read to get data and a remote write to send the data. It would be nice is there was a single transaction interface. I already have the 64-bit data ready. I just want to provide it to the interface and have it directly send the data without a bus read. -EliArticle: 90214
Eli Hughes wrote: > Has anyone actually gotten the master functionality in the PLB IPIF to > work correctly? I have been making slave peripherals without a problem. I have not had much luck with the Xilinx tools for creating peripherals. I tried and failed to use ipif to create a plb master. I would just read http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/8BA965C773B2E0ED87256AB20082CC9F/$file/64bitPlbBus.pdf (search for 64bitplbbus.pdf on www.ibm.com) and write it by hand. This worked great for me. Alan NishiokaArticle: 90215
Hello all, I've recently been examining methods for acceleration of matrix inversion... does anyone know of any hardware acceleration or parallel processesing succesful method for matrix inversion? Thanks for your help, RafaelArticle: 90216
Phil Hays wrote: > I should have mentioned this above, but I unchecked the box (shift > register extraction) so ISE didn't convert the FFs into a SRL16. > > Probably better do cover this in the code. Add this line to the > Verilog: > > // synthesis attribute shreg_extract of ss is no; Thanks for this, Phil. My code actually synthesizes to a 3-bit shift register (two for ss plus one for the output). This was implemented in a SRL16 and I was wondering if that "broke" the synchronizer. If I specify two flip-flops it doesn't use an SRL16. I'm still learning and I'm not familiar with the whens and whys of contraints, so this is an excellent example for me. Thanks again. Regards, Paul.Article: 90217
Thanks for the answer. In ISE 7.1, data2bram has been changed to data2mem. This is already done in ISE, it prints out: Analyzing file microblaze_UNI/code/executable.elf... Running Data2Mem with the following command: data2mem -bm implementation/system_bd -bt implementation/system.bit -bd microblaze_UNI/code/executable.elf tag bram1 -o b implementation/download.bit Memory Initialization completed successfully. Looks like it initialize it, but program runs correctly only when imported back to EDK and doing a Update Bitstream. Newman wrote: > Francis > I used to run this little script (below) after running ProjNav. > There are other options to data2bram that help verify the correct data > is going to the right bram. > This worked with ISE6_2. > > -Newman > > ####################################################################### > # This script runs data2bram to populate BRAMs with program > information. > # This is automatically generated by LibGen. > # > ####################################################################### > echo Initializing BRAMs with program information ... > echo Inserting executable image > > data2bram -bm implementation/system_bd -bt projnav/system -bd > ppc405_i/code/executable.elf tag bram1 -o b projnav/download.bit >Article: 90218
Paul, The SR16 is not a chain of master slave flip flops, so their metastability resolution is not going to very good at all. In fact, they may be exactly the wrong choice to use as asynchronous signal synchronizers! The SRL16 is more like a charge transfer chain with two clock phases internally (bucket brigade). That would make it preserve a metastable state through all 16 stages.....(as it transferred from one stage to the next). Austin Paul Marciano wrote: > Phil Hays wrote: > >>I should have mentioned this above, but I unchecked the box (shift >>register extraction) so ISE didn't convert the FFs into a SRL16. >> >>Probably better do cover this in the code. Add this line to the >>Verilog: >> >> // synthesis attribute shreg_extract of ss is no; > > > Thanks for this, Phil. My code actually synthesizes to a 3-bit shift > register (two for ss plus one for the output). This was implemented in > a SRL16 and I was wondering if that "broke" the synchronizer. > > If I specify two flip-flops it doesn't use an SRL16. > > I'm still learning and I'm not familiar with the whens and whys of > contraints, so this is an excellent example for me. > > Thanks again. > > Regards, > Paul. >Article: 90219
A general question: Synchronizers seem to be a basic building block, whether you have external signals to sample or internal clock domains to cross. Yet to use them seems to require careful constraint specification. I wonder if it would make sense for there to be a language construct to describe a sychronizer such that the tools would just do right thing(TM) without having to get into these tricky details? Or maybe for experienced engineer these details aren't tricky? Regards, Paul.Article: 90220
For those of you asking for details of Raggedstone1 the initial draft spec is here http://www.enterpoint.co.uk/moelbryn/raggedstone1.html . Pictures maybe tomorrow. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Very Cheap Spartan3 PCI Development Board. http://www.enterpoint.co.ukArticle: 90221
rafaelcns@gmail.com wrote: > Hello all, > > I've recently been examining methods for acceleration of matrix > inversion... does anyone know of any hardware acceleration or > parallel processesing succesful method for matrix inversion? > > Thanks for your help, > > Rafael I believe AccelChip has some IP for that; probably a VHDL generator... www.accelchip.comArticle: 90222
If you re-write the code to use these attributes, you will likely get
what you want out of the synchronization circuit:
module test(input clk, input in_sig, output reg out_sig);
(* ASYNC_REG="TRUE", SHIFT_EXTRACT="NO", RLOC="X0Y0" *) reg [1:0] ss;
always @(posedge clk)
begin
out_sig <= ss[1];
ss <= { ss[0], in_sig };
end
endmodule
The SHIFT_EXTRACT keeps the registers from being implemented in an SRL,
the RLOC places both registers into a single slice (as close as you can
get) and the ASYNC_REG allow you to simulate the asynchronous interface
without X's being driven all over your circuit.
-- Brian
Austin Lesea wrote:
> Paul,
>
> The SR16 is not a chain of master slave flip flops, so their
> metastability resolution is not going to very good at all. In fact,
> they may be exactly the wrong choice to use as asynchronous signal
> synchronizers!
>
> The SRL16 is more like a charge transfer chain with two clock phases
> internally (bucket brigade). That would make it preserve a metastable
> state through all 16 stages.....(as it transferred from one stage to the
> next).
>
> Austin
>
> Paul Marciano wrote:
>
>> Phil Hays wrote:
>>
>>> I should have mentioned this above, but I unchecked the box (shift
>>> register extraction) so ISE didn't convert the FFs into a SRL16.
>>>
>>> Probably better do cover this in the code. Add this line to the
>>> Verilog:
>>>
>>> // synthesis attribute shreg_extract of ss is no;
>>
>>
>>
>> Thanks for this, Phil. My code actually synthesizes to a 3-bit shift
>> register (two for ss plus one for the output). This was implemented in
>> a SRL16 and I was wondering if that "broke" the synchronizer.
>>
>> If I specify two flip-flops it doesn't use an SRL16.
>>
>> I'm still learning and I'm not familiar with the whens and whys of
>> contraints, so this is an excellent example for me.
>>
>> Thanks again.
>>
>> Regards,
>> Paul.
>>
Article: 90223
HELP!
How to constrain source-synchronous DDR inputs in Xilinx?
In Synplify Pro?
Double Data Rate input scenario:
CLK = 500MHz (Period = 2ns, Pd/2=1ns, Pd/4=0.5ns)
Data rate = 1.0 Gb/sec (Ideal bit valid window = 1ns)
time t=0.0 1.0 2.0 3.0 4.0 etc...
__________ __________ _______
CLK _________| |__________| |_________|
_____________________________________________________________
DATAi___X__________X__________X__________X__________X__________X__
_____________________________________________________________
DATAa___XXX_______XX__________XXX_______XX__________XXX_______XX__
DATAi = ideal (perfect edges, 0.5ns Tsu/Th before/after CLK edge)
DATAa = actual (degraded edges, smaller valid window, less Tsu/Th)
Assume DATAa is valid 300ps before clock edge, 400ps after clock edge,
for a total valid time of 700ps.
The clock does go into a DCM, and data is captured in DDR IOB flops
Assume no clock jitter either; I'm just trying to figure out the Xilinx
UCF constraint syntax by example; their data books are inconsistent...
# With this:
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 2.0 ns HIGH 50.00%;
NET "DATA" TNM = "DATA";
# I've tried this:
TIMEGRP "DATA" OFFSET = IN: 0.3 : BEFORE CLK;
TIMEGRP "DATA" OFFSET = IN: 0.4 : AFTER CLK;
# And this:
TIMEGRP "DATA" OFFSET = IN: 0.3 VALID 0.7: BEFORE CLK HIGH;
TIMEGRP "DATA" OFFSET = IN: 0.4 VALID 0.7: BEFORE CLK FALL;
And several other variants, but get nothing sensible (or nothing at
all) out of the compiler and timing reports. Ditto for entering
Synplicity scripts and asking it to pass good .ucf/ncf forward...
I'm much more accustomed to the Synopsys Design Constraints format
(DesignCompiler/PrimeTime), and I'm struggling to get this thru
Synplify and ISE.
Sorry if the post is premature. I didn't find much yet by googling,
but wanted to get this out to the world before the weekend, since
I'll since I'll be working most of it. 8-P
Thanks in advance for your help!
mj
Article: 90224Hi, We are using Xilinx Spartan2E in our platform and so far functioning of every logical cores was looking good. Today, I saw some weird behaviour after addng additional logic, all of sudden I was missing some signals coming out of FPGA and some signals looks different. This additional logic does not interfer with the exisitng logic cores. I am reaching upper limit of FPGA resource but still I can fit in all the logic cores. So my question is, by utilizing the FPGA resource around 90%, does the behaviour of FPGA logics becomes unpredictible ? Any pointers or suggestions in this regard is much appreciated. Thank you in advance. -Kiran
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