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srini, Virtex II was the first family to boast of having (almost) fully buffered Interconnect. One of the advantages was that placement and routing could be done much faster by our software with little thought made to inserting buffers (as buffers were not required). With the buffering built into each path, the use of the path provided the proper drive, without the user having to be concerned. Virtex II was the beginning of the cacth phrase: "we do the ultra deep submicron engineering, so you don't have to." It was also the beginning of significant use of FPGAs as a solution instead of designing their own ASIC, so we had to train many ASIC engineers that were used to designing their own clock trees, and solving signal buffering issues, to 'trust' us (which was completely unnatural for them, yet there was no reason for them to worry about all these ASIC issues, as we had already solved them). As others have already indicated, play around, and see what makes a difference. Get comfortable with the technology. But, I would encourage you to start a new design with a newer part. Not that Virtex II is obsolete (it and the Virtex II Pro are the most successful and profitable FPGA lines in history), but the Virtex 4 is much more power efficient, and less cost per function, and has superior signal integrity with the SparseChevon(tm) package. AustinArticle: 102301
Piotr, Since no one else seems to wish to answer your technical questions, I will: see below Austin > 1. what is their performance (relatively to the older Spartan 3 stepping 4) > Almost identical. 3E uses the same process as 3. The families are cost optimized for logic, and the other for IO. > 2. can I use a multiplier and its "neighbour" BRAM simultaneously, > i.e. is there enough routing? The routing is the same as Spartan 3. If you had problems before, then you will have them again (with a particular routing). Not sure what you are trying to do. There may be a different suggested way to solve the problem using these families' architecture. > 3. can I clock the device (preferably differential mode) using > a 50MHz sine, extremely pure clock? It's Vpp can be adjusted > to meet the requirements (what are they?). You may use a sine wave clock, but that will mean that you will have more jitter than if you use a square wave clock. That has nbothing to do with Spartan 3E (or 3), it is just the fact that a sine wave is provides a vaying time if there is any ground bounce, Vcc bounce, cross talk, etc (which there always is). I would suggest using the largest p-p sine wave you can get, if this is desired, then the transition through the zero crossing will be the fastest. For example, if the differential input is in a 2.5V bank, a 2.5 V sine wave (rail to rail) is best as the LVDS input buffer slices at about 50 mV or less between + and -.Article: 102302
MikeShepherd564@btinternet.com wrote: > It's a good point. My first thought with production in China is "How > do we stop them from copying it?" Perhaps that's a little unfair, > because it's an important question, no matter to whom you transfer a > design. It's one thing to have them actually seek out one of your boards/systems, buy it, and invest the effort to reverse engineer both PCB and programmable entities. It's quite another to send them your design files for the PCB or project and make it easier.Article: 102303
Andreas Ehliar wrote: > H have recently been working on a floating point unit for a Virtex 4 > SX 35. I have a floating point adder and a floating point multiplier. > The adder has 6 pipeline stages and the multiplier has 3 stages. > > The idea behind this project is to find out the kind of floating > point performance that is possible in a modern FPGA. > > Our floating point format uses up to 15 bits of mantissa (with an > implicit one) and up to 10 bits of exponent. We have managed to get > a complex butterfly running at up to 250 MHz. So my question now is > if these numbers are reasonable or if anyone knows of a reference to > a faster fpu. > > > We have already used some tricks to improve performance, for example > by manually instantiating LUTs so that we can build an adder with a > 2 to 1 MUX on one of the operands using only one LUT per bit. > > We have also tried to build up the design using RLOC:ed modules. This > did not lead to improved performance as compared to a non RLOC:ed design. > This could change once we start to fill up the device though. At the > moment we are only utilizing about 20% of the FPGA. > > /Andreas I've got a floating point 4/8/16 point kernel for Virtex4 that meets timing at 400 MHz in the -10 speed grade part (limited by the speed of the DSP48 and BRAM blocks). It has 24 bit mantissas and 8 bit exponents (IEEE single precision floating point). Instances of that kernel are combined obtain three parallel 400 MS/sec single precision 64 to 2048 point floating point FFTs for an aggregate continuous complex data stream of up to 1.2GS/sec. The 3 parallel 64-2k pt FFTs fit into a single V4SX55-10 device, along with QDR-II RAM interfaces. You need to use the adders in the DSP48's in order to reach 400MHz clock rates, the LUT carry chains are too slow. Reaching the 400 MHz performance with the density needed requires considerable hand-optimization as well as a number of algorithmic tricks. You also won't get the density if you start with floating point math operations as your basic building blocks.Article: 102304
Hello everyboby, My name is Giovanny I am working with two types of xtreme dsp Development cards: Kit virtexII ( xc2v3000) and virtex II PRO (xc2vp30) ; I am trying to implement the example "16 QAM demodulator for Software Defined Radio" running sysgenqam16_dplr.mdl file in simulink ;I have been using the tool "system generator" for generating VHDL code , but I have realized that I need add source sysgenqam16_dplr_clk_wrapper.ucf ( I have looked for these files .ucf in the CD xtreme dsp, but I have not found them) and thus to be able to generate sysgenqam16_dplr_clk_wrapper.bit to load it in the card with FUSE tool ;I know that "sysgenqam16_dplr_clk_wrapper.bit" file is on CD,but I would like to make the process "Generate Programming File" for implementing of the project Can Someone help me???, If somebody of you has these files sysgenqam16_dplr_clk_wrapper.ucf for this types xtreme dsp Development cards could send them please to my mail giovanny.fco@gmail.com ??? Thanks a lot GiovannyArticle: 102305
Hi Austin, Thanks for your detailed explanation. I will try the options and try to get comfortable with capability of the device. Srini.Article: 102306
Hi Jim, I am able to see the flops packed into IOBs in FPGA editor. Thanks for your help. Srini.Article: 102307
On Sat, 13 May 2006 06:35:33 -0700, Phil Hays <Spampostmaster@comcast.net> wrote: >Ray Andraka <ray@andraka.com> wrote: > >>Jim Wu wrote: >> >>> Another way to verify this is to open the ncd file in FPGA_EDITOR and >>> see what are put in the IOBs. >>> >>> HTH, >>> Jim >>> http://home.comcast.net/~jimwu88/tools/ >>> >>Or look at the pad report, there is a column there indicating whether >>the signal is registered or not for each pad. That's a good way to check... >Or set static timing constratints on all pins that can only be reached >with IOB FFs... This is my favorite. If timing passes, I know that the FFs that are supposed to be in the IOBs actually are. This has proved to be a very useful check. Bob Perlman Cambrian Design WorksArticle: 102308
Hello, I am going to buy about five Spartan3 XC3S100Es along with config ROMs in the next few days. I may be ordering several hundred more parts in the coming months, but then again I may not be ordering any more. It all depends how successful the prototypes are. I've never dealt with distributors before so the whole concept seems kind of foreign to me. I am not looking for someone to hold my hand in choosing parts or someone to help me build a working design or anything like that, I just want someone to ship me the parts I need. If only Amazon or Newegg sold FPGAs :D Anyway I've checked the Nuhorizons, Digikey and Avnet online inventories. Only Nuhorizons has the XC3S100Es in stock, priced at 9.88 each. Since the price of these parts in big qty. is something like $2, I can't help but feel that the $9.88 price is kind of high. Are there any alternatives to getting the parts I need without paying 400% markup? I'm not so concerned about the extra cost of the prototype parts, but more about the cost of the parts I may buy later. Is it pretty much a reality of the business that the small volume guy gets crapped on?Article: 102309
oh the 9.88 USD price is ok. The marketing price of 2USD is for 1 Million/year for orders shipped 2007 or something alike. For orders of 100 or 1000 dont expect much less than 9USD per piece. In other words the 400% markup in this case is "normal" - do not expect some disti to sell you with 100% e.g. at price of 4USD, its just not possible. AnttiArticle: 102310
forget it AnttiArticle: 102311
Hi, I am using Viretx II as my target FPGA. I use Synplify Pro 8.4 for synthesis and Xilinx ISE 7.1 for PAR. All my input/ouput data are registered. Do I have to specify the IO delays in the constraints editor in Synplify Pro? Even if I have to specify the IO delays, I dont have any idea as to what values should be given. Any thumb rules to start with? Similarly, there is a OFFSET IN/OUT constraint in the Xilinx constrainst editor. Right now I have left it untouched bcoz I dont know what values are normally given for it. In my PAR report, I am seeing the maxilum pin delay to be some 8.6 ns. Has it got something to do with the OFFSET IN or setup time constraint? Can anyone clear my doubts and help in specifying the setup/hold times? Thanks & Regards, Srini.Article: 102312
> I need to build a piece of hardware ( I already wrote most of it in > vhdl and as schematic designs ) that will manipulate a large amount of > data - data that i believe cannot fit on-chip with the design itself. usually you start the other way round ... you first estimate the amount and datarate of memory required, then you design your dataflow and algorithm ... - sram can directly address each memory-location - with sd-ram you should work in bursts and linear in address space, - flash-memory is way slower (on writes), should be used block-wise why taking the trouble of using an FPGA if you do not care about speed?! bye, MichaelArticle: 102313
We are actively doing a mechanical bracket at present and that should be available shortly. Further ahead a 5V tolerant I/O module will be available with a bracket too but that is awaiting the design and build of our next module batch that hasn't been scheduled yet. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Xavier T" <xavier.tastet@gmail.com> wrote in message news:1147626162.560110.261140@j33g2000cwa.googlegroups.com... > Hi All ! > I saw on the web site lots of add-on, but is there "soon available" a > kind of IO rear bracket to fit in the pc slot; to easily access IO from > the rear of the pc ? > Regards, X. >Article: 102314
Be careful of the resistor values. We have used these parts and from my memory the LDO has a different reference voltage and hence resistor ratio to the switcher elements. Your 40mV could be resistor or reference tolerance have you checked those? John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board. http://www.enterpoint.co.uk "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in message news:e3v0va$brk$1@dux.dundee.ac.uk... > Dear all, > > I hope this isn't OT but I was wondering if anyone has any experience > using the TPS75003 to power a Spartan 3? For my particular application > I'm having to swap round the output voltages produced by one of the buck > convertors and the LDO with respect to most of the app notes. The > potential dividers which give the reference feedback in the app notes come > out to give a voltage which is consistently about 40mV above spec for all > three outputs. I was wondering if anyone knew why? Or is it just a bit > of design headroom? > > TIA > > -- PeterArticle: 102315
Is there information available about projects using FPGAs/CPLDs successfully in safety critical application (e.g. automotive, railway, industry)? I am exspecially interested in certification, e.g. IEC61508 (SIL2) or RTCA DO-178B. Any special problems in comparison to microcontrollers? Do I need certified development tools? Thanks for your help FalkArticle: 102316
I'll second that tolerance concern. I was surprised to find that the
core voltage on some parts ('C5510 DSP) has a tolerance as low as +-50
mV making it about 3%. With two resistors and the innate tolerance of
the part, that can be a tough spec to meet.
But I think the OP is saying the values selected provide a voltage 40
mV too high. I would suggest that you contact Xilinx support about
this. They put a lot of things in app notes that may or may not be
best for your design. Don't be afraid to change things, but it
wouldn't hurt to contact them to ask why they picked what they picked.
Or are you talking about the TI app notes? Actually I don't see how
you can say all three outputs are 40 mV too high when the 1.2 volt
output does not use external resistors! The values in the TI data
sheet (figure 1) produce about 2.54 volts, 3.29 volts and of course,
1.2 volts.
John Adair wrote:
> Be careful of the resistor values. We have used these parts and from my
> memory the LDO has a different reference voltage and hence resistor ratio to
> the switcher elements. Your 40mV could be resistor or reference tolerance
> have you checked those?
>
> John Adair
> Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board.
> http://www.enterpoint.co.uk
>
> "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in
> message news:e3v0va$brk$1@dux.dundee.ac.uk...
> > Dear all,
> >
> > I hope this isn't OT but I was wondering if anyone has any experience
> > using the TPS75003 to power a Spartan 3? For my particular application
> > I'm having to swap round the output voltages produced by one of the buck
> > convertors and the LDO with respect to most of the app notes. The
> > potential dividers which give the reference feedback in the app notes come
> > out to give a voltage which is consistently about 40mV above spec for all
> > three outputs. I was wondering if anyone knew why? Or is it just a bit
> > of design headroom?
> >
> > TIA
> >
> > -- Peter
Article: 102317
variable: store information in a memory cell
signal: "wire" to send information to other modules
if the information in signal is needed later on, a latch is
put in the signal line
"YiQi" <yiqihuang@gmail.com> schrieb im Newsbeitrag
news:1147501971.218294.309200@g10g2000cwb.googlegroups.com...
> thx, Jim,
> Sorry, the examples are miss leading. My main concern is the different
> during design flow.
> Let me restate my question, During HDL synthesis, that's the difference
> between them?
> Will that make any different after synthesis(place & route)?
>
Article: 102318John, Thanks for your response. It think I have the resistor values correct, I've attempted to follow the app notes to the letter, anyway. Resistor and Vref tolerances is a good idea, I should have checked that before I posted. Having looked at them, it could possibly be the source of the 40mV. If it were required that near the lowest error tolerance bound the Vref was still not below the required value, this would seem make some sense. The only niggle is that the error bounds are relative (resistor/Vref), and this 40mV over-voltage doesn't change all that much from the 1.2V to the 3.3V supplies. The app notes don't seem to provide an explanation for this. I have come up with two plans, one for a voltage close to spec, another for 40mV (approx) over. Unless I hear any different, I'll probably prototype with the former, and only use the latter if things go belly-up. From your experience, do you have any other advice about using these devices? Thanks, -- Peter John Adair wrote: > Be careful of the resistor values. We have used these parts and from my > memory the LDO has a different reference voltage and hence resistor ratio to > the switcher elements. Your 40mV could be resistor or reference tolerance > have you checked those? > > John Adair > Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board. > http://www.enterpoint.co.uk > > "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> wrote in >> I hope this isn't OT but I was wondering if anyone has any experience >> using the TPS75003 to power a Spartan 3? For my particular application >> I'm having to swap round the output voltages produced by one of the buck >> convertors and the LDO with respect to most of the app notes. The >> potential dividers which give the reference feedback in the app notes come >> out to give a voltage which is consistently about 40mV above spec for all >> three outputs. I was wondering if anyone knew why? Or is it just a bit >> of design headroom?Article: 102319
You can assign MGT pins in ADEPT. Here is the web site: http://home.comcast.net/~jimwu88/tools/adept/ HTH, JimArticle: 102320
Falk Salewski schrieb: > variable: store information in a memory cell > signal: "wire" to send information to other modules > if the information in signal is needed later on, a latch is > put in the signal line I doubt it. There are plenty of signals in every HDL design without any latch. As someone pointed out before, it's a complicated story (and so answer) of HDL principles. Regards FalkArticle: 102321
Falk I have done three SIL4 fpga development on my last contract, we did not use certified tools as I am not aware there are any however we used very stringent RTL design guidelines, independantly developed test benches for each module which must achieve 100 % in code coverage for path, branch, statement, toggle, and condition at all levels. along with independant reviews of rtl code and module specifications / test specifications. Further more we used two synthesis tools targeting different technologies i.e. xilinx and actel and then used formal equivelence checking to ensure that the RTL against the implementation actel devices (the devices used were actel) were the same with no mismatches and then compared the xilinx against actel top ensure the synthesis tools had not filled any holes with logic. There are a few guidelines for coding RTL style to ensure all possible failure conditions are detecteable, I would be happy to advise you further if you would like to know more ? I think i have some documents I wrote on saftey critcal fpga design somewhere. What is your intended application ? hope this helps AdamArticle: 102322
Is your voltmeter calibrated? Aurash Peter Mendham wrote: > John, > > Thanks for your response. It think I have the resistor values correct, > I've attempted to follow the app notes to the letter, anyway. Resistor > and Vref tolerances is a good idea, I should have checked that before I > posted. Having looked at them, it could possibly be the source of the > 40mV. If it were required that near the lowest error tolerance bound > the Vref was still not below the required value, this would seem make > some sense. The only niggle is that the error bounds are relative > (resistor/Vref), and this 40mV over-voltage doesn't change all that much > from the 1.2V to the 3.3V supplies. The app notes don't seem to provide > an explanation for this. > > I have come up with two plans, one for a voltage close to spec, another > for 40mV (approx) over. Unless I hear any different, I'll probably > prototype with the former, and only use the latter if things go belly-up. > > From your experience, do you have any other advice about using these > devices? > > Thanks, > > -- Peter > > John Adair wrote: > >> Be careful of the resistor values. We have used these parts and from >> my memory the LDO has a different reference voltage and hence resistor >> ratio to the switcher elements. Your 40mV could be resistor or >> reference tolerance have you checked those? >> >> John Adair >> Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development >> Board. >> http://www.enterpoint.co.uk >> >> "Peter Mendham" <petermendham@NOCANNEDMEAT.computing.dundee.ac.uk> >> wrote in >> >>> I hope this isn't OT but I was wondering if anyone has any experience >>> using the TPS75003 to power a Spartan 3? For my particular >>> application I'm having to swap round the output voltages produced by >>> one of the buck convertors and the LDO with respect to most of the >>> app notes. The potential dividers which give the reference feedback >>> in the app notes come out to give a voltage which is consistently >>> about 40mV above spec for all three outputs. I was wondering if >>> anyone knew why? Or is it just a bit of design headroom? > >Article: 102323
http://ai.unime.it/~gp/publications/full/tccrc.pdf This paper describes the algorithm for parallel implementation of CRC. I was able to use the same concept for implementing parallel scrambler. The matlab code in the paper is very helpful for understanding the algorithm. Sovan.Article: 102324
Thanks both Falk, In a FPGA, does a latch and a memory cell make any different? Isn't it the same ?
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