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Austin, thanks for the info. So 0.2V being > the treshold voltage is not surprising at 90nm. I had no idea where the breakthrough voltage would be, your mentioning the 3.9V makes me think it is about 5V. Not so bad, come to think we are used to reverse base emitter voltage around 6-7V (and about 3 for some really hf parts) for decades.. :-). > Without all these bells and whistles that now make up a modern FPGA > offering, they are basically back in the XC2064 era: basic fabric, some > IO, and no tools. On a side note, what did Xilinx do back then? I doubt they have made the specification of the insides public so other people could write their tools (I keep on dreaming abou that day....), what was it? > One other point: their design is about 16X more area (less density) > than a modern FPGA. That is going to be a real killer - <100K gates for > ~$10? When the market is at 1M+ gates for <$10? Well they appear to be targetting some (most likely speed) specs which are much better than the rest and hope to get into busyness based on that. If their specs are just, say, 1.something better, it will take more than that to stay alive - but if they are well connected they might well get some big contract to give them the starting kick. Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ Austin Lesea wrote: > dp, > > Even Intel has realized that frequency kills. Not sure why they are so > excited about touting 2 GHz. > > The fets are running in "active mode" basically just behaving as analog > (low gain) transistor amplifiers in their sub threshold regions...kinda > on, kinda off, kinda inbetween. > > I am sure that the speed of operation is very slow down at 0.2V. > > At 3.9 volts on a 90nm transistor, I am guessing the lifetime to > breakdown is about a week, or sooner. > > I'd like to see them get block RAM, processors, DLL's/PLL's, MGTs, etc. > to work in the same fashion. I am sure we all know the stories of the > attempts at making async microprocessors, and how they were abandoned > for having far too much area, and no real performance benefits. > > And when async logic is running as fast as it can, it is going to have 2 > to 3 times the power dissipated, as that is how many more wires and > transistors are switching. Asnyc when doing nothing is very low power. > I just love systems that do nothing: they end up going away (why does > anyone care what a system does when it has nothing to do? Just turn it > off!). > > Their press announcement did say that now that they have the core > working, they need to get their (hardened?) IP to work, next. > > Without all these bells and whistles that now make up a modern FPGA > offering, they are basically back in the XC2064 era: basic fabric, some > IO, and no tools. > > One other point: their design is about 16X more area (less density) > than a modern FPGA. That is going to be a real killer - <100K gates for > ~$10? When the market is at 1M+ gates for <$10? > > Good luck. > > Async design is a religion, and you either believe it will save you, or > you don't. I'm just a sceptic. I am still waiting to see it do > something useful in the marketplace. > > More interesting (I think) is the (synchronous) FPOA, with its enforced > pipelining, and medium grain architecture aimed at extreme DSP > applications. At least that product looks like one can actually use it, > and it does something. Although 30W power dissipation is just about > twice what most folks can deal with. > > Austin > > dp wrote: > > >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply > >>range. 0.2V is not much voltage at all... I would have thought > >>transistor threshold voltages would have caused issues at such a low > >>voltage. How are they achieving such low threshold voltages? > > > > > > Sounds interesting to me as well, perhaps some of the other 90nm > > manufacturers could shed some light - does it really work? Probably > > not at full speed, but even at DC - do the FETs really turn on at 0.2 > > V? > > While I am not sure what this synchronous/asynchronous gimmick is > > all about I would say I am glad they may soon have a marketable > > alternative to the rest of the makers, I guess they all became a bit > > too big to talk to (and stay innovative). > > > > Dimiter > > > > ------------------------------------------------------ > > Dimiter Popoff Transgalactic Instruments > > > > http://www.tgi-sci.com > > ------------------------------------------------------ > > > > > > Bevan Weiss wrote: > > > >>Jim Granville wrote: > >> > >>>For those interested in Async devices, and uses : > >>> > >>>http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 > >>> > >>> > >>>It is a way's off being usable, but the numbers are impressive :) > >>> > >>> No mention of device size, but the info suggests they target the > >>>high-price/low volume user space. > >>> [ Not too many customers need -196'C :) ] > >>> > >>>.. and no mention of design tools, which may prove to be a bigger > >>>challenge than the silicon. > >>> > >>>-jg > >> > >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply > >>range. 0.2V is not much voltage at all... I would have thought > >>transistor threshold voltages would have caused issues at such a low > >>voltage. How are they achieving such low threshold voltages? > >> > >> > >>Bevan > > > >Article: 101151
On Wed, 26 Apr 2006 16:24:21 +1200, Jim Granville <no.spam@designtools.co.nz> wrote: >stuff on new asynch. FPGA announcement skipped > >.. and no mention of design tools, which may prove to be a bigger >challenge than the silicon. Truer words were never spoken. Bob Perlman Cambrian Design WorksArticle: 101152
<pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote in message news:444fb007$0$490$cc7c7865@news.luth.se... > >They'd potentially have another market if the increased the operating >>temperature well beyond 130'C - downhole applications in the oil industry, >>for instance. > > How hot are those ..? >From one of Peter Alfke's posts here (May 15th, 2003): "Silicon is one tough material ! The 125 or even 150 degree limit is more a plastic package issue than a silicon issue. I have helped down-hole (oil-drilling) applications where our chips functioned (with relaxed performance) for many weeks at 175 degree ambient, and the user was pushing for 200 degrees."Article: 101153
Austin Lesea wrote: > I am sure we all know the stories of the > attempts at making async microprocessors, and how they were abandoned > for having far too much area, and no real performance benefits. The jury is still out on that one, as we noted a couple months back with the ARM. > And when async logic is running as fast as it can, it is going to have 2 > to 3 times the power dissipated, as that is how many more wires and > transistors are switching. Actually, when you count the clock in a sync design based on lut/ff it works out about the same, especially when you include the clock distribution network. > Asnyc when doing nothing is very low power. > I just love systems that do nothing: they end up going away (why does > anyone care what a system does when it has nothing to do? Just turn it > off!). I don't see that being any different that having to leave half an FPGA idle when you need to turn up the frequency on your FPGA's because of heat/power limits. > One other point: their design is about 16X more area (less density) > than a modern FPGA. That is going to be a real killer - <100K gates for > ~$10? When the market is at 1M+ gates for <$10? Seems that you have said a number of times that the wasted area in an FPGA as compared to ASIC wasn't a problem???? > Async design is a religion, and you either believe it will save you, or > you don't. hardly. More like it solves your problems or not. > Although 30W power dissipation is just about > twice what most folks can deal with. Yep ... even with your parts.Article: 101154
dp wrote: >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply >>range. 0.2V is not much voltage at all... I would have thought >>transistor threshold voltages would have caused issues at such a low >>voltage. How are they achieving such low threshold voltages? > > > Sounds interesting to me as well, perhaps some of the other 90nm > manufacturers could shed some light - does it really work? Probably > not at full speed, but even at DC - do the FETs really turn on at 0.2 > V? Note they were carefull in the wording : "operated correctly". I would place 0.2V at a data-retention point, not a clocking one. CMOS nodes will 'stay-put' at much lower voltages than they will toggle, and there is a clear need for a spec point that allows instant-config from the lowest possible Icc. Xilinx have been playing a little with this, but so far are a long way off 0.2V -jgArticle: 101155
dp, Some comments, Austin -snip- > thanks for the info. So 0.2V being > the treshold voltage is not > surprising at 90nm. I had no idea where the breakthrough voltage would > be The Vt is defined as the voltage at which the Idsat is X. The transistor has a subthreshold region where some voltage causes some current to flow, well down to the millivolts. It isn't digital at all. It is all analog design... , your mentioning the 3.9V makes me think it is about 5V. Not so > bad, come to think we are used to reverse base emitter voltage around > 6-7V (and about 3 for some really hf parts) for decades.. :-). You would blow the 90nm gate to smithereens in a blink at 6 volts. -snip- > On a side note, what did Xilinx do back then? I doubt they have made > the specification of the insides public so other people could write > their > tools (I keep on dreaming abou that day....), what was it? No, we made our own crude (really) tools, and folks made use of them, and folks started to ask us for better ones, and slowly we figured out how, and provided better and better tools. No one was interested in making tools for some unknown and unheard of company that was "wasting" transistors. Back then, we were vilified by the semi industry as being quacks, and con artists (almost). Real semi companies owned their own fab, and carved their own masks on rubylith with Xacto knives.Article: 101156
fpga_toys, Only comment is that the async FPGA is 16X our area. Not 16X the area of an asic designed to do the same job. AustinArticle: 101157
Austin Lesea wrote: > dp, > > One other point: their design is about 16X more area (less density) > than a modern FPGA. That number comes from where ? > That is going to be a real killer - <100K gates for > ~$10? When the market is at 1M+ gates for <$10? Let's stand back a little, and consider markets : Pure Logic is still a > $2B business, and the ECL/LVDS sides of that are not going away, but are increasing. Sometimes pure MHz really does matter, and price is secondary. Will this replace the vanilla FPGAs = no. Could one of these sit alongside a vanilla FPGA ( just like ECL and LVDS blocks do right now ) = yes. Taking an even wider perspective, it pays to remember the ASIC market is still much higher $$$ than FPGAs - in dollar terms, FPGAs are a fringe business, and in pure performance, they also struggle. - but that still leaves enough customers to support a $2-3B FPGA sector > Good luck. I think there is plenty of room for them. Xilinx might even buy them out, in 2007.... -jgArticle: 101158
Jim Granville wrote: > I think there is plenty of room for them. > Xilinx might even buy them out, in 2007.... Or maybe Altera will and port C2H to it :)Article: 101159
Eric Smith <eric@brouhaha.com> wrote: > Dan McDonald wrote about using ISE on Linux: > > You will be able to do everything up to generating the programming > > file. The drivers, however, are 32-bit only - so you can't actually > > program it when running a 32-bit kernel. > Dan obviously meant that you can't program devices when running a > 64-bit kernel, since the drivers are 32-bit. > Xilinx, *please* give us 64-bit cable drivers in the next service > pack, or at least the next release (8.2i?)! An easy way to achieve that would be to drop WinDriver and use the standard drivers like /dev/parport or USB access by a dedicated driver or by direct endpoint access via /proc/bus/usb -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 101160
jg, Who knows? The estimates come from earlier papers that were published by this group when they were students and professors before they found funding. Who knows? They don't have anything but slick press releases right now. Plenty of room for specialty stuff in the market. Just have to pick the right stuff. Is the extreme DSP market 2B$? 5B$ Or is it 500M$? Who is going after it? All part of the game. Is it like the structured ASIC market? All hot air, and no money (with folks leaving so fast)? How does the cost of the next process ASIC affect their business model? Can they hope to layout in 65nm and release that in 2008 when we are at full production with 65nm -- 65nm will be the 'old' product then? We will beat them on processing power by just being ahead a node or two. Got to think about that business model: they can use up all that seed money pretty fast fixing masks....only to face a 35nm FPGA that is 1/8 the cost and area, and 4X the performance? And their claims of space, radiation, etc. means they have to use epitaxial wafers (not bulk CMOS), and they have to be heavy ion immune to latchup, SEL, SEU, SER, etc....that is a much tougher thing to prove! Our QPRO line is already in space, and does work. Has a history of success. Space folks are real hard to convince to do anything new (believe me, I have tried). No one wants their mission to be the one that is used as the "case study of a disaster." AustinArticle: 101161
If I worked for a company that has nothing available to sell, I would really be embarrased if somebody forced me to brag about multi-million gates and 1.93 GHz in one paragraph, and minus 196 degree operation, and 0.2 V to 3.9 V supply voltage in the next. But normally super-critical people that enjoy nailing us for the slightest oversight, just drool... The date was April 24, maybe it was just 23 days delayed... Peter Alfke, speaking for himselfArticle: 101162
Austin Lesea wrote: > Only comment is that the async FPGA is 16X our area. Not 16X the area > of an asic designed to do the same job. No question. The point is that is their first silicon cut, will likely get smaller over time, and that as you have clearly said in the past that die size isn't everything, but rather it's the cost/performance of the finished product. So your argument why the bloated size of an FPGA in comparision to ASIC equally applies to other products as well -- it's the end customer, not their competitors, that decides if the product has reasonable cost/performance to design their products with.Article: 101163
Peter Alfke wrote: > If I worked for a company that has nothing available to sell, I would > really be embarrased if somebody forced me to brag about multi-million > gates and 1.93 GHz in one paragraph, and minus 196 degree operation, > and 0.2 V to 3.9 V supply voltage in the next. Is that how Xilinx enginering and sales feels when they are out pumping interest in next generation product (before finished production parts are available) with select customers looking for advanced design wins?Article: 101164
Roger Bourne wrote: > Hello all, > > I am attempting to expand the 18x18 multipliers as provided in the > xilinx Spartan 3 series. > I followed the proposed implemention of expanding the multipliers as > described in the xapp467.pdf app note (figure 5). However, I arrived at > an impasse: > When the operand is splitted up in 2 or more partial operands of 18 > bits, the sign-extension of the operand does not carry over -I'll > expalin: > E.g Lets say we want to multiply (-1)in18bitsx(1)in 22bits.The 22 bit > operand is splitted in 2 4-bit(lsb) and 18-bit(msb) operands. Thus, > when we multiply the lsb part: 3FFFFh(=-1)x1h=3FFFFFh(=-1), we obtain a > non-nil answer. However, when we multiply the msb part: > 3FFFFh(=-1)x00000h=000000000h, we obtain a nil answer. When the 2 > partial products are added and the bits properly weighed as to > constructed the final product, the msb bit(sign bit) will be 0. > Consequently, resulting in a positive product when a negative one was > expected (-1 was expected, FFFFFFFFFFh.) > > I feel I must be doing something wrong.. > Please advise > -Roger > The lower parts of the inputs have to be treated as unsigned, and you need to form partial products of all the peices: A = AH*2^n + AL B = BH*2^m + BL A*B = AH*BH*2^(m+n) + AH*BL*2^n + AL*BH*2^m + AL*BL AL and BL are unsigned, AH and BH are signed if A and B are signed. In your case, I guess you have only one of the operands split so: A*B = AH*B*2^n + AL*B, AL is unsigned, AH and B are signed. Your example has AH=0, AL=1, n=4, B=-1 A*B = 0 + -1 = -1. Keep in mind your partial products require sign extension to the full width of the full product in order to add them together.Article: 101165
At least Analog Devices and also Fairchild propose analog switches as level translators to interface eg 1.8V logic to 3.3V logic. I fail to recognize how this is going to work. The Low state is understood, it is just pulled down, but how is a 1.8V output high propagated to a 3.3V high by just a resistor ? Apart from the analog switches, what alternative are there to interface an 1.8V FPGA to normal 3.3V or 5V logic ? Yes, switchable bidirectional, or auto bidirectional is preferred. Else what unidirectional solutions are there ? ReneArticle: 101166
Peter Alfke wrote: > If I worked for a company that has nothing available to sell, I would > really be embarrased if somebody forced me to brag about multi-million > gates and 1.93 GHz in one paragraph, and minus 196 degree operation, > and 0.2 V to 3.9 V supply voltage in the next. fpga_toys@yahoo.com writes: > Is that how Xilinx enginering and sales feels when they are out pumping > interest in next generation product (before finished production parts > are available) with select customers looking for advanced design wins? It's how any reasonable engineer feels looking at those ridiculous claims. Don't tell me you believe them?Article: 101167
Austin, some more from me, > The Vt is defined as the voltage at which the Idsat is X. ... I was referring to the voltage below which the channel is off, i.e. the cutoff voltage, so we are talking about the same thing. I have extensive experience using FETs in analog designs (mostly JFETs, of course), but I may well have forgotten which letter goes for which parameter. Of course I know you won't open a FET down to its lowest achievable Rdson at 2GHz (I believe this is what you refer to as "saturation"). > You would blow the 90nm gate to smithereens in a blink at 6 volts. Yep, apparently so, what I noted to myself was that they could survive (sometimes perhaps not) a short term 3.3V glitch (not that I would like to do it but with all these multiple supply voltages nowadays one just cannot avoid the thought... :-). > No one was interested in making tools for some unknown and unheard of > company that was "wasting" transistors. Back then, we were vilified by > the semi industry as being quacks, and con artists (almost). This must have been in the pre-LCA time, back in 1990 or so I asked about the programming specs of the LCA and was denied it. I did appreciate the devices then, I still do now, my only problem is that all my design tools are under my control (this gives a world of a difference so many times). Well, the truth is, I have never gone hard enough after the FPGA data, so I don't really know how difficult to achieve this goal is. Some time ago I got some valuable help from Peter on other devices I use, I imagine if I really need something and (as it happens to be) I am not in anyone's way things could be sorted out... Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ Austin Lesea wrote: > dp, > > Some comments, > > Austin > > -snip- > > > thanks for the info. So 0.2V being > the treshold voltage is not > > surprising at 90nm. I had no idea where the breakthrough voltage would > > be > > The Vt is defined as the voltage at which the Idsat is X. The > transistor has a subthreshold region where some voltage causes some > current to flow, well down to the millivolts. It isn't digital at all. > It is all analog design... > > , your mentioning the 3.9V makes me think it is about 5V. Not so > > bad, come to think we are used to reverse base emitter voltage around > > 6-7V (and about 3 for some really hf parts) for decades.. :-). > > You would blow the 90nm gate to smithereens in a blink at 6 volts. > > -snip- > > On a side note, what did Xilinx do back then? I doubt they have made > > the specification of the insides public so other people could write > > their > > tools (I keep on dreaming abou that day....), what was it? > > No, we made our own crude (really) tools, and folks made use of them, > and folks started to ask us for better ones, and slowly we figured out > how, and provided better and better tools. > > No one was interested in making tools for some unknown and unheard of > company that was "wasting" transistors. Back then, we were vilified by > the semi industry as being quacks, and con artists (almost). > > Real semi companies owned their own fab, and carved their own masks on > rubylith with Xacto knives.Article: 101168
Austin Lesea wrote: > jg, > > Who knows? > > The estimates come from earlier papers that were published by this group > when they were students and professors before they found funding. > > Who knows? They don't have anything but slick press releases right now. Having spent most the 1980's and 1990's working with early startups, there is another factor that you seem to miss. Startups are frequently captive design/production facilities to larger companies that need that product, and greatly influence the intial product design by stating what they want to buy. When a large early customer says "I need x, y, and z delivered in 100K qty" between two dates, that becomes your product, business plan, and production schedule.Article: 101169
Eric Smith wrote: > It's how any reasonable engineer feels looking at those ridiculous > claims. Don't tell me you believe them? It's not a mater of belief, they will either deliver or not. In 35 years of engineering I've done my share of products that people said can not be done, and delivered to their disbelief. We have modems today that broke the modulation "laws" set in 60's ... by more than an order of magnitude. We have semi design rules today, that exceeded a large number of "walls" in process over the last 30 years too. There are many more examples of what can not be done, that have be easily broken by innovative engineers. So, I'm not in a big hurry to claim what can not be done ... I'll wait and see what is delivered, rather than ranting about what is impossble.Article: 101170
Thanks for the reply, The code does actulaly synthesis (withouth the typo). However, is it possible that the data on word_stream_out could not be the same as the data on word_stream in, with this current implementation? If I seperate it into two processes (one on the rising edge and another on the falling edge) and with a temp_word signal between them, will this give me the functionality that I require? SimonArticle: 101171
On Wed, 26 Apr 2006 11:08:19 -0700, Stephen Williams <spamtrap@icarus.com> wrote: > >Francesco wrote: >> Hi all, >> On www.poderico.co.uk you can download the free C compiler for >> Picoblaze version 1.7.7 >> In the next 2 months the optimizer should be ready and the code >> generated will be shorter. >> I' wish to design the debugger too. >> Any help and suggestions is welcome. > > >Binary only? >Windows only? There's no pleasing some people....Article: 101172
Eric Smith wrote: > Peter Alfke wrote: > >>If I worked for a company that has nothing available to sell, I would >>really be embarrased if somebody forced me to brag about multi-million >>gates and 1.93 GHz in one paragraph, and minus 196 degree operation, >>and 0.2 V to 3.9 V supply voltage in the next. > > > fpga_toys@yahoo.com writes: > >>Is that how Xilinx enginering and sales feels when they are out pumping >>interest in next generation product (before finished production parts >>are available) with select customers looking for advanced design wins? > > > It's how any reasonable engineer feels looking at those ridiculous > claims. Don't tell me you believe them? I find them plausible - what is hard to believe ? They do not mean they run at 2GHz _and_ @ 0.2V :) "operated correctly" is their carefull wording. To me, correct (expected) operation at 0.2V is data retention. Target Vcc sounds ~1.2V : "is capable of running common FPGA performance benchmark designs at up to 1.93 GHZ at 1.2V" -- not sure what they were testing at 3.9V, - might have meant the IO buffers, and probably not the Core Vcc! Also, I take these as Lab-bench-test values, so production margins are not yet added. These are the sort of numbers you try to keep from marketing, in case they get promised/morphed into performance minimums :) -jgArticle: 101173
On Wed, 26 Apr 2006 16:24:21 +1200, Jim Granville wrote: > For those interested in Async devices, and uses : > > http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 > > It is a way's off being usable, but the numbers are impressive :) > > No mention of device size, but the info suggests they target the > high-price/low volume user space. > [ Not too many customers need -196'C :) ] > > .. and no mention of design tools, which may prove to be a bigger > challenge than the silicon. > > -jg It sounds very suspicious. A serious startup usually doesn't make public announcements at this stage of the game, they'll show what they have to a few interested parties under NDA. Also there are just to many claims, .2 - 3.9V operation on a 90nm process? You never know it could be real, but I'd wait until they show something publicly before I got excited about this.Article: 101174
Josh Rosen wrote: > You never know it could be real, but I'd wait until they show something > publicly before I got excited about this. Or take a real project to them that just isn't possible on other products, and see what's behind the NDA?
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