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>><snip> >> constant SNAP_FLAGS_RESET : SNAPTYPE_INTERNAL_FLAGS := >> ((zero => '0', negative => '0', carryBorrow => '0', overflow => '0'), >> equalityTests => b"000", globalInterruptEn => '0'); > > > Have you tried using named association for that first parameter? i.e. > > constant SNAP_FLAGS_RESET : SNAPTYPE_INTERNAL_FLAGS := > (aluFlags => (zero => '0', negative => '0', carryBorrow => '0', overflow > => '0'), > equalityTests => b"000", globalInterruptEn => '0'); Ben, That did the trick. Also, if anything, that approach is a little clearer/meaningful too. Thanks for the pointer. Shame XST failed horribly though, rather than produced a more meaningful error. Cheers Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 101126
Uwe Bonnes wrote: > Jim Granville <no.spam@designtools.co.nz> wrote: > >>For those interested in Async devices, and uses : > > >>http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 > > >>It is a way's off being usable, but the numbers are impressive :) > > >> No mention of device size, but the info suggests they target the >>high-price/low volume user space. >> [ Not too many customers need -196'C :) ] > > > Jim, the press release tells about testing from -196C to +130C not only at > -196 C... I realise that, of course, - the comment still stands : Do you have an app that needs to go to -196'C ? Mars is the only deployment I can think of, most others are covered by the terrestrial Military -55'C - 125'C range. -jgArticle: 101127
Hi Andrew,
"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message
news:e2nc15$rvj$1@pump1.york.ac.uk...
> >><snip>
> > Have you tried using named association for that first parameter? i.e.
> That did the trick. Also, if anything, that approach is a little
> clearer/meaningful too. Thanks for the pointer.
> Shame XST failed horribly though, rather than produced a more meaningful
> error.
Indeed. I've hit several record/aggregate-related snags like this before and
spent ages trying to pinpoint exactly what bit of (legal) syntax XST was
complaining about, because they always seem to fail with a "fatal error" (or
else work fine)
FYI, I ran your snippet through a slighty behind-the-curve 8.1i build of XST
and it worked fine for me.
Cheers,
-Ben-
Article: 101128> I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, > my cpld some times work and sometimes does not work at that frequency. > If I lower the clcok frequency to 12MHz then it always work. bu tin > both cases the chip does get hot. I put a heat sink on the chip but if > the chip works for long hours then it effects its functionality. Can > anybody advice me how to slove this problem? > > John > I doubt that the problem has anything to do with 'heat' unless this is a very unusual environment that you're in. That's just a symptom that you're observing. It's most likely a timing problem. Some things to look for... - Asynchronous input not being handled properly. - Setup times are being violated. - Is the clock frequency computed by the tool used to fit your design telling you that it will run at the speeds you're running it at? The actual timing of a device at a given moment is a function of device temperature. Further, device temperature is a function of clock speed as well. Another occasional problem is if you're driving a lot of load from this device (either lots of outputs switching simultaneously or just a few that are heavily loaded sometimes). But I'd check into the timing first since that's almost always where the problem is KJArticle: 101129
I have never done an FPGA design and I am considering purchasing the
Starter Board. It has crossed my mind to implement at least part of a
design I did in an ASIC many years ago. The largest part of the ASIC
design was a "funnel" shifter. Basically the shifter operated as a barrel
shifter on the 96-bit input and output the 21-bits beginning at any
designated position. Cycle time was one clock.
Is this doable with the XC3500 on the Starter Board? How much of the
logic would this consume? Any thoughts on what the max clock rate would
be?
Thanks!
~Dave~
Article: 101130Jim Granville wrote: > For those interested in Async devices, and uses : > > http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 > > > It is a way's off being usable, but the numbers are impressive :) > > No mention of device size, but the info suggests they target the > high-price/low volume user space. > [ Not too many customers need -196'C :) ] > > .. and no mention of design tools, which may prove to be a bigger > challenge than the silicon. > > -jg I'm amazed they have achieved this operation over the 0.2V - 3.9V supply range. 0.2V is not much voltage at all... I would have thought transistor threshold voltages would have caused issues at such a low voltage. How are they achieving such low threshold voltages? BevanArticle: 101131
> I'm amazed they have achieved this operation over the 0.2V - 3.9V supply > range. 0.2V is not much voltage at all... I would have thought > transistor threshold voltages would have caused issues at such a low > voltage. How are they achieving such low threshold voltages? Sounds interesting to me as well, perhaps some of the other 90nm manufacturers could shed some light - does it really work? Probably not at full speed, but even at DC - do the FETs really turn on at 0.2 V? While I am not sure what this synchronous/asynchronous gimmick is all about I would say I am glad they may soon have a marketable alternative to the rest of the makers, I guess they all became a bit too big to talk to (and stay innovative). Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ Bevan Weiss wrote: > Jim Granville wrote: > > For those interested in Async devices, and uses : > > > > http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 > > > > > > It is a way's off being usable, but the numbers are impressive :) > > > > No mention of device size, but the info suggests they target the > > high-price/low volume user space. > > [ Not too many customers need -196'C :) ] > > > > .. and no mention of design tools, which may prove to be a bigger > > challenge than the silicon. > > > > -jg > > I'm amazed they have achieved this operation over the 0.2V - 3.9V supply > range. 0.2V is not much voltage at all... I would have thought > transistor threshold voltages would have caused issues at such a low > voltage. How are they achieving such low threshold voltages? > > > BevanArticle: 101132
Jim Granville schrieb: >> a) I still wonder if 15ns is a reasonable worst-case delay for a direct >> input to output connection (or for an input->not gate->output >> connection) for this kind of device. I have been trying to figure out >> which combination of t_xyzk?#? from the datasheet I should be adding in >> this case (have to say, without success) For what load are these delays specified? (Datasheet) What drive strength are you using? (Constraints File) Do the math: Driving a 50pF standard PCI load with a 2mA driver from 0 to 1.6V will take 40ns without any internal delay. Most FPGAs have programmable output drive strengths and logic families. Try changing your output to LVDS or GTL and see what delays you get. >> b) It is surprising that the simulator tells that the direct connection >> exhibits greater delay than the inverted one. Perhaps this depends on >> which particular output pin is driven? > > > That sounds like a bug - if you have checked that's what the design > tools actually created. Not at all. Because NMOS transistors are faster than PMOS transistors the fastest overall speed for a CMOS device is achieved if the falling transition of each gate is made faster than the rising transition. http://www-md.e-technik.uni-rostock.de/lehre/vlsi_ii/Harris/LogicalEffort.pdf (Page 2/11) This probably is the case for your output buffers. Try out what delays you get when simulating the opposite transition. Also, for higher loads, circuits actual can get faster by adding gates to the path. http://bwrc.eecs.berkeley.edu/Classes/IcDesign/EE141_s02/Lectures/Lecture7-invsize.PDF Kolja SulimmaArticle: 101133
Hi! We are are planning a project were we want to use 8 MGT receivers at 10Gbps on an FX20. The layout for the power supply filtering is rather demanding so I am wondering if it could be simplified when not using the transmitters. I suppose that I can use VTTXA unfiltered or even leave it unconnected when setting floating 100R termination for the transmitters? Is this also true for VTRX when using that termination style? Can I also leve AVCCAUXTX unfiltered? Also: What is the current roadmap for delivering 10gps silicon? Kolja SulimmaArticle: 101134
dp, Even Intel has realized that frequency kills. Not sure why they are so excited about touting 2 GHz. The fets are running in "active mode" basically just behaving as analog (low gain) transistor amplifiers in their sub threshold regions...kinda on, kinda off, kinda inbetween. I am sure that the speed of operation is very slow down at 0.2V. At 3.9 volts on a 90nm transistor, I am guessing the lifetime to breakdown is about a week, or sooner. I'd like to see them get block RAM, processors, DLL's/PLL's, MGTs, etc. to work in the same fashion. I am sure we all know the stories of the attempts at making async microprocessors, and how they were abandoned for having far too much area, and no real performance benefits. And when async logic is running as fast as it can, it is going to have 2 to 3 times the power dissipated, as that is how many more wires and transistors are switching. Asnyc when doing nothing is very low power. I just love systems that do nothing: they end up going away (why does anyone care what a system does when it has nothing to do? Just turn it off!). Their press announcement did say that now that they have the core working, they need to get their (hardened?) IP to work, next. Without all these bells and whistles that now make up a modern FPGA offering, they are basically back in the XC2064 era: basic fabric, some IO, and no tools. One other point: their design is about 16X more area (less density) than a modern FPGA. That is going to be a real killer - <100K gates for ~$10? When the market is at 1M+ gates for <$10? Good luck. Async design is a religion, and you either believe it will save you, or you don't. I'm just a sceptic. I am still waiting to see it do something useful in the marketplace. More interesting (I think) is the (synchronous) FPOA, with its enforced pipelining, and medium grain architecture aimed at extreme DSP applications. At least that product looks like one can actually use it, and it does something. Although 30W power dissipation is just about twice what most folks can deal with. Austin dp wrote: >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply >>range. 0.2V is not much voltage at all... I would have thought >>transistor threshold voltages would have caused issues at such a low >>voltage. How are they achieving such low threshold voltages? > > > Sounds interesting to me as well, perhaps some of the other 90nm > manufacturers could shed some light - does it really work? Probably > not at full speed, but even at DC - do the FETs really turn on at 0.2 > V? > While I am not sure what this synchronous/asynchronous gimmick is > all about I would say I am glad they may soon have a marketable > alternative to the rest of the makers, I guess they all became a bit > too big to talk to (and stay innovative). > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------ > > > Bevan Weiss wrote: > >>Jim Granville wrote: >> >>>For those interested in Async devices, and uses : >>> >>>http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562 >>> >>> >>>It is a way's off being usable, but the numbers are impressive :) >>> >>> No mention of device size, but the info suggests they target the >>>high-price/low volume user space. >>> [ Not too many customers need -196'C :) ] >>> >>>.. and no mention of design tools, which may prove to be a bigger >>>challenge than the silicon. >>> >>>-jg >> >>I'm amazed they have achieved this operation over the 0.2V - 3.9V supply >>range. 0.2V is not much voltage at all... I would have thought >>transistor threshold voltages would have caused issues at such a low >>voltage. How are they achieving such low threshold voltages? >> >> >>Bevan > >Article: 101135
Hello all, I am attempting to expand the 18x18 multipliers as provided in the xilinx Spartan 3 series. I followed the proposed implemention of expanding the multipliers as described in the xapp467.pdf app note (figure 5). However, I arrived at an impasse: When the operand is splitted up in 2 or more partial operands of 18 bits, the sign-extension of the operand does not carry over -I'll expalin: E.g Lets say we want to multiply (-1)in18bitsx(1)in 22bits.The 22 bit operand is splitted in 2 4-bit(lsb) and 18-bit(msb) operands. Thus, when we multiply the lsb part: 3FFFFh(=-1)x1h=3FFFFFh(=-1), we obtain a non-nil answer. However, when we multiply the msb part: 3FFFFh(=-1)x00000h=000000000h, we obtain a nil answer. When the 2 partial products are added and the bits properly weighed as to constructed the final product, the msb bit(sign bit) will be 0. Consequently, resulting in a positive product when a negative one was expected (-1 was expected, FFFFFFFFFFh.) I feel I must be doing something wrong.. Please advise -RogerArticle: 101136
Roger Bourne wrote: > Hello all, > > I am attempting to expand the 18x18 multipliers as provided in the > xilinx Spartan 3 series. > I followed the proposed implemention of expanding the multipliers as > described in the xapp467.pdf app note (figure 5). However, I arrived at > an impasse: > When the operand is splitted up in 2 or more partial operands of 18 > bits, the sign-extension of the operand does not carry over -I'll > expalin: > E.g Lets say we want to multiply (-1)in18bitsx(1)in 22bits.The 22 bit > operand is splitted in 2 4-bit(lsb) and 18-bit(msb) operands. Thus, > when we multiply the lsb part: 3FFFFh(=-1)x1h=3FFFFFh(=-1), we obtain a > non-nil answer. However, when we multiply the msb part: > 3FFFFh(=-1)x00000h=000000000h, we obtain a nil answer. When the 2 > partial products are added and the bits properly weighed as to > constructed the final product, the msb bit(sign bit) will be 0. > Consequently, resulting in a positive product when a negative one was > expected (-1 was expected, FFFFFFFFFFh.) > > I feel I must be doing something wrong.. > Please advise > -Roger Ooops, I forgot to sign-extend the lsb partial product before the summing of the partial products. I hope that take care of the problem.. -RogerArticle: 101137
When I test my udma33 interface , I write the first sectors with LBA address mode,but the datas I read from the same address are diffrent from which I write in.Article: 101138
Are you performing the LSbit multiply as unsigned? Figure 5 of that app note shows the LSbits of the 22-bit A vector coming in unsigned while B is applied as defined. A=M+L (L>0, M==A>>n) A*B = M*B + L*B If B is negative, the L*B result is negative and the sign extension has to be included in the post-multiply adder. "Roger Bourne" <rover8898@hotmail.com> wrote in message news:1146065155.946945.162590@i39g2000cwa.googlegroups.com... > Hello all, > > I am attempting to expand the 18x18 multipliers as provided in the > xilinx Spartan 3 series. > I followed the proposed implemention of expanding the multipliers as > described in the xapp467.pdf app note (figure 5). However, I arrived at > an impasse: > When the operand is splitted up in 2 or more partial operands of 18 > bits, the sign-extension of the operand does not carry over -I'll > expalin: > E.g Lets say we want to multiply (-1)in18bitsx(1)in 22bits.The 22 bit > operand is splitted in 2 4-bit(lsb) and 18-bit(msb) operands. Thus, > when we multiply the lsb part: 3FFFFh(=-1)x1h=3FFFFFh(=-1), we obtain a > non-nil answer. However, when we multiply the msb part: > 3FFFFh(=-1)x00000h=000000000h, we obtain a nil answer. When the 2 > partial products are added and the bits properly weighed as to > constructed the final product, the msb bit(sign bit) will be 0. > Consequently, resulting in a positive product when a negative one was > expected (-1 was expected, FFFFFFFFFFh.) > > I feel I must be doing something wrong.. > Please advise > -Roger >Article: 101139
"Dave" <dave@comteck.com> wrote in message
news:pan.2006.04.26.11.20.11.317645@comteck.com...
>I have never done an FPGA design and I am considering purchasing the
> Starter Board. It has crossed my mind to implement at least part of a
> design I did in an ASIC many years ago. The largest part of the ASIC
> design was a "funnel" shifter. Basically the shifter operated as a barrel
> shifter on the 96-bit input and output the 21-bits beginning at any
> designated position. Cycle time was one clock.
>
> Is this doable with the XC3500 on the Starter Board? How much of the
> logic would this consume? Any thoughts on what the max clock rate would
> be?
>
>
> Thanks!
>
> ~Dave~
With almost no effort to speed the process you can easily achieve 85 MHz
with 261 LUTs (2% of the XC3S500E-4) giving you a full 0-127 rotate of a
96-bit vector with 21 bits out. If you replicate some select bits you can
improve on the timing. If you pipeline the operation, you can do better
still.
module
funnel
( input clk
, input [95:0] large_word
, input [ 6:0] select
, output [20:0] selected
);
reg [ 6:0] s;
reg [20:0] selected;
always @(posedge clk) s <= select;
wire [147:0] s4 = {large_word[51:0],large_word};
wire [ 51:0] s3 = s4 >> (s & 7'h60);
wire [ 27:0] s2 = s3 >> (s & 7'h18);
wire [ 21:0] s1 = s2 >> (s & 7'h06);
wire [ 20:0] s0 = s1 >> (s & 7'h01);
always @(posedge clk) selected <= s0;
endmodule
Article: 101140king wrote: > to colin: > > but it really happend :-( > the frequency is 155MHz, and I made channel banding once a time > when the data flow is slow, there is nothing wrong > but as soon as the data flow becomes fast (also working at 155MHz), > the 4 channels can not receive a special mark at the same time > so I think they are lossing channel banding > > I wonder what happend when the speed of data flow changes, and why this > can > result in the loss of channel banding. > > Thanks a lot!! > > king > You need to rephrase your problem in a way that makes sense so that someone can help you. The numbers of bits that are being transmitted and received will always be the same so you can't simply say "as the data flow becomes fast" you need to elaborate on this so that others can understand what is happening. You also haven't mentioned which device you are using or the protocol that you are using, so it is next to impossible to help out. Ed -- Xilinx Inc.Article: 101141
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:444f3d60$1@clear.net.nz... > > I realise that, of course, - the comment still stands : > Do you have an app that needs to go to -196'C ? > Mars is the only deployment I can think of, most others are > covered by the terrestrial Military -55'C - 125'C range. > > -jg How cold does it get in space? (where no one can hear you scream) They'd potentially have another market if the increased the operating temperature well beyond 130'C - downhole applications in the oil industry, for instance.Article: 101142
I want to verify few of my concepts about Processor Local Bus (CoreConnect) in Xilinx FPGA. I know each master on PLB is connected to PLB arbiter on a seperate read and write bus. But i am confused about the shared connection between the PLB slave and PLB arbiter. Is this connection is parallel too. I mean i can see its shared but shared means still 64-bit parallel right ????Article: 101143
Dear All,
I have a requirement to convert the edge of a clock that the data is
valid on. I want to clock data into an entity on the falling edge of a
clock and clock data out of an entity on the rising edge of the same
clock.
Is the code below sufficient to achieve this functionality? Any
pitfalls that I might fall into?
Regards,
Simon
***********************************************
entity clock_edge_conversion is
port (
word_stream_out : out std_logic_vector ( 9 downto 0 );
reset : in std_logic;
clock : in std_logic;
word_stream_in : in std_logic_vector ( 9 downto 0 )
);
end clock_edge_conversion;
architecture RTL of clock_edge_conversion is
begin
process ( clock, reset )
variable temp_word : std_logic_vector( 9 downto 0 ) := B"00" & X"00";
begin
if ( clock'event and clock = '0' ) then
temp_word := word_stream_in;
end if;
if ( reset = '0' ) then
word_stream_out <= (others => '0');
elsif ( rx_rocket_io_clock'event and rx_rocket_io_clock = '1' ) then
word_stream_out <= temp_word;
end if;
end process;
end RTL;
***********************************************
Article: 101144Hi all, On www.poderico.co.uk you can download the free C compiler for Picoblaze version 1.7.7 In the next 2 months the optimizer should be ready and the code generated will be shorter. I' wish to design the debugger too. Any help and suggestions is welcome. FrancescoArticle: 101145
>They'd potentially have another market if the increased the operating >temperature well beyond 130'C - downhole applications in the oil industry, >for instance. How hot are those ..?Article: 101146
You'll probably have a hard time making it through synthesis. You'll need to... 1. Break it into two processes, one triggered by the rising edge of clock, the other by the falling edge. 2. Change 'temp_word' from a variable to a signal so that it can be transferred between the two above mentioned processes. 3. The 'initial value' that you assign to temp_word is usually not synthesizable. Add an if condition to initialize it to what you want based on the signal 'reset' much like you have for "word_stream_out". 4. Consider using 'rising_edge(x)' and falling_edge(x) functions that are a part of ieee lib instead of x'event and x = '1'. It's more readable. 5. I'm assuming that "rx_rocket_io_clock" is a typo and that you meant to say "clock" since there is no signal called "rx_rocket_io_clock" KJArticle: 101147
Dan McDonald wrote about using ISE on Linux: > You will be able to do everything up to generating the programming > file. The drivers, however, are 32-bit only - so you can't actually > program it when running a 32-bit kernel. Dan obviously meant that you can't program devices when running a 64-bit kernel, since the drivers are 32-bit. Xilinx, *please* give us 64-bit cable drivers in the next service pack, or at least the next release (8.2i?)! Thanks! EricArticle: 101148
Francesco wrote: > Hi all, > On www.poderico.co.uk you can download the free C compiler for > Picoblaze version 1.7.7 > In the next 2 months the optimizer should be ready and the code > generated will be shorter. > I' wish to design the debugger too. > Any help and suggestions is welcome. Binary only? Windows only? - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 101149
KJ schrieb: > 4. Consider using 'rising_edge(x)' and falling_edge(x) functions that > are a part of ieee lib instead of x'event and x = '1'. It's more > readable. The second form is also a simulation mismatch. A transition of x from 'U' to '1' (as it can occur at simulation start) is not a rising edge, but it is an event on x with x = '1'. The same is true for transitions from 'H' to '1' and 'X' to '1'. Kolja Sulimma
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