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Respected , knowledgious people,i m student of M.Sc. Electronics 4th semister .i m working on a project on newer tech. related to implementation of DSP algorithms on FPGA.so presently i m doing project related to speech in which i have to implement LPC analysis and synthesis filter on FPGA .I m doing all this for voice morphing as a application.so please give any help to undestand algorithms related to voice morphing with hardware view.thanks in advance. kapilRespected , knowledgious people,i m student of M.Sc. Electronics 4th semister .i m working on a project on newer tech. related to implementation of DSP algorithms on FPGA.so presently i m doing project related to speech in which i have to implement LPC analysis and synthesis filter on FPGA .I m doing all this for voice morphing as a application.actually i have implemented some circuits on fpga by using VHDL ,but with DSP its my first experience.so please give some information about which FPGA i preffer to target ,is this project fissible with fpga or not.basic information i have to kept in mind.thanks in advance. kapilArticle: 101276
The actual MGT pins are completely determined by the MGT location from the ucf: "INST aurora_module_i_1/lane_0_mgt_i LOC=GT_X0Y1;" You can specify this location in the Coregen GUI as another poster mentioned or simply edit the ucf afterwards like the "Using High Speed Serial MGTs with the Aurora IP" at http://www.xilinx.com/univ/xupv2p.html does. Don't forget to change any other per MGT constraints such as the "Phase Align Module" LOC. Paul billu wrote: > > Hi There, > > I just generated a Aurora sample design that communicates between 2 > MGT's using Coregenerator. How do I configure two specific MGT's to be > used in the design (say MGT4 & MGT9). I tried to use PACE to assign > I/O's of the Aurora design to the pins on the board. But, the MGT pins > are disabled. (color coded:Brown and the legend:Gigabit serial) How do > I assign the assign the TX signals (TX_N & TX_P) and RX (RX_N & RX_P) > to the MGTs? > > Thx in advance, > BilluArticle: 101277
You can try to play with the PRIORITY keyword: e.g. # the lower the PRIORITY number, the higher the priority TIMESPEC TS_In1 = PERIOD In1 60 MHz PRIORITY 0; TIMESPEC TS_In2 = PERIOD In2 50 MHz PRIORITY 1; HTH, Jim (jimwu88 at yahoo dot com)Article: 101278
andrew.hood@gmail.com wrote: > So I want to program a serial data flash (SDF) using the SPI protocol > but my board/software seems to be unhappy with that idea. I am using a > USB Platform Cable and I have been using Xilinx's xspi.exe program. I > KNOW the documentation says that one needs to use either a PC3 or PC4 > cable to do this but you'd figure Xilinx would write something to > support their new-fangled USB cable. Does anyone have a method they'd > like to share for using the Platform Cable USB to program SPI? > > Thanks! > Andrew, The JTAGkey comes with JTAG.dll, spi.dll and i2c.dll. All these protocols can be remoted via USB JTAGkey at a 1Hz to 6MHz. Regards, LaurentArticle: 101279
Hello John,
This is also not working. It is creating distributed RAMs. Is there
any problem with the version of synplify. I am using 8.0. Also used
syn_ramstyle directive.
One more thing not related to this issue; can you guide me to some good
study materials about synplify synthesize techniques and constrains
(different clock domains, clock relations etc etc). And xilinx PAR
techniques.
Article: 101280Karl wrote: > Here are the details. The DSP kit should also become 2C70, but the > webpage is not updated yet... > > http://altera.com/products/devkits/altera/kit-video-cyclone2.html Very cool, the very first kit with the 2C70 :-) It looks like I'll have to roll my own extender card to get network, mass storage, and kbd/mouse. Thanks Karl. TommyArticle: 101281
Brian Drummond wrote: .. > One worth looking at - if you want Spartan-3 and PCI - is the > "Raggedstone" from Enterpoint. > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html .. This looks greate, but it costs 1.2k$ http://www.xilinx.com/bvdocs/images/ipcenter/product_images/DO-V4-ML455-DK_l.jpg Here are nice boards but all of them cost >>1k$ http://www.hitechglobal.com/Xilinx/boards.htmArticle: 101282
Larry, the OP asked about using Xilinx Platform Cable for SPI programming, not about altermatives. purchasing jtagkey for 139EUR (what ist just a box with ft2232c+lever shifter) just to program an SPI flash only because Xilinx is doing so bad with the support of their own cables in not so much an option. Xilinx USB platform cable could of course theoretically do spi programming as it it based on Cypress FX2 + upgradeable CPLD, but xilinx is doing a bad job with the support of the cables. All the xilinx SPI support seems to be done by some students, that would explain why there is no support for USB platform cable, as such support would require update for the usb platform cable and that info is was possible not available for those who wrote the XSPI thing. Too bad - the Xilinx USB cable is quite nice piece of hardware but its so closed design, that it well of course it could be reprorammed to be Altera Byteblaste :) - firmware for this is now under GPL and available (sure the PLD should be updated as well to be plain bypass) sorry for ranting - but I have had to mess up with some boards that are using Xilinx CPLD+spi solution and are supposed to be programmed with the xilinx SPI tool. And that experiences is just another 2 weeks of my time wasted in frustration. Antti Xilinx - please dont get upset (again) - I say what I think, and I cant (and dont wanna) change that. For the Xilinx Platform Cable issues there is a very elegant solution - no work at required from Xilinx just a matter of making a decision - so here it comes: IDEA for Xilinx -------------------- Open up the Platform USB Cable design in such manner that it could be used by 3rd parties, eg the Cable would still start and configure as it normally does but afterwards a secondary protocol could be used to reload new firmware and re-enumarate as new device with new host drivers. All that is needed from Xilinx is the decison that such use is OK and some small bits of information - all the rest would be done by the community - of course, everything that happens with the cable after the secondary protocol is no longer under Xilinx control meaning that there is no support required from Xilinx. This would allow the cable to be used as SPI programmer or any some other gadget as required.Article: 101283
I was wondering what's the tariff classification of an FPGA development board. Searching through some documentations, I ended up thinking that it may be this: 8542.70.00 or Electronic microassembly. Any person around here knows what it might be. This call specially goes to ppl who are exporting to the EU. Many thanks JacquesArticle: 101284
king wrote: > to McGettigan: > > thank you for your remind. > > I use the VII Pro xc2vp20 device. > There are 8 GTs, and I used 4 of them. > The protocol is Custom. > The clk is 155MHz, the data width is 2 bytes, > So these 4 bonded channels could process 10Gb/s data flow in theory. > > Unfortunately, however, it could only work at 1.5Gb/s in field. > At this(1.5Gb/s) time, all the things looks right: > The FSM on both TX and RX sides transformed well,no invalid state, no > invalid transmition. > And the Rocket IO works well: no rxlossofsync, no rxnotintable... > RX can receive the 4 SOPs at the same time(channel bonding ok). > > As soon as the flow rate increase to 2Gb/s and upper, > The RX side could not receive the 4 SOPs simultaneously, > which is one of the transmition conditions of my RX FSM, > so the FSM will stop. > And I know that it lossed channel bonding. > In order to overcome this error, I send CBS once again as soon as > sending 65535 data packets at TX side. > CBS would let the RX FSM continue to move, but it looks wierd. > There are some invalid transmition happend, > And some error signals of Rocket IO appears, such as rxlossofsync, > rxnotintable. > > That is my problem. > > Many thanks! > > king > Ok, this has more information on your problem, but I still need to make some assumptions such as these: 1) You are communicating between 2 seperate boards 2) Each board has its own clock source and thus some frequency PPM difference 3) Your custom protocol transmits 8b10b characters 4) Your custom protocol transmits a clock correction (CC) sequence when in IDLE My initial thought is that your custom protocol has not been designed to properly handle the necessary amount of clock tolerance. When each link is transmitting 1.5Gbps with IDLE/clock correction characters between bursts the receivers are able to insert or delete enough of the IDLE/CC characters to handle the frequency difference between your receiver and transmitter. When you increase the burst size and the time between the IDLE/CC transmissions you exceed the size of the elastic FIFO in the receiver and get an underflow/overflow condition and your link goes bad (loss of channel bonding, invalid characters, etc..). You mentioned transmitting 65535 data packets followed by a CBS (Channel Bonding Sequence). Even if a data packet was only 2 bytes, this would definitely be creating problems as most protocols would generate a CC every 4-8K bytes. Instead of creating your own custom protocol I would suggest using the Aurora protocol that we developed and deliver as part of CoreGen. This will handle everything that you want to do including channel bonding in a nice simple package. Ed -- Xilinx Inc.Article: 101285
In comp.arch (and others) there is a thread on this Opteron Virtex4 coprocessor that sits in socket 940. http://www.dailytech.com/article.aspx?newsid=1920 http://www.theregister.co.uk/2006/04/21/drc_fpga_module/?www.dailytech.com http://www.drccomputer.com/pages/products.html I wonder what others think of this, at $4500 its way to steep for most individual buyers who might happen to have a dual socket Opteron board (I don't), but I wonder if companies like Digilent, Enterpoint and others might see any opportunity to build a much lower cost edu version that is more in line with the cost of an Opteron cpu chip say <$1k and based on best Spartan3 or Virtex2,4 that can still use Webpack. I also wonder how much faster exactly the HT link is over any of the PCI interfaces. John Jakson transputer guyArticle: 101286
hey friends , I'm trying to design an interface between a ps2 keyboard and the digilent DIO5 board which contains a Xilinx CoolRunner CPLD. but the Xilinx synthesis tool Xst drove me crazy here are the errors I got followed by my VHDL code please help me WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... ========================================================================= * Final Report * here is my code ---- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity kbd is port( kclk,kd,uclk : in std_logic; -- keyboard clk , keyboard data , universal clk ,respectively s_ca: out std_logic_vector(7 downto 0); -- seven-segments display s_an: out std_logic_vector(3 downto 0)-- seven-segments anode ); end kbd; --}} End of automatically maintained section architecture kbd_archi of kbd is signal ready : std_logic := '1'; -- 11 bits have been received signal data : std_logic_vector(7 downto 0); -- ASCCI character pressed constant keyup : std_logic_vector := x"f0"; -- keyup character signal dr : std_logic_vector(10 downto 0); -- a temporary register to hold the data coming from the kbd signal count : std_logic_vector(1 downto 0) := "00"; -- to indicate that the key up has been received and expecting the final data signal ssg : std_logic_vector(7 downto 0); -- seven-segments temp. register begin p1 : process(kclk) subtype int is integer range 0 to 11; variable cnt : int := 0; begin if falling_edge(kclk) then if cnt /= 11 then dr(cnt) <= kd; cnt := cnt + 1; ready <= '0'; else ready <= '1'; cnt := 0; end if; end if; end process p1; p2: process(ready) begin if ready ='1' then if dr(8 downto 1) = keyup then count <= count + 1; ready <='0'; else if count = "01" Then count <= count + 1; ready <= '0'; end if; end if; else dr <= dr; end if; end process p2; p3: process(uclk) begin if rising_edge(uclk) then if count = "10" then data <= dr( 8 downto 1); count <="00"; else data <= data; end if; end if; end process p3; s_an <="1110"; with data select ssg <= "00111111" when x"45" , "00000110" when x"16" , "01011011" when x"1E" , "01001111" when x"26" , "01100110" when x"25" , "01101101" when x"2E" , "01111101" when x"36" , "00000111" when x"3D" , "00000111" when x"3E" , "00000111" when x"46" , "00000000" when others; s_ca <= not ssg; end kbd_archi;Article: 101287
Antti wrote: > unfortunatly FPGA companies do not support 3rd party programming cables > :( > > so as example if you want to evaluate nios or use signalTap then you > need altera supported cable But can't you get an SVF stream out of the vendor tools then use a generic SVF player to actually run the program operation? This wouldn't work for the fancy stuff (like auto-detecting a chain) but won't it work for the basic operation of doing a prom program, etc? -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 101288
Stephen Williams wrote:
>
>
> OK, Xilinx was uniquely unhelpful this time, so I resort to this
> list. My setup is a SystemACE connected to 1 or 2 Virtex2 FPGAs,
> and also to a PPC405GPr running Linux. The second FPGA is optional,
> and when the optional FPGA is installed, the JTAG is rerouted through
> and a different ACE file supplied. The CF card contains a second
> partition where the Linux fs (ext3) lives.
>
> My problem is that when the second fpga is installed, the board
> will crash Linux within a few minutes. The SystemACE driver is
> getting an error that the JTAG configurator was unable to read
> the configuration stream from the CF. (This is 1/2 nonsense, because
> the chips were programed by the SystemACE under the watchful eye
> of u-boot before Linux was even started.)
>
> The second FPGA is getting programmed (during u-boot) because the
> PPC is able to discover it's PCI id at boot time.
>
> The CFGADDR[2:0] bits are unconnected on our board, as are the
> CFGMODEPIN, POR_BYPASS and POR_RESET. The CFGPROG goes to both
> FPGA devices (with a single pullup.) The CFGINIT is connected to
> only the first FPGA.
>
> So does anybody have any clue why in blue blazes the SystemACE is
> going nuts when the second FPGA is installed?
> - --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
Not enough information on your problem.
1) In the single Virtex-II case, what does the complete JTAG chain look like?
2) In the dual Virtex-II case, what does the complete JTAG chain look like?
3) Have your connected the DONE pins of the Virtex-II devices together?
4) In the dual Virtex-II case, do both device go DONE?
5) Which device is connected to the MPU port of the SystemACE device?
6) What holds the PPC405GPr in reset until both Virtex-II devices have been configured?
7) What exactly is a PPC405GPr, I think that this is discrete PPC405, but which one?
8) What exactly does this mean?
"The SystemACE driver is getting an error that the JTAG configurator
was unable to read the configuration stream from the CF."
9) It sounds like you filed a case with our hotline, what number were you assigned?
Ed McGettigan
--
Xilinx Inc.
Article: 101289Wow - this topic has got lots of activity. Ben, thanks for pointing out the APU bits - I was aware of these and do have this value already in place (I am running 7.1, although I keep thinking of trying 8.1). As for interrupts, I just think that if I was hitting one that the OCM or PLB busses would jump to that location and try to fetch the instruction at the interrupt handler, on top of the fact that a simple "move register" command shouldn't cause an interrupt to occur to begin with. I'll keep the interrupt possability on the board to come back to in case my current train of testing doesn't pan out. At this point, I have disabled cache in order to remove one more possible issue from the design. The current train of thought I'm working on is getting an SDRAM/OCM Virtex-4 system working on a Xilinx ML403 development board and comparing it to my SDRAM/OCM system. So far I have got the LED test to work out of SDRAM when running the core at 2x the PLB clock speed (my system does 3x, but the dev board has issues running at 3x). So here are the things I am going to try first 1) Try my system running at a 1:1 ratio 2) Try our customized PLB controller on the dev board Hopefully, I can get some information out of these two steps...Article: 101290
People here are driving me crazy insisting that the Xilinx factory has told them that you *MUST* tie the mode pins to either Vaux or GND. After finding all the info in the data sheet and talking with support, it looks pretty clear to me that the S3 parts have a very stiff internal pull up and there is no need for an external pull up of any kind, resistor or direct connection to Vaux. Am I misunderstanding? Why did the factory tell us before that the mode pins *MUST* be tied to Vaux? Did we misunderstand what they were saying? I promise this is the last time I will ask about this. I am totally sick of going around this loop with everyone here.Article: 101291
the answer is almost always: Yes/No all the in-system-programming and JTAG stuff is not as much standard as it could be. there have been many attempts to develop vendor neutral or at least multi-vendor technologies but all attempts have failed so far. its seems that big boys have big issues playing it nicely in a (common) sandbox, so almost all vendors have some 'special' things making the 'generic' things not fully useable. xilinx has XSVF a binary version of SVF, some Xilinx parts can not be programmed with standard SVF, lattice has SVF-Plus altera has its own flavors of JAM/STAPL actel has its own flavors of STAPL if you think a SVF player is a SVF player is a SVF player, then no it isnt, same for JAM/STAPL there are small things that make some the all stuff not fully compatible. sure for some cases it works, works also cross vendor, but there is absolutly no guarantee. as example for Lattice XP you need VME player (VME is converted from SVF) version 11 or above, similarly some xilinx PLDs may require some special version of XSVF player to work, etc... there are lots of small things... AnttiArticle: 101292
by stiff mean smaller pullup value than 47-100kohm? if that so then its something that is not well known - ASFAIK no FPGA have stiff pull's before (or after configuration). AnttiArticle: 101293
In article <1146246311.256472.241490@j73g2000cwa.googlegroups.com>, "JJ" <johnjakson@gmail.com> writes: |> I wonder what others think of this, at $4500 its way to steep for most |> individual buyers Still way cheaper than a Cray XD-1... RainerArticle: 101294
Lovely Robot wrote: > hey friends , I'm trying to design an interface between a ps2 keyboard > and the digilent DIO5 board which contains a Xilinx CoolRunner CPLD. > > but the Xilinx synthesis tool Xst drove me crazy > here are the errors I got followed by my VHDL code > please help me > > WARNING:Xst:1710 - FF/Latch (without init value) has a constant value > of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, > FF/Latch (without init value) has a constant value of 0 in block . > WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without > init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due > to other FF/Latch trimming, FF/Latch (without init value) has a > constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch > trimming, FF/Latch (without init value) has a constant value of 0 in > block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch > (without init value) has a constant value of 0 in block . > WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without > init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due > to other FF/Latch trimming, FF/Latch (without init value) has a > constant value of 0 in block . WARNING:Xst:1291 - FF/Latch is > unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in > block . WARNING:Xst:1291 - FF/Latch is unconnected in block . > WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit > ... > ========================================================================= > * Final Report * > > here is my code > ---- > library IEEE; > use IEEE.STD_LOGIC_1164.all; > use IEEE.STD_LOGIC_UNSIGNED.all; > > entity kbd is port( > kclk,kd,uclk : in std_logic; -- keyboard clk , keyboard data , > universal clk ,respectively > s_ca: out std_logic_vector(7 downto 0); -- seven-segments display > s_an: out std_logic_vector(3 downto 0)-- seven-segments anode > ); > end kbd; > > --}} End of automatically maintained section > > architecture kbd_archi of kbd is > > > signal ready : std_logic := '1'; -- 11 bits have been received > signal data : std_logic_vector(7 downto 0); -- ASCCI character > pressed > constant keyup : std_logic_vector := x"f0"; -- keyup character > signal dr : std_logic_vector(10 downto 0); -- a temporary register to > hold the data coming from the kbd > signal count : std_logic_vector(1 downto 0) := "00"; -- to indicate > that the key up has been received and expecting the final data > signal ssg : std_logic_vector(7 downto 0); -- seven-segments temp. > register > begin > > p1 : process(kclk) > subtype int is integer range 0 to 11; > variable cnt : int := 0; > begin > if falling_edge(kclk) then > if cnt /= 11 then > dr(cnt) <= kd; > cnt := cnt + 1; > ready <= '0'; > else > ready <= '1'; > cnt := 0; > end if; > end if; > > > end process p1; > > p2: process(ready) > begin > if ready ='1' then > if dr(8 downto 1) = keyup then > count <= count + 1; > ready <='0'; > else > if count = "01" Then count <= count + 1; > ready <= '0'; > end if; > end if; > else > dr <= dr; > end if; > end process p2; > > > p3: process(uclk) > begin > if rising_edge(uclk) then > if count = "10" then > data <= dr( 8 downto 1); > count <="00"; > else > data <= data; > end if; > end if; > end process p3; > > s_an <="1110"; > > > > with data select > ssg <= "00111111" when x"45" , > "00000110" when x"16" , > "01011011" when x"1E" , > "01001111" when x"26" , > "01100110" when x"25" , > "01101101" when x"2E" , > "01111101" when x"36" , > "00000111" when x"3D" , > "00000111" when x"3E" , > "00000111" when x"46" , > "00000000" when others; > > s_ca <= not ssg; > > > end kbd_archi; I noticed that both "P1" and "P2" processes assign a value to "ready". I'm surprised that ISE didn't complain about that. It looks like you meant process "P2" to be a counter. However, you didn't supply a clock, so "count <= count + 1" will synthesize to combinatorial logic (gates) only. This may lead ISE into "thinking" that it doesn't need FF's for "count". Also, assigning an initial value when a signal is declared (signal ready : std_logic := '1') may not synthesize. It would be better to initialize them when the circuit is reset. HTH -Dave PArticle: 101295
Jeff Brower wrote: > Steve, Peter and Austin- > > Can you give definitive instructions -- or point me to who can -- for > initializing an array of registers? > > I need to initialize an array of registers in one way, set values > differently upon Reset, and set values differently again during normal > operation. I have this code: > > reg [31:0] array [11:0]; > > // synthesis attribute INIT of array is 64'h0C0001820C000080; > > which is intended to initialize the first 2 elements of the array, but > doesn't set any bits although XST appears to "accept" the INIT > attribute. What is needed? The whole 384 bits set with one number? > Can this be done using 384'hxxxx... syntax? > > I have opened a webcase through our local FAE, but after about 3 weeks > have no clear answers other than to instantiate a RAM using CoreGen and > use a .coe file, or read in a .dat file for simulation purposes but not > synthesis. To use a RAM I would have to switch the array row/column to > get XST to recognize asynchronous reads, and I have done that in other > cases, but in this case I can't because I actually need 32-bit > registers (they are accessible via a host processor). > > For something like array initialization, there has to be a solid answer > -- hopefully some actual code showing how to do it. > > Thanks. > > -Jeff Jeff; I don't have an answer for you, but since your code appears to be in verilog, I wonder if you'd get a response by posting in comp.lang.verilog. -Dave PArticle: 101296
gburx@yahoo.com.au wrote: > Hi, > > I've got a little knowledge about fpga's. I've used for fun spartan2 at > school. > I'm interested in embedded systems in view of operating systems. > Which development platform (starter kit) do you suggest for such a > person like me ? > > My expectations are: > * low costs, > * "helpfull hand" - projects from which I can learn, gain knowledge, > documentation (I haven't met ppl yet here who would help me with it - > that's why it's so important for me as it gonna be my very begging with > this stuph), > * included good development software (with cores which would allow me > to start to play), > * features of platform (ethernet, usb, video, audio, connectors etc). > > The nice thing would be to have PCI. Either edge or slot. > > XUP Virtex-2 Development Platform (http://www.digilentinc.com/) - it > cought my attention. > Are there better platforms ? > > Thanks. IIFC, the Xilinx guys (Peter and Austin) have said that Xilinx offers big discounts on devlopment boards to students. Other companies may offer discounts as well. HTH -Dave PArticle: 101297
fpga_toys@yahoo.com wrote: > We have modems today that broke the modulation "laws" set in 60's ... > by more than an order of magnitude. I wrote: > What "laws" are those? AFAIK, today's modems are still subject to the > Shannon-Hartley Theorem and the Nyquist Sampling Theorem, which > substantially predate the 1960s. Perhaps these putative "laws" from > the 1960s were promulgated by people with little understanding of > information theory? fpga_toys@yahoo.com writes: > Without a doubt. "Information theory" and achievable practice would > take several decades to mature in the progression of doctorial study, > general graduate study, and finally in the 1970's become mainstream > undergraduate material. [... long description of changes to phone system ...] OK, but that still doesn't explain what "laws" were broken. I was an engineer at Telebit, the company that introduced the world's first 18Kbps dialup modem in 1985 (though I didn't join the company until 1991). Telebit's patented PEP modulation is the forerunner of OFDM, now widely used in many digital communication systems. But I don't recall any claims that the Telebit modems were breaking any "laws", nor were the Bell 212A/V.22/V.22bis modems that came before, nor the V.32/V.32bis/V.34 modems that came after. V.90 is somewhat of a special case, in that it does not work between two analog subscriber lines. > But much more than that, was a steady progression of improvements in > the transmission channel, which started out with attachment limitations > of acoustical connection to the carbon mics on 500 desk sets that were > the norm in the mid 1960's and into the 1970's. Carbon packing, analog > voice bandwidth with loading coils of around 5 KHz, purely analog > encode/decode circuits, etc ... all let if common knowledge that the > upper limit on consumer modems was well under 1200 baud. "Common knowledge" is much different than "laws". Telebit's modem technology worked fine on phone connections much worse than what the US had in the 1960s. It was widely deployed in countries with poor telephone infrastructure, where modems using standard modulation technology were useless. Several of Telebit's modem engineers speculated that it should be possible to run PEP over tin cans and string, and still get a stable (but relatively low bit rate) connection, but AFAIK the experiment was never actually conducted. EricArticle: 101298
Of course that is the point, get rid of what you don't really need, the special purpose motherboards that can only be made in tiny volumes at very high NRE costs, and get on to something alot more HPC people already have, a spare socket perhaps. Next step is to use cheaper parts for entry level but I suppose the PCi... boards could fill that role. John Jakson transputer guyArticle: 101299
Jim Granville <no.spam@designtools.co.nz> writes: > FWIR, what enabled them to sidestep the apparent limits, was the > Group Delay equalisation, and the ability to trade-off Signal/Noise for > more apparent bandwidth. [= DSP and better Codecs ] And (in some cases) the use of multiple carriers, rather than a single carrier, which simplifies everything else. > That takes things in rather a different direction than Nyquist/Shannon... Not really. They are still completely applicable. > This has fed-on into ADSL (which also keeps advancing), ADSL DMT uses OFDM modulation (Orthogonal Frequency Division Multiplexing, a multicarrier modulation). > and I think 10GBd Ethernet uses the same ideas. Not really. 10GBase-T uses a modified 16-level pulse amplitude modulation, which is more closely related to 1000Base-T than to what telephone and DSL modems use.
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