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Hello, I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, my cpld some times work and sometimes does not work at that frequency. If I lower the clcok frequency to 12MHz then it always work. bu tin both cases the chip does get hot. I put a heat sink on the chip but if the chip works for long hours then it effects its functionality. Can anybody advice me how to slove this problem? JohnArticle: 101026
<bachimanchi@gmail.com> wrote in message news:1145863736.590389.143060@u72g2000cwu.googlegroups.com... > Hi all, > i am currently working on altera FPGAs,when i was trying to generate a > memory using megafunction wizard,in the options it is registering both > inputs and outputs of the memory,and i have the option of > not-regestering the output.But as the input is registered when i use > the component it is not giving the expected value.Can anyone tell me > how to disable the option of not registering he inputs. > > waiting for reply, > > Thank you, > > > Regards > Ramakrishna Is the address value already registered? One thing the Synplify synthesizer will do for an asynchronous style memory is provide a registered output for a live address *or* a live data for a registered address. If you can come up with your next-cycle's address one cycle early, the *required* address register can "look like" the live address you otherwise wanted. Once you know that the address *must* be registered, designing for that requirement is pretty simple. If your address is going to be one of 2 values and you can't make the decision of which one immediately, a single-port RAM could be implemented as a dual-port with the two different addresses with the choice of read data coming up after the actual read.Article: 101027
"Devlin" <springzzz@gmail.com> wrote in message news:1145768982.221641.314840@u72g2000cwu.googlegroups.com... > When I complied any project with ISE 8.1 webpack with SP3, I got > warnings like below: > > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0 > duplicate design unit: 'Module|stopwatch' > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate > design unit: 'Module|stopwatch' > > Does anyone know what does it mean? or how can I avoid this? > thanks a lot. If you have an include file with a verilog module (stopwatch) then every time you reference that include file it will see that a module of that name has already been defined. It may be that an identical implementation will give a warning while a different implementation will give an error or at least a different warning. This all may also apply to VHDL.Article: 101028
Hi Robin, Interestingly enough, I believe this group started off with this charter:- CHARTER The unmoderated newsgroup comp.arch.fpga will be open to discussions on all topics related to the use of reconfigurable Field Programmable Gate Arrays (FPGAs) as computational engines. see:- http://groups.google.com/group/comp.sys.super/browse_thread/thread/7d1569e95c6b7722/df354dd08c5eff91?lnk=st&q=%22comp+arch+fpga%22&rnum=1&hl=en#df354dd08c5eff91 That's why it's in the comp. hierarchy. Perhaps you should complain about all the non-computing folks spamming your newsgroup? :-) Cheers, Syms.Article: 101029
John, "Quite hot" Anyway to be more specific? If you can hold your finger on it, that tells us one thing. If you can't even touch it (as it is boiling water) that is another. If it is somewhere in between, that tells us something else. Austin john wrote: > Hello, > > I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, > my cpld some times work and sometimes does not work at that frequency. > If I lower the clcok frequency to 12MHz then it always work. bu tin > both cases the chip does get hot. I put a heat sink on the chip but if > the chip works for long hours then it effects its functionality. Can > anybody advice me how to slove this problem? > > John >Article: 101030
Would you have been "happy" if the response simply said "2) yes. http://www.x..." rather than adding that the information is already quite available on the site? A well thought out question or one that's fleshed out with comments on what you've already found would help to avoid the silly "Yes." responses. Giving the audience a clue into your true needs will get those needs fulfilled better than asking too-simple questions. "AnonymousFC4" <afc4@noemail.net> wrote in message news:j_qdnaYA7PwG99fZRVn-sQ@comcast.com... > Austin: > I am aware of google search... so be reasonable. > If you post with a Xilinx email address, you may refrain from the "RTFM" > type of answers... > -- > So if you have any experience, the fact you may to work for xilinx, does > not > disqualify to post... with details (the good, the bad, the ugly) about > your > experience, we will all benefit from... and Xilinx as a company will also! > > Hope it will be more answers from individuals more willing to share their > experience on this topic. > ---Article: 101031
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4b4hneFvg226U1@individual.net... > > However, if you plan decode 32 bit or 128 bit IP addresses, > an FPGA solution will likely cost just as much and not > work quite as well as a real CAM. > > -- Mike Treseler But if each 128-bit IP address only needs 4 slices and the number of IP addresses is rather limited, the cost can be much better than a real CAM.Article: 101032
Hello, Its something in between if the heat sink is on. JohnArticle: 101033
Hi all, I need desperate help in two areas: 1. Can i do CRC check while transmiting data from PLB master to PLB slave. If yes than what are the best technique i can use. 2. Can any buddy tell me the data format for PLB transaction. I mean does it have any specified fields like any other standards or all 64 bits are assigned for data??? If so can i put assign different fields like 16 bits for CRC 4 bits for type of data and 4 bits for length of data. Please forgive me for my little education about PLB and FPGA. ThanksArticle: 101034
John, Which tells me that with the heatsink, you may be right on the edge of overheating the die (anyway). Without the heatsink, it is hopeless (junction temperature is way out of spec). Sounds to me like heat is the problem, but without real measurements, I have no way of knowing for sure. Austin john wrote: > Hello, > > Its something in between if the heat sink is on. > > John >Article: 101035
The Silicon Valley Homebrew Robotics Club has several
members using the Digilent 3e starter kit to learn
Verilog and FPGA design. We are all newbies and a
few of us are trying to do this using Linux. Attached
is a posting I did to describe some problems and some
work-arounds to those problems.
Jürgen Böhm wrote:
> 2) Will the ISE 8.1i software run under Novell/SuSE 10.0 64-bit Linux too ?
No.
=================================================================
TO: Home Brew Robotics Club
Silicon Valley Linux Users Group
WHAT: This note briefly describes how to get the Xilinx FPGA
development tools to work on Linux
To learn FPGA design I followed in the steps of Chris Palmer
of the HBRobotics Club and ordered a Digilent "Spartan-3 Board"
for $99. You can order one at http://www.digilentinc.com/
Download the Xilinx free WebPACK 8.1i development software
from the Xilinx web site. You have to register, but it is not
too intrusive. The download is almost 900MB. Xilinx provides
an IDE that looks like a C and Tcl/Tk wrapper around a bunch
of command line tools. Instead of trying to keep up with the
latest kernels and libraries, Xilinx just puts every library
and executable it needs into the download and makes the tool
completely self-contained. They missed libXm.so.3 and I had
to copy it from a Fedora Core 3 system. (They built the IDE
on Red Hat Enterprise Edition 3). For the record, I use
Mandriva 2006 but it does not seem to matter too much which
distribution you use.
The key to getting the Xilinx tools to work on Linux is to
follow the directions at http://gentoo-wiki.com/HOWTO_Xilinx
This page tells where to download, and how to install the
parallel port drivers for the JTAG programming cable that
comes with the kit.
As root, install the software with "sh WebPACK_81i_SFD.sh".
Run the software as root and select HELP->Software_Updates
to get the latest updates from the Xilinx web site.
The quick start is in Xilinx/doc/usenglish/books/docs/qst.pdf.
Open this with xpdf or evince and follow the directions to
create, build, and download a four bit counter. I made a
typo error when editing the design and the tools wouldn't
let me proceed until I fixed the error.
I am just learning Verilog / VHDL but I'd be happy to help
if you want help getting to your first download of an FPGA
circuit.
Bob Smith
Article: 101036John_H wrote: > "Devlin" <springzzz@gmail.com> wrote in message > news:1145768982.221641.314840@u72g2000cwu.googlegroups.com... > > When I complied any project with ISE 8.1 webpack with SP3, I got > > warnings like below: > > > > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch_map.ngm" line 0 > > duplicate design unit: 'Module|stopwatch' > > WARNING:ProjectMgmt - "G:/test/watchver/stopwatch.ngc" line 0 duplicate > > design unit: 'Module|stopwatch' > > > > Does anyone know what does it mean? or how can I avoid this? > > thanks a lot. > > If you have an include file with a verilog module (stopwatch) then every > time you reference that include file it will see that a module of that name > has already been defined. It may be that an identical implementation will > give a warning while a different implementation will give an error or at > least a different warning. This all may also apply to VHDL. John; This is the warning message I get when running a VHDL project using ISE 8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3", where "MON_v3" is my top VHDL module. I also have 2 lower level modules. I built a very similar project with no errors/warnings when I used ISE 7.1SP4. I tried seaching for "duplicate design unit" on Xilinx's web site, but didn't find the warning. Would this be suitable for a web-case? -Dave PollumArticle: 101037
I'd suggest you look for high-drive I/O or bus contention. Your dynamic power consumption should be minimal so where is the power going? Have you looked at the part in "reduced power mode?" That might give you insight into I/O versus core supply. If the part draws 200 mA at 5V without I/O, 1W would be used to determine the minimum case temperature from the theta-jc. Do you have thermal data for that package? I only fount the mechanical info in the data sheet. "john" <conphiloso@hotmail.com> wrote in message news:1145902382.532784.313830@v46g2000cwv.googlegroups.com... > Hello, > > I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now, > my cpld some times work and sometimes does not work at that frequency. > If I lower the clcok frequency to 12MHz then it always work. bu tin > both cases the chip does get hot. I put a heat sink on the chip but if > the chip works for long hours then it effects its functionality. Can > anybody advice me how to slove this problem? > > John >Article: 101038
"Dave Pollum" <vze24h5m@verizon.net> wrote in message news:1145906965.687960.25460@u72g2000cwu.googlegroups.com... > > John; > This is the warning message I get when running a VHDL project using ISE > 8.1SP3: "..MON_v3.NGR line 0 duplicate design unit: Module|Mon_v3", > where "MON_v3" is my top VHDL module. I also have 2 lower level > modules. I built a very similar project with no errors/warnings when > I used ISE 7.1SP4. > > I tried seaching for "duplicate design unit" on Xilinx's web site, but > didn't find the warning. > Would this be suitable for a web-case? > -Dave Pollum I'd expect unexplained/undocumented errors and warnings would each warrant a web case. I haven't run VHDL through XST - I'm a Verilog guy in Synplicity tools. Would it be safe to say you don't use include files (at least ones that reference the modules)? If you don't use them, the "duplicate" arrangement I envisioned wouldn't be an issue.Article: 101039
Hello, I recently requested advice as to performing bit-matrix multiplication on bit matrices (bitwise AND followed by a population count), one matrix stored onboard an fpga in block rams, the other one (first operand) streaming in row by row. It was thought that one of the latest pcie cards would be able to provide dot-product throughput limited by the pcie input speed of 16 Gbps for pcie x8. The adders would be 80-bits wide (80 bits arrive per cycle at 200 mhz over pcie x8) and each column of the onboard matrix would be stored in 80 block rams. My question is: How much more difficult is the problem if I must find out the maximum dot-product, and which column produced it, for each input vector? This operation must be performed for each input row, yielding 1 max and argmax for every 1000 input bits. The input vector is 1000 bits long, of course, and finishes arriving over pcie after about 12 pcie cycles. Is there a fast enough way to argmax 1000 numbers that are 10-bits (representing each columns dot-product)? What would the cost of the argmax operation be in fpga space as compared to the column adders (which are probably 80-bits wide for each column)? Thanks for your help. I want to make sure that the max and argmax functions will not be a limiting factor in the design of the bit-matrix multiplier. Also, thanks for so many helpful comments that have gotten me to this level of understanding of the problem. - AndrewFArticle: 101040
Robin Bruce wrote: > So, who here would be interested in creating a reconfigurable > computing only group? Incidentally, one exists already at > openfpga.org: > > http://www.osc.edu/forums/w-agora/index.php?bn=oscgeneral_openfpga > > It's been quiet so far but I think it just needs a push to get > started. It may however be too far off the beaten track to ever see > much action. John Williams started a partial-reconfig-mailing list a few years back: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ You can find the list archives here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Traffic is moderate, but I believe most active "reconfigurators" read it and post there regularly. I think this list is "the place to be" when you're doing something with partial reconfig at the moment. cu, SeanArticle: 101041
lecroy7200@chek.com wrote: > It appears that the Stratix II is not going to be fast enough for the > first stage. The primary problem is the lack of being able to support > a synchronous parallel bus. Looking in the October 2005 Stratix II GX > handbook, the fastest reference clock appears to be 622MHz, far below > where I want to run at. I could run a slower clock, use the SERDES to > multiply it up and resync the data and expand it out as you suggest, > but this really does not make a lot of sense. The clock already has > phase noise under 5pS rms (from testing) and the data would be matched > going to the device. I tried the SERDES approach you mentioned with > the Quartus tools using the Stratix II as a target device (even though > we have a full license for Quartus the tool requires TalkBack spyware > when targeting a GX device) and it seems to work. I tried to set the > clock to the frequency I am interested in and the tool barks back with > an error. I then tried a very simple approach of just using clocked > register but no luck. > > I have seen a few Virtex 4 designs now that directly run a parallel bus > at the speeds I am interested in. I am a bit gun shy after all the > problems we have seen with Xilinx over the years, but they seem to be a > better fit for this application. > > If you have any other ideas, I would be interested in hearing them. You might want to take a look at the Lattice SC device its PURESPEED IO has 2 Gbps throughput per differential I/O pair. http://www.latticesemi.com/products/fpga/sc/index.cfmArticle: 101042
I *didn't* address the message to anyone at Xilinx. This was an open message to everyone who uses Xilinx parts and might have something to comment about it. If you review the other thread on the documentation shortcomings of the Spartan 3 parts, you will see that at least one poster has encountered such signficantly difficult to resolve issues that they consider the solution to be proprietary information. You are a big proponent of how good a job Xilinx does on support. Instead of asking why I posted the message, have you considered asking why a significant issue such as 1 kohm pullup resistors on the configuration pins remains largely undocumented? It was only after I found that confusing sentence shown below that I realized that these resistors are also on the JTAG pins. I have been asked repeatedly why I did not use a pull down resistor on JTAG my board like the other designs here use. My answer was that this is what I am used to using. I nearly changed the design since I had no strong conviction either way. Now I realize that if I had used a pull down of typical 1 to 4.7 kohms, the circuit would not have worked at all being biased in an undefined region. Come on Austin. Don't shoot the messenger! Listen to the message and work on your internal processes. If it was important enough to create an answer record and was not in the data sheet, someone should have made sure that it found its way into the data sheet in a clear and accessible manner. BTW, I still don't know if the configuration pullup resistors are disabled by the HSWAP_EN signal. Anyone out there know the answer? I really don't know if Xilinx does. I would love to see a clear and comprehensive table covering all the pins. Austin Lesea wrote: > Rick, > > Why not just email all of this to Steve Knapp directly? Or me or Peter > for Virtex parts? > > Seems that if you'd like to help us by pointing out anything confusing > or inconsistent, you could get it to the right party in one step. > > I agree with you that answers should be scrubbed for any update to a > document. It is the little things that drive us all crazy. > > Austin > > > rickman wrote: > > I still have not completely figured out the pull up resistors on the > > Spartan 3 chips. It would appear that the data sheet has never been > > thoroughly reviewed for omissions and errors. Some of the information > > that should be clearly indicated in any number of places is missing > > and/or misleading. > > > > "A Low logic level on HSWAP_EN activates the pull-up resistors on all > > I/Os during configuration." Does this include the dedicated > > configuration signals? How about the dual purpose configuration pins? > > Or is it just the User IO? > > > > I found this sentance to be especially unenlightening... > > > > "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, > > HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a > > pull-up resistor to HSWAP_EN during configuration, regardless of the > > value on the HSWAP_EN pin." > > > > What does a "pull-up resistor to HSWAP_EN" mean??? Why would TDO have > > (or need) a pull up to any value since it is a full time output? > > > > Why does Xilinx make it so hard to get the all important details on a > > part that has been in full production for so long? They just updated > > the Spartan 3 data sheet this month! Why wasn't the information that > > they know is lacking included? I say they know info is lacking because > > you can find it in an answer record if you know to look for it. > > > > I may put up a web page detailing all the short comings in the Spartan > > 3 devices and documentation. > >Article: 101043
Hello, I was looking at a similar issue recently. The problem is that bluetooth dongles are SLAVE devices -- or in the USB terminology, simply USB devices. They are supposed to work under the control of a USB host (controller), which is ussualy a PC. The USB host has to perform USB bus enumeration and probably other complex tasks. This means your FPGA has to perform the tasks of a USB host ... (see USB Complete 3rd edition, Jan Axelson) Also note that the bluetooth dongle is supposed to be powered-up by the power lines (5V) available on the USB interface ... Finally, the bluetooth protocol is quite complex and implementing the bluetooth stack is not trivial. You may want to take a look at http://www.bluez.org/ to get an idea. There are USB controllers that implement the OTG (On The Go) supplement to USB. They allow devices to comunicate with other devices -- that is, allow devices to work as hosts. (see http://www.usb.org/developers/onthego/) Check the datasheets for Philips ISP1362, TransDimension TD242LP, Cypress CY7C67200EZ-OTG My advice to you is to use a eb100-SER (http://www.a7eng.com) module. It has the full bluetooth stack implemented in firmware with a serial profile available on power-up and they say 230kb/s bandwidth. You connect to this module over a serial UART (easy to implement in an FPGA). It's simple to use and it worked for me ... :) According to me you face a nice project but a huge one most probably... Good luck and hope this helps. CristianArticle: 101044
During the design of my latest FPGA, I wrote a vhdl cpu emulator. I would like to know if there is interest in the (open source) FPGA community for such a vhdl cpu emulator? The emulator supports: reading and writing from / to memory on the FPGA waiting for interrupts or set periods of time multiple threads cpu global registers thread local registers setting local registers based on thread arguments when spawning one level while loop one level of if with else statement outputting data read during a read to a file CPU commands come from a main file, and each thread has its own separate file. If there is already something like this out there, I would love to hear about it. Thanx, nachumArticle: 101045
hi ALL!! i have a small query, FPGA geeks help me plz... I have a question on the XDL report, i am acually trying to move a circuit by modifying the XDL file, btw i am using a Virtex II FPGA. i have been successful in moving the slices and the pins to differnt locartion but not the routers, i was able to decode the slice info., but not the routrers information. Please help me in decoding the routers info. i have attached a small report on the routers info from the XDL file, the info that i have attached it the output net of the 2 input AND gate. ======================================================= net "Z_OBUF" , inpin "Z" O1 , outpin "Z_OBUF" Y , pip R17C1 Y3 -> OMUX10 , pip LIOIR16 OMUX_NW10 -> IOIS_FAN_BX2 , pip LIOIR16 IOIS_FAN_BX2 -> O1_B1 , ; ========================================================= i want information on OMUX, FAN_BX2, and where i can get info on them, please help me with the routers info, i am stranded with this for the past 3 days. i will thanful if you could throw some light on it. A speedy reply will be appreciated.Article: 101046
Rick! Back off -- I am on your side. I am just asking that you send comments to the appropriate person in Xilinx (too). Go ahead and post (it is your time, and your effort). I don't have a problem with that. But, if you post something that can be fixed, at least give us the oppostunity to fix it. If we screw up, then OK, scream and rant, and do whatever makes you feel better. Its a big company, with many products, and millions (literally) words of documentation. I didn't say we were perfect. In fact I said we were imperfect, and looking for ways to get better. I have spent about two hours today trying to identify where in the process APD and GPD could do better. I am still trying to find the best way to attack the problems, and provide the best solutions. It has long been an issue with me that tech answers should automatically feed back into documents, and then have a sunset so they go away after a suitable time when the docs now have the info (OK to have both for awhile). That is my job (as a principal engineer) here at Xilinx: to be an agent for change (for the better). It is in my job description. So, I really appreciate that you post (it directly helps me to fufill my job responsibilities), but if I don't have to go to the newsgroup to read it, it makes it even easier for me. OK if you don't. I am just asking (nicely). Thanks for today's tough task, by the way. As for "the answer" I can't do that in Spartan land, as I have no easy access to the chip schematics like I do for Virtex. If it was Virtex X+1, I just go to the schematics and dig for awhile. Sorry I can't do that for you on this one, AustinArticle: 101047
"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> schrieb im Newsbeitrag news:444d0565$0$20704$ba620e4c@news.skynet.be... > Antti wrote: >> Hi >> >> does anyone know what should happen on read access to DDR >> memory space when external connections to DDR memory >> are not correct? I am troubleshooting a custom board and >> what I see is that OPB DDR controller makes total OPB bus >> freeze on first DDR read access. ToutSup=1 and then nothing >> happens. In the datasheet DQS strobe is going to WREN of >> read fifo so I could think a missing DQS from external chip could >> cause bus freeze, but I am not really sure as it is not described >> in the datasheet (eg what should happen on missing DQS). > > It freeze ... ie, never acks the transfer. > > We use the ddr controller from EDK (without any ipic/ipif, just the > bare controller that's common to plb_ddr, opb_ddr & co) and > if the phase shift of the second dcm is off, it never acks and > thus freeze. > > > Sylvain thanks! this is what I guessed too, just wanted confirmation that it really freezes when no DQS on reads are seen. AnttiArticle: 101048
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:1145896022.809609.5340@t31g2000cwb.googlegroups.com... >I still have not completely figured out the pull up resistors on the > Spartan 3 chips. It would appear that the data sheet has never been > thoroughly reviewed for omissions and errors. Some of the information > that should be clearly indicated in any number of places is missing > and/or misleading. > > "A Low logic level on HSWAP_EN activates the pull-up resistors on all > I/Os during configuration." Does this include the dedicated > configuration signals? How about the dual purpose configuration pins? > Or is it just the User IO? > > I found this sentance to be especially unenlightening... > > "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, > HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a > pull-up resistor to HSWAP_EN during configuration, regardless of the > value on the HSWAP_EN pin." > > What does a "pull-up resistor to HSWAP_EN" mean??? Why would TDO have > (or need) a pull up to any value since it is a full time output? > > Why does Xilinx make it so hard to get the all important details on a > part that has been in full production for so long? They just updated > the Spartan 3 data sheet this month! Why wasn't the information that > they know is lacking included? I say they know info is lacking because > you can find it in an answer record if you know to look for it. > > I may put up a web page detailing all the short comings in the Spartan > 3 devices and documentation. > Rick TDO is not is not full-time output (or at least doesnt have to be) TDO is driven when JTAG TAP is in 'shift' states and tri-stated otherwise so a pullup makes sense :) AnttiArticle: 101049
Hello to the group! I've been struggling to get the Xilinx IOCM and DOCM modules working with the PPC405 in my current design and I'm starting to run out of ideas. The first iteration of the design uses cached SDRAM via the PLB to store/load the boot code and runs without issue. Since the design is starting to get full (running out of LUTs, but BRAMs are available), it was decided that it might be worthwhile to use the OCM interface to cut down on logic. The OCM should be the perfect solution because the boot code is currently only called once and then code executes out of SDRAM. I have been able to get the OCM modules connected and currently the boot code makes it through without issue. The problem occurs just after the conditional jump to SDRAM: the first instruction out of SDRAM is completed and then PPC405 stops. I have been able to connect via a debugger and everything appears to be fine at the stopped location, but if I step the processor, it gets lost and never returns. I am not sure why it stops at this point (See code below). I have gone through the OCM/Virtex-4 information and everything seems ok: * The errata 212/213 fix is in place * Cache is disabled (cache was working fine on the first design) * I have compared all the PPC registers at the point of failure with the values from the first iteration and have found no major unexplainable differences * I have added a PLB_IBA core and observed that the OCM design loads the first four instructions from SDRAM after completing the boot code. I have verifed that these instructions are correct. After this point, however, there is no more activity on the PLB nor the OCM busses * An ILA on the OCM bus showed that the instructions stop being executed by the IOCM following the jump (and it looks like a few extra instructions are loaded from IOCM because of the conditional branch) * Neither the ILA nor the PLB_IBA cores showed an error/abort occuring. The debugger did not indicate that any exceptions had occurred * I have tried changing the OCM values (range checking/fixed latency/auto-detect clocking), but this seems to make no difference * The memory map used: SDRAM 0x0000 0000 - 0x01FF FFFF DOCM 0x2080 0000 - 0x2080 1FFF IOCM 0xFFFFC000 - 0xFFFF FFFF * The Assembly code is nothing fancy: ... 0xffffca2c main+0x258: 7c0903a6 mtctr r0 <entryPt> 0xffffca30 main+0x25c: 4e800421 bctrl 0x2000: 7ca62b78 mr r6, r5 0x2004: 7c852378 mr r5, r4 ... Basically it seems like the bus is hooked up correctly, but that maybe a register bit or mode is not correct. I am wondering if anyone in this forum has the IOCM/DOCM working and also executes code out of SDRAM (or anyone else who has comment) - are there any register bits that I might have left out? Does software have to do anything differently now that the design is non-cached (I have tried initializing all cached registers...)? Thanks, -Charles Eddleston
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