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Hi That difference in ES and production samples are taken care. Any way what we have got is production samples. We are using ISE 7.1 version. rgds bijoyArticle: 99426
Hmm.. does that means I have to invoke the process manually? I'm not sure if I got you correctly. Anyways, I have a problem generating the ACE file from within the EDK (XPS) environment for this particular case (dual ppc405 core).Article: 99427
Hi I have a board with Spartan-3-e mounted on it. I am using HSWAP pin as an User I/O. I forgot to put an external pull-down resitor on HSAWP pin, will it have any problem in configuring the FPGA ? please help me. rgs bijoyArticle: 99428
Does anybody knows what is the best way to connect DAI (PCM digital audio interface) which must be master and to connect it to USB ? Is there any USB chip that have slave DAI on it ? thanksArticle: 99429
Hi, Can you do this: Take the tricky part of the design into a new blank design on its own. Get the P&R to churn away on that until it gets something that works (should be easier, as there is nothing from a huge design to get in its way). Then export that routing to a ucf, as suggested by Ray, and finally re run with this ucf for the full design. I could be completly wrong - but it might save you the hassle of hand placing. Maybe something like PlanAhead also - that seems to be incredible for constraining the P&R tools in a graphical way - check out the Demos on Demand for it on the Xilinx website.Article: 99430
Hello! I am looking for anybody who could help me to try synthesis my design in Precision2005c. Private replay. Thank you, ChristopherArticle: 99431
Hello There! We need to profile our software program that runs on the MicroBlaze SCP. We referred to the Platform Studio user guide. It says so: "The following steps illustrate profiling on a MicroBlaze program. The system has BRAM and External Memory. The system has an opb_timer, and the Interrupt signal is directly connected to MicroBlaze External Interrupt signal. The opb_timer is used as the profile timer on MicroBlaze." I think the addtion of opb_timer can be done froom the "Add/Edit cores" dialog (correct me if i'm wrong). But how do i "directly connect" the interrupt signal to MicroBlaze External Interrupt signal? Thanks. - DN.Article: 99432
On 2006-01-19, Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: > From what I understand in Linux you can install/remove drivers on the > fly (you might be able to do this in Windows if you know what you're > doing). Something I've done in Linux is to simple open /dev/mem and mmap it. No driver needed and you can access your PCI card directly. If you need support for DMA you usually need a driver though, but you can do some experiments by simply booting linux with the argument mem=248M for example. If you have 256M of memory this will give you 8 megabyte free for your own usage. It is ugly, but a great way to debug your stuff before you write a complete driver. /AndreasArticle: 99433
On 2006-01-17, John Adair <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: > Coming in the next batch are Ethernet Phy, IDE, Video Codec, 5V tolerant I/O > to name a few. I don't have the full list with me so those are just the ones > I can remember. These should be available in 4-8 week time frame assuming no > design issues. What are the specs for the Ethernet Phy board? 10, 100 or 1000 mbit? /AndreasArticle: 99434
Yes, I've seen thit too. It's not as bad since SP2, but its still there. I used to bitch about Quartus all of the time, since 8.x came out all I do is bitch about ISE.Article: 99435
Ray wrote: > > The thing is, it no longer picks the low hanging fruit (ie the direct connects) >consistently, which in turn congests the other routing resources. > One thing I've done in 5.x and 6.x ( but haven't tried in 7.x or 8.x ) that seems to work OK is to go into FPGA editor with a simple test design, find the delays for the direct connect paths I want it to use, then stick a MAXDELAY on those nets to force the router to use those connections. This has worked well in conjunction with placed logic without resorting to the directed routing constraints ( at least for the small sections of critical logic that I've used it for so far, I'm not sure if a horde of MAXDELAYs would blow up P&R for a big RPM ). BrianArticle: 99436
I'm wanting to get a handle on how much can be done on what size FPGA [leaning more to the qualitative than quantitative]. I do not plan to actually implement something but to get enough background to intelligently listen to some discussions. I've been to http://en.wikipedia.org/wiki/FPGA but found "Programmable Logic: What's it to Ya?," http://www.netrino.com/Articles/ProgrammableLogic/ more focused on what I'm looking for. Searching this group on Google I found references to "Xilinx FPGAs: A Technical Overview for the First-Time User". Interesting, but too focused on the internals for my needs/desires. Through various links found these sites to answer some needs http://www.andraka.com http://www.fpga4fun.com/ http://www.opencores.org/ Does this group have a FAQ? Any other suggestions of links? Thank youArticle: 99437
Falk Brunner wrote: > Symon schrieb: > >>> 1. Support for a lot of chips, say 2048 of them. JTAG supposedly >>> supports 16 chips. Yeah, right. The 5MHz clock signal dies out after >>> three or four. The 200KHz signal dies after eight or nine. This will >>> require some strong signals with error correction, but, heck, if a >>> basic ethernet layer can do it.... >>> >> >> Hi Brannon, >> I agree with much of what you write. >> As a workaround for your clocking problems, you could try source >> terminating the clock driver from your JTAG controller. On my platform >> cable USB I use a > > HMMMM??? SOURCE-Termination for a multidrop CLOCK signal? It may work, > but more due to murphys law than by design . . . > > AC-termination at the end of a clock line is most probably the better > way to go. And don't forget, those parallel port often enough spit out > really ugly signals. So a buffer for the clock line with a schmitt > trigger input and a RC-filter in front pays off. > Many years ago, I had to build a parallel-port to JTAG pod. Simple enough, indeed. But one wrinkle I added was to take two parallel-port bits for the clock, with a S-R flipflop in the pod. Pulse one bit to set the clock, and one to reset. Yes, it was a fraction slower, but it stopped any parallel line-bounce in its tracks.Article: 99438
This module is 10/100. We have plans for modules that will do more but it is going to be a while before we do those. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan3 Development Board. http://www.enterpoint.co.uk "Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message news:e00mhm$f86$2@news.lysator.liu.se... > On 2006-01-17, John Adair > <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: >> Coming in the next batch are Ethernet Phy, IDE, Video Codec, 5V tolerant >> I/O >> to name a few. I don't have the full list with me so those are just the >> ones >> I can remember. These should be available in 4-8 week time frame assuming >> no >> design issues. > > What are the specs for the Ethernet Phy board? 10, 100 or 1000 mbit? > > /AndreasArticle: 99439
johnp wrote: > Note that both circuites route from a YQ output, jump two slices, > then go to a BY input. Yet, the net delays vary by 200 psec. > > Ideally, I'd pack the 2 flip-flops in one slice, but in my design they > are clocked by opposite clock edges as I convert a DDR signal from > the negedge into the posedge domain. Are you using local inversion for that? I.e. are you using the same clock in both cases to enter the slice, and then use pos-/neg-edge stuff inside the slices? If so, in one case the local inverter for the clock adds some delay, in the other case it's not used. Maybe the difference in the delay originates in the clock delay introduced by the inverter. cu, SeanArticle: 99440
Richard Owlett wrote:
> I'm wanting to get a handle on how much can be done on what size FPGA
> [leaning more to the qualitative than quantitative]. I do not plan to
> actually implement something but to get enough background to
> intelligently listen to some discussions.
I would suggest learning verilog or vhdl for
use in synthesis an simulation.
> Searching this group on Google I found references to "Xilinx FPGAs: A
> Technical Overview for the First-Time User". Interesting, but too
> focused on the internals for my needs/desires.
This group is mainly focused on Xilinx architecture details.
An HDL design can be used with any architecture.
> Does this group have a FAQ?
http://www.fpga-faq.org/FAQ_Root.htm
> Any other suggestions of links?
Here are some vhdl design and simulation examples:
http://home.comcast.net/~mike_treseler/
Good luck.
-- Mike Treseler
Article: 99441dotnetters@gmail.com wrote: > And how do I synthesize the components seperately and then finally > "merger" them together? We work in XPS. Is it possible to do it in XPS > itself directly? Sorry, I don't know XPS. But usually synthesis tools offer the following steps: 1) read HDL source & analyze (= syntax check) 2) elaborate / compile (= synthesis) 3) save the existing database 4) load saved databases plus read & analyze of the next upper component This means after mapping the function to the primitives (compilation) and before place & route it is possible to save the result. This saved result can be read, when the next upper component needs these already synthesized components. Another option would be to synthesize and place & route all subcomponents. Don't care the pin mappings (take a "random" mapping). Because you are not interested in the test if the subcomponent is working, you just need the synthesis to complete. RalfArticle: 99442
Tim, I did not intend to be sarcastic. Perhaps it sounded so. It is true that when we were on allocation, there were no dates possible until you were placed in the queue. We subsequently had a lot which yielded incredibly well (the beginning of a nice and long hard fought for trend). In any event, I apologize, I didn't intend to offend or insult. Just explain what happens. If, as you say, we did not give you a date until you ordered, that is consistent with something being on allocation: only those on order have dates. Those not on order are not even in the queue. At that time, we had no idea what the yields would be, so we could not give a delivery date. Having been so badly beat up (justifiably so) for delivery issues, when we actually succeeded, I was shocked to see your complaint, that is all. It is a Catch-22, as you say. Works both ways. We don't know either. Austin Tim wrote: > Austin Lesea wrote > > >>If you order them, they will arrive. I think that is how it is supposed >>to work? >> >>Sometimes sooner, sometimes on time (and the objective is to never be >>late). >> >>So don't blame us that we delivered an order, please! > > > > Yes, I do blame Xilinx. Because the line you give out is that a delivery > date cannot be quoted until an order is placed. And if we want to discover > the date at which volume will be available, we have to place a large order > for delivery ASAP. Are you familiar with Catch-22? > > I am puzzled by the tone of your response. What I posted was more than > amiable, considering the treatment dished out by your distributors (for whom > I know you take no responsibility) and you use a public forum to dump your > sarcasm on me. That was inappropriate. > > >Article: 99443
Antti, Personally, I think the purchasing agent should refine their negociation skills. If you will not accept an early shipment, that has to be specified in the purchase agreement. Of course, asking the distributor to stock for you (which is effectively what you are doing) will cost them money (evening out the supply/demand), which will raise the price to you. "There ain't no such thing as a free lunch." (TANSTAFL) We have some control over our yields, but it is in everyone's best interests that our yields get better and better. If the yield jumps up (defect denisity jumps down) due to a process improvement and learning because we churn out so many wafers, then we will suddenly have all the parts we need. Our our costs go down, our margins go up, and we have more room for negociating prices with our customers. Sounds like we can never make everyone happy. Don't yield, we get roasted. Yield well, we get flamed. Oh well. AustinArticle: 99444
Austin Lesea wrote: > Back to Kevin: > "Every customer that doesn't use a particular function > that is hard-wired on the chip is essentially paying for wasted silicon. " > Austin "Paying for wasted silicon"... isn't that what FPGAs are all about, wasting a bunch of silicon so that you get the benefit of the small portion that you use? In fact, isn't that the crux of the philosophy of Easypath, not testing all the unused, wasted silicon? Once a Xilinx FAE was trying to explain the economics of FPGAs (logic vs. routing) and expressed the fact that the routing dominates the die area by saying, "We sell you the routing and give you the logic for free". That was supposed to mean that I should not be concerned that I could not use all the logic (wasted silicon) because of routing congestion. Ironic that Xilinx would hold Kevin's feet to the fire for understanding wasted silicon when Xilinx's entire business model is founded on "wasted silicon". ;^)Article: 99445
Have you filed this with the hotline? It really helps if when you catch it, you archive everything and send it in (if at all possible). No one is perfect. Software has bugs. Some more annoying than others. This sounds serious enough that someone would be put right on it. Austin typhon62 wrote: > Yes, I've seen thit too. It's not as bad since SP2, but its still > there. > I used to bitch about Quartus all of the time, since 8.x came out all I > do is bitch about ISE. >Article: 99446
"Richard Owlett" <rowlett@atlascomm.net> wrote in message news:1227pqr8pit2eab@corp.supernews.com... > > Does this group have a FAQ? > Any other suggestions of links? > > Thank you > Richard, www.fpga-faq.com Or put FPGA FAQ into Google? ;-) HTH, Syms.Article: 99447
sorry, it wasnt me complained, but as I had heard a similar story to the posting here, so I posted what I heard. The story was commented with general remark that things with order and deliveries got worse since Avnet swallowed Memec. I dont know the all background, but I can understand that the impossibility to get leadtimes without orders and orders shipped too early can get people upset. Sure it may have been that some one did not read the very fine print. AnttiArticle: 99448
Rick, I don't understand your comment. Of course we have "wasted" silicon. That is the basis of the whole FPGA architecture. It is also the basis for our success: Knowing what to put in the chip, and what not to put in the chip. Knowing what to hardern, and what not to harden. Making bizillions of the same chip to get economies of scale so the "wasted" silicon doesn't cost the customer what it would if it was an ASIC. It is more of an issue if you are a structured ASIC (back to Kevin... he gets it). If you are a structured ASIC, you are attempting to be a platform for a wide range of designs, with two or three masks for all customization. You need: MGTs, BRAMs, DSPs, PLLs/DLLs, EMACs, PCIe, (and the list goes on, and on, and on). As an ASIC this is really expensive, if no one uses even one of these cells. That is serious area we are talking about here. Doubling the area with wasted stuff. For an FPGA, the routing alone used up area (along with the memory cells to control it) so adding a whole bunch of hardened IP just made the FPGA more of a bargian, not less. Adding less than 5% area with stuff that may, or may not get used, but is used far more often than interconnect! Austin rickman wrote: > Austin Lesea wrote: > >>Back to Kevin: >>"Every customer that doesn't use a particular function >>that is hard-wired on the chip is essentially paying for wasted silicon. " >>Austin > > > "Paying for wasted silicon"... isn't that what FPGAs are all about, > wasting a bunch of silicon so that you get the benefit of the small > portion that you use? In fact, isn't that the crux of the philosophy > of Easypath, not testing all the unused, wasted silicon? > > Once a Xilinx FAE was trying to explain the economics of FPGAs (logic > vs. routing) and expressed the fact that the routing dominates the die > area by saying, "We sell you the routing and give you the logic for > free". That was supposed to mean that I should not be concerned that I > could not use all the logic (wasted silicon) because of routing > congestion. > > Ironic that Xilinx would hold Kevin's feet to the fire for > understanding wasted silicon when Xilinx's entire business model is > founded on "wasted silicon". > > ;^) >Article: 99449
> Roger, > Look at making your filter as a series of half-band FIR filters. These are > efficient in that every other tap is zero. (Nice and easy to multiply by > zero!) Use three, decimating by two at each stage. Your implementation > should be a lot more compact. I am new to the digital filter world. Every day I discover a new type another type of digital filter, so perphaps (or most probably) I am wrong in my following observation: How can a half-band FIR filter be employed as a decimating FIR filter for a downsampling factor of 2 ? If my limited understanding of half-bands (Lth-bands=2) is accurate, then the stopband of the half-band will lie above Fs/4 (Fs/2 -Fpass, where Fpass cannot exceed Fs/4). This will violate the anti-aliasing criterion and as such will make it non-viable to use as a decimating filter. What am I missing? (From what I can tell from Mr.Google, halfs-bands are very popular, so my reasonning must be off...) -Roger
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