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fpga_toys@yahoo.com wrote: > It's the NRE and volume commitment that are the real OUCH. Hmmm ... I thought I saw a statement there was a 10,000 min for the program, which I don't see any more .... might not be as big a hit.Article: 99226
exactly as expected. unless you are 10M pcs/year customer you dont get SATA PHY's anttiArticle: 99227
Neil Glenn Jacobson wrote: > The new Xilinx Platform USB cable does work under Linux. You apparently > read some out-dated information. > > You are right, I found that information. What I saw before was from October of last year. So I guess I will give that a try, before spending more time getting the cable IV to work.Article: 99228
John, I'm not saying your ideas won't work, I am saying that you have a very large task ahead of you, perhaps larger than you realize. I'd like to see you pull it off, as doing so would mean that you've solved a number of vexing problems that have plagued the RC community for a long time. A solution to many of those problems would also greatly benefit the designers of static designs as well. So far, however, your posts have pretty much focused on whining about what you can't get rather than on solutions to the known problems. There is a tremendous amount of FPGA experience and knowledge among people on this newsgroup. I believe many of us have tried to point out the pitfalls (that many of us have already encountered) so that you might have an easier time navigating the field. Your responses so far have mostly been whining about what you can't get rather than looking at ways to get around those obstacles within the framework of what is available. Posting it here and not listening to the advice the seasoned veterans here have offered only serves to sour people on your ideas. If you truely feel you've discovered a route to success that others who've been playing in this field for over a decade have not seen, then it would make sense for you to first get patent protection for your ideas, and then go into Xilinx and other FPGA vendors and negotiate with them for what you want. If you have a convincing story, I suspect they'd be asking you what you need rather than the other way around. If you can solve the fast PAR issues, for example, you could probably fund your development with the proceeds from the FPGA companies lining up at your door to buy rights to your PAR algorithms. > >>I respectfully suggest you try first to get the system together >>using perfect FPGAs, When I referred to the system, I am not just talking about the FPGA boards. That's the easy part. I am referring to the implementation tools, libraries, user interfaces etc. Many of the major pieces you need are still a long way from being developed enough to be usable in a general purpose RC system such as you have described.Article: 99229
>Most IIR filters are constructed as cascaded biquads (and sometimes one >first order section). The choice of the biquad structure has a >significant impact on performance. I compared an [8th order lowpass chebychev lowpass filter, 16-bit fixed point] with [2nd order lowpass chebychev lowpass filter, 16 bit fixed point, whose frequency I multiplied by 4 as to emulate a 4 2ndorder-cascaded-structure]. I used WinFilter freeware. (-I do not yet know if all 2nd order IIR filters can be called biquads. Have to look into that...) Anyways, based on the attenuation evaluated from the frequency response from both filters (8th and 4x2nd), the 8th order filter clearly was the better filter. It's attenuation was stronger and faster (rolloff rate greater). The 4x2nd structure did eventually outperform the attenuation of the 8th order filter, but only because the 8th order filter had reached its 16 bit attenuation floor. The 4x2nd order filter structure frequency response (attenuation) was most definitely NOT sharp! Stability ? Based on the pole enplacements of the 2nd order filter, the 2nd order filter if FAR more stable than the 8th order filter. Its poles are nowhere near the unit cercle's circumference. On the other hand, the 8th order filter poles are located nearer the unit cercle's circumference (than the 2nd order's poles), but I would not say that the poles are shadowing the unit cercle's circumference. Except for 2 of the 8 poles - they are located near to +j and -j. Nonetheless, the poles were eveluated using a 16 bit limited precision and consequently were displaced (at least I assume they were) from their infinite-precision-theoretical-locations. Thus, since all the poles were found ALL in the unit circle, the IIR filter should be stable. (I have a feeling I am leaving myself wide open for a finger-waggling session) Thus, my question is: Why are cascaded-biquad-structures preferred over non-composite higher order filters since the attenuation pays such a high price? for IIR filters, of course. Thx in advance -RogerArticle: 99230
The arguement for kings english was based in maners, and presented with hypocrisy. The lynching party took the maners banner, and then trolls with inflamatory name calling claims like "we feel offended by his imbecile spelling". I agree "Actually language is very important!" but it needs to be used with culturally time honored respect ... rather than berate younger posters with trolling like "If you prefer to use infantile spelling as it seems many recent younger posters do". I prefer civil butchering of our languange, far above perfectly constructed sentences laced with insults and attacks. When it comes to maners .... the first is at least very polite, and the second anything but. My mother did teach me that. One poster claims ... "Netiquete may have gone away in many groups, but it survives pretty well in most of the technical groups that you posted to that have any content value." I disagree. The concept of civil disagreement has been lost. What remains, are the personal attacks and name calling when the failure to articulate a rational debate is lost. We are not ever going to be of one opinion. We need to "agree to disagree" without these constant personal attacks.Article: 99231
Ray Andraka wrote: > Your responses so far > have mostly been whining about what you can't get rather than looking at > ways to get around those obstacles within the framework of what is > available. Posting it here and not listening to the advice the seasoned > veterans here have offered only serves to sour people on your ideas. The responses so far have been far from advise, they have been the stock answer that it's been tried before and fails. Advise to fail by failing to try. Advise is suggestions on how to move past prior failures, and get past the limitations of the existing tools.Article: 99232
Anyone remember him? Deja vu?Article: 99233
GaLaKtIkUs™ wrote: > Hi all, > Did some company already implemented G.709 OTU-2 on Virtex-4 using the > RocketIO? > In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is > 10.709. Should Virtex-4 be definitively excluded or are there some > tricks to achieve that challenge? I don't know about this protocol exactly, but for 10GBit Ethernet, which is a similar speed, you can use interfaces like XAUI (4x3.125Gbit) - if there is either a standard interface or a chip that could do this for you, then V4 could still be a contender. JeremyArticle: 99234
J Silverman wrote: > Hi All, > > Ok, you all kinda convinced me on this. After three days of searching for support software and not finding any, I started looking for another way of using a more modern FPGA. I was originally looking at the original Spartan (as they came in PLCC84 packaging) but cannot find any for sale in small quantities. So I started looking for ways on how to use a current FPGA in a breadboard, and I came across this site: > > <http://www.beldynsys.com/quadpacks.htm> > > They have a bunch of boards that will take SMT components and give you the ability to stick them in a breadboard. I was looking at the Q100-80 one and am wondering if that will work for a Spartan3 in VQ100 packaging. I'm not sure if the difference between VTQFP and TQFP is great enough to cause problems when trying to solder it on the board. > > Thanks, J Silverman You know, it's really a shame that there aren't more minimal "breadboard" adapters for FPGA's. The Xilinx sample pack was darn close, but had an odd shape, and not enough grounds. (that didn't stop me from mounting the peripheral connectors on the other side, and plugging it into a breadboard) Opal Kelly makes a decent "breadboard" style part, but it's $200 - does come with some nice software drivers, though. XESS also makes some breadboardable products as well. The real problem is that you practically have to have a PCB with fairly controlled trace lengths and properties to get modern bits working. The days of wire-wrap are virtually over, except for low-speed and non-critical analog. Keep in mind, even if you do manage to get a modern part on a breadboard or protoboard, you still have to power it. There are plenty of linear regulators to do the job, but virtually all of them are SMT (and flyspecks to top it off) It is a shame, though. I have some of those older parts in my drawer, and I hate to throw them out as well - even though I know I'll never build anything with a Xilinx XC3042...Article: 99235
I suggest you to use RAM inference instead, which is supported in ise7.1. You will find appropriate templates for all supported RAM types and modes in the XST user guide, section 2 (HDL coding techniques). best regards, ManuArticle: 99236
santhosh_h_98@yahoo.com skrev: > Guru's > > I want to take the RTL schematic generated by XST to LATEX doc. > Basically I need an .eps file. > > When I tried to copy the RTL schematic from XST and paste to MAYURA > DRAW > or TPX program, nothing gets copied. Can some kind soul helps in > getting .eps file for latex. > > Thanks in advance > Sant alt-printscreen and then paste in a drawing program should work but this is probably better: http://office.microsoft.com/en-au/assistance/HP062079971033.aspx any postscript printer driver should work -LasseArticle: 99237
radarman wrote: > It is a shame, though. I have some of those older parts in my drawer, > and I hate to throw them out as well - even though I know I'll never > build anything with a Xilinx XC3042... > Put them on ebay. Somebody might be able to use them for an existing product, provided they are still in the packaging.Article: 99238
Virtex4 uses RAMB16 instead of RAMB16_Sxx_Sxx. It is more convenient for parameterized blocks. A little bit more awkward for straight instancing. Pay attention to the addressing for different sizes, it may not be intuitive.Article: 99239
Roger Bourne wrote: >>Most IIR filters are constructed as cascaded biquads (and sometimes one >>first order section). The choice of the biquad structure has a >>significant impact on performance. > > > I compared an [8th order lowpass chebychev lowpass filter, 16-bit fixed > point] with [2nd order lowpass chebychev lowpass filter, 16 bit fixed > point, whose frequency I multiplied by 4 as to emulate a 4 > 2ndorder-cascaded-structure]. > I used WinFilter freeware. > (-I do not yet know if all 2nd order IIR filters can be called biquads. > Have to look into that...) > > Anyways, based on the attenuation evaluated from the frequency response > from both filters (8th and 4x2nd), the 8th order filter clearly was the > better filter. It's attenuation was stronger and faster (rolloff rate > greater). The 4x2nd structure did eventually outperform the attenuation > of the 8th order filter, but only because the 8th order filter had > reached its 16 bit attenuation floor. > The 4x2nd order filter structure frequency response (attenuation) was > most definitely NOT sharp! > > > Stability ? Based on the pole enplacements of the 2nd order filter, the > 2nd order filter if FAR more stable than the 8th order filter. Its > poles are nowhere near the unit cercle's circumference. On the other > hand, the 8th order filter poles are located nearer the unit cercle's > circumference (than the 2nd order's poles), but I would not say that > the poles are shadowing the unit cercle's circumference. Except for 2 > of the 8 poles - they are located near to +j and -j. Nonetheless, the > poles were eveluated using a 16 bit limited precision and consequently > were displaced (at least I assume they were) from their > infinite-precision-theoretical-locations. Thus, since all the poles > were found ALL in the unit circle, the IIR filter should be stable. > (I have a feeling I am leaving myself wide open for a finger-waggling > session) > > Thus, my question is: > Why are cascaded-biquad-structures preferred over non-composite higher > order filters since the attenuation pays such a high price? for IIR > filters, of course. > > > Thx in advance > -Roger > You misunderstood what was said. If you want to implement that 8th-order Chebychev filter you can choose several methods. You might think that the most sensible thing to do would be to implement it as an 8th-order direct form filter. If you did you would be wrong. Why? Because the pole locations of a filter are sensitive to the accuracy of the coefficients, and this sensitivity increases sharply as the filter order goes up. For a 1st-order filter the pole sensitivity is roughly equal to the precision of the coefficient, so a 1r15 coefficient will give you a pole that is no more than 2^-15 off from target. For a 2nd-order filter the pole sensitivity is roughly equal to the square root of the precision of the coefficient, so a 1r15 coefficient will give you a pole that could be off by as much as 0.006. Note that in some systems this amount of variation could make or break the system performance. Extend this to an 8th-order system and your 1r15 coefficient gives you poles that will wander by as much as 0.27 -- that's going to be a pretty useless filter! For pretty much the same reasons the accuracy requirements of your arithmetic goes up with filter order. So what you do is you take your filter and you break it into sections of no more than 2nd-order each. You implement each one of these individually, and cascade them. The transfer function of the cascade is the product of the individual transfer functions so you get the response that you need, but the accuracy requirements are no more than for 2nd-order sections, so you don't need to use an infinite number of bits to do your work. I have a pair of suggestions for you: First, hie thee down to a bookstore and get a copy of "Understanding Digital Signal Processing" by Richard G Lyons. It's a good book, and it's written for people who need to know the stuff without experiencing a lot of pain. This link will get you a copy: http://www.powells.com/partner/30696/biblio/0-13-108989-7. Second, think of posting (or cross-posting) questions like this to comp.dsp. Al and I both frequent that group; there are other's there (including Rick Lyons) who may have useful input. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 99240
It is good to the the venerable LM317, has some smarter offspring These new devices allow fine software control of Vcc, using either a small uC, or maybe the FPGA itself. ( Probably safer with a small uC ) So you can scale Vcc to suit frequency, or drop into the config-hold regions, or margin test your designs..... http://www.national.com/news/item/0,1735,1136,00.html -jgArticle: 99241
Hi,
I'm trying to do multiply-and-accumulate (MAC) in a custom IP created
by Create/Import IP peripherals in XPS. Xilinx provides basic
read/write functions with the user_logic vhdl code. I removed the code
for reg2 and reg3 in these two processes. I then added MUL_AND_ACCUM
process. I'm not a vhdl programmer, so I'm having difficulty with this
simple piece of logic. All I'm trying to do is
mul (reg3) = num1 (reg0) * num2 (reg1);
accum (reg2) = accum (reg2) + mul (reg3);
I wrote a process:
MUL_AND_ACCUM_PROC : process( Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
if slv_reg_write_select = "0010" then
slv_reg2 <= Bus2IP_Data(0 to 31);
else
slv_reg3 <= slv_reg0 * slv_Reg1;
slv_reg2 <= slv_reg2 + slv_reg3;
end if;
end if;
end if;
end process MUL_AND_ACCUM_PROC;
I suppose when I write a 0 to slv_reg2, it'll initialize slv_reg2 to 0.
Once it's initialized, I can simply write to slv_reg0 and slv_reg1, and
obtain the accumulated value in slv_reg2. But when I wrote a test
program in C to test this IP:
FPGA_MAC_mWriteReg(XPAR_FPGA_MAC_0_BASEADDR,0x8,3);
FPGA_MAC_mWriteReg(XPAR_FPGA_MAC_0_BASEADDR,0,8);
a = FPGA_MAC_mReadReg(XPAR_FPGA_MAC_0_BASEADDR,0);
printf("a: %d\n",a);
FPGA_MAC_mWriteReg(XPAR_FPGA_MAC_0_BASEADDR,0x4,4);
b = FPGA_MAC_mReadReg(XPAR_FPGA_MAC_0_BASEADDR,0x4);
printf("b: %d\n",b);
product = FPGA_MAC_mReadReg(XPAR_FPGA_MAC_0_BASEADDR,0xc);
printf("product = : %d\n",product);
output = FPGA_MAC_mReadReg(XPAR_FPGA_MAC_0_BASEADDR,0x8);
printf("output = : %d\n",output);
I have the following output:
a: 8
b: 4
product = : 1657088
output = : 32
a: 2
b: 5
product = : 12544852
output = : 10
It seems product and output are reversed somehow. It just doesn't work
as I expected. I can't figure out what's wrong with my code. I have
very little knowledge of vhdl. Can anyone point it out to me? The
following shows the read/write processes. Thanks.
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_select is
when "1000" => slv_reg0 <= Bus2IP_Data(0 to 31);
when "0100" => slv_reg1 <= Bus2IP_Data(0 to 31);
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1, slv_reg2, slv_reg3 ) is
begin
case slv_reg_read_select is
when "1000" => slv_ip2bus_data <= slv_reg0;
when "0100" => slv_ip2bus_data <= slv_reg1;
when "0010" => slv_ip2bus_data <= slv_reg2;
when "0001" => slv_ip2bus_data <= slv_reg3;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
Article: 99242Jim Granville wrote: > It is good to the the venerable LM317, has some smarter offspring Thanks Jim ... definately useful.Article: 99243
Thanks for the answer. This works but this has a big problem. Even if I have 2 AND gates in a design, when I export this as .eps file, using the method you mentioned, and insert in LATEX it takes one complete page. How can I copy just the part of the drawing as an .eps file ??? Please help. SantArticle: 99244
On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote: >Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : >"Payload compatible only"), so no hope for OTU-2 I think. >We have to wait Virtex-5 family ? No. That is unlikely to have sufficient jitter performance, due to certain compromises that must be made when putting an MGT on an FPGA. In particular, it's likely to use a ring oscillator rather than an LC oscillator which would have better perfomance. Use an external SERDES designed for G.707 / G.709 work. Note that (before they discontinued it) Xilinx's standalone SERDES didn't meet the SONET jitter requirements either, so getting these things to work is clearly not a trivial task. Regards, AllanArticle: 99245
Hi, I am interested in the algorithm too. By googling, the following address shows 16,700 articles. http://scholar.google.com/scholar?as_q=&num=100&btnG=Search+Scholar&as_epq=square+root&as_oq=&as_eq=&as_occt=title&as_sauthors=&as_publication=&as_ylo=2000&as_yhi=&as_allsubj=some&as_subj=eng&hl=en&lr= WengArticle: 99246
On Tue, 21 Mar 2006 16:30:27 -0500, Ray Andraka <ray@andraka.com> wrote: >Anyone remember him? Deja vu? How could I forget? The problem with trolls like Tisdale is that they don't realise they are trolls. Everyone else must be educated! My way is the only way, even though I have a minority viewpoin that isn't relevant to the other newsgroup users! I'm sure it relates to some childhood trauma. (joke) Blergh. AllanArticle: 99247
Erik Widding wrote:
> As this is a thinly veiled reference to my last post, I am going to
> treat it as directed at me, personnally.
Actually, I posted to the head article simply because it wasn't
directed at any one person. But you certainly choose to make it
personal.
> The bigger picture is this: you are a guest in this community.
The bigger picture is that YOU have never owned this forum, nor have
you ever been elected to speak for this forum. I was not the only
poster to object to the lack of respect of others actions and view
points regarding this matter. Your diatribe here in the form of direct
personal attacks is nothing more than classic trolling, by assuming
that you speak for the community in it's entirety, which has been
clearly demonstrated as false.
> We as a community ask that people make an effort to write in proper
> english, making a best effort to use proper spelling and grammar, be
> considerate of others, keep commercial postings to a minimum, etc.
And if that was truely your intent, that posters be considerate of
others, and commercial posting kept to minimum, then your angst should
be at yourselves, as the worst offenders in consideration are those
that mistakenly think they own it. YOU, John_H, Peter, Austin, and
several others, regulary insult anyone that dares to disagree with you.
In fact, each of you when challenged, ask people to leave, just to
protect your kingdom.
> We will defend our turf from those that do not show it the
> respect we ask for.
So anyone that doesn't bow before you is unwelcome .... I didn't see
that anywhere in the description of this groups founding principles, or
any usenet group since inception two and a half decades ago when I
first started participating on usenet.
> Ray's posts are always informative and well thought through.
Actually Ray's posts were not. I actually called him this afternoon and
we talked a while, and at the end of that talk I think we are on the
same page, or reasonably close.
The long and the short of it, we agree that all the major things I see
as RC needs are lacking, and there currently isn't any plan to provide
them, nor is their any simple short term solution path. But I'll let
you talk with Ray yourself.
If the experts can stop handwaving about what has failed in the past,
and start being objective about solution paths to explore, then maybe
your advise would be worth something. But people that whine about those
that are trying to forge past previous failures, really are just
obstructionists. NOT mentors.
> Not only do you lack the bigger picture understanding with much of the
> subject material that you chose to write on, you also seem to lack an
> understanding of who you are actually communicating with. So when you,
> as you did this afternoon, rip someone like Ray a new one, it sends an
> even more significant message: you not only don't have enough respect
> for this forum, you don't know enough about the subject matter to know
> who some of the strongest minds in the field are.
Stongest minds? I don't see you providing constructive advise toward
solutions, I just see you having a tantrum because someone else is
trying what others have failed at. I'm not the brightest kid on the
block, but an I'm persistant.
You do not deserve RESPECT when you freely trash others ... RESPECT is
earned, not bought, demanded, coerced, or extorted as you attempt.
Respect comes when you can learn to show respect at ALL times, with
patience and empathy. That YOU, Peter, John_H, and others just demand
it, is your falacy in your own self image as gods.
I chose the word bigot for a reason:
Bigot \Big"ot\, n. [F. bigot a bigot or hypocrite
1. A hypocrite; esp., a superstitious hypocrite. [Obs.]
[1913 Webster]
2. A person who regards his own faith and views in matters of
religion as unquestionably right, and any belief or
opinion opposed to or differing from them as unreasonable
or wicked. In an extended sense, a person who is
intolerant of opinions which conflict with his own, as in
politics or morals; one obstinately and blindly devoted to
his own church, party, belief, or opinion.
[1913 Webster]
Note the "intolerant of opinions which conflict with his own", as you,
Peter, John_H and others demand that your views are the one and only
acceptable view in this forum.
As you lack the capacity to discuss others view point, and simply
demand that they accept yours. You lack the ability to discuss issues,
you demand yours. You lack the ability to even debate issues on the
merits of each others view points, as when you feel threatened, it's an
all out session of ridicule and personal attack.
Get over yourself.
> I have read as you have been given sensible information by many in this
> group that reflects years of practical experience with FPGAs, silicon
> fabrication and test, partial reconfiguration and place and route, and
> stood back in utter disbelief as you couldn't be bothered to digest
> this information and allow it to sculpt your view in the least. You
> simply defend your original view, or one that is simply contrary to the
> masses, and keep arguing.
Sensible? get real. I've been told what doesn't work, as fact, not a
discussion point of why with consideration that maybe things have since
changed, and today there is a solution, that didn't exist 5 years go,
or 20 years ago, when the last failure occured.
I'm equally at that point. For reconfigurable computing .... IE using
FPGAs as computing engines for arbitrary programs and netlists ....
nearly everything is broken. There is NO discussion about getting this
fixed, or pointers to things that would provide fast dynamic place and
route on Xilinx FPGAs today ... NOR tomarrow.
I'm sure that each of you have very valid reasons for wanting expensive
zero defect FPGA's. That doesn't give you the right to start insulting
me and argueing why my vision of RC with defect management isn't right
for my application. In fact, the posters here have a lot of lame
execuses why that is bad for me, but NO ONE has objectively constructed
a clear case for why it would be bad for FPGA based computers.
> Mr. John Bass, fpga_toys, you are what is wrong with our community.
> Welcome to my witch trial. This forum existed for ten years before you
> got here, and it will exist for many more after you get bored and leave
> to torment another community.
No Eric, YOU and your fellow self proclaimed GODS are what is wrong
with OUR community, as it is NOT YOURS. And you are right ... it is a
witch trial, just as flawed as every other witch trial in history. And
this forum will most likely exist long after YOU are gone.
>
> Actually, as you seem to be a rather intelligent individual, that might
> be able to become a member of this community I respectfully ask that
The right to post here is NOT subject to your permission.
> you drop the devil's advocate role and leave it for those that have
> spent more time in our community and more than a few days in our
You don't even have a clue.
> Xilinx wants to sell chips.
That is great .... They also currently want to put many in the trash,
because of an out dated zero defect policy. I don't think that you
speak for Xilinx, but you sure seem to claim to.
> This post is the extent of the help that I am likely to offer you, as
> you have royally pissed me off. Maybe some of the others will
> eventually be more charitable.
Your Royality worked himself into a frenzy because this is an open
forum, and not subject to your rule.
When you and your cronies learn that it is NOT your right to call
others imbecile, infantile, fools, and the other many insults here, and
you start actually being constructive, rather than intentionally
distructive, then you might, just might once again earn the right and
respect as a peer, in a peer forum.
Till then, I WILL stay here and challenge your flagrant assertion you
are the GODS of this forum, each and every time you violate another
poster RIGHT to be treated fairly and respectifuly with your arrogant
self proclaim right to dis others here as you please.
If you wish to be a bigot, and irrationally force your views on others
without the right of discussion or free and open debate, then I will
continue to remind you just what a bigot is. I will remind you of what
and who the real imbecile is here.
Article: 99248What's the betting that Antti is the first to get this going on an FPGA? Though I imagine it is huge when synthesized... Pablo Bleyer Kocik wrote: > For those who are interested, SUN released Open SPARC today: > > http://opensparc-t1.sunsource.net/download_hw.html > > Verilog RTL, verification and simulation tools included. > > Cheers. > > -- > PabloBleyerKocik /"Person who say it cannot be done > pablo / should not interrupt person doing it." > @bleyer.org / -- Chinese proverbArticle: 99249
John McGrath wrote: > What's the betting that Antti is the first to get this going on an > FPGA? > Though I imagine it is huge when synthesized... Has anyone seen Sizes / and MHz for this, finally sitting in a FPGA ? How does it compare with Leon ? -jg > > Pablo Bleyer Kocik wrote: > >>For those who are interested, SUN released Open SPARC today: >> >> http://opensparc-t1.sunsource.net/download_hw.html
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