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Ben, if you can afford to use a small amount of analogue circuitry around your fpga, i suggest you use a second 1000010.0 Hz oscillator (this can be a "detuned" 1 MHz oscillator) and mix the received signal with this this oscillator down to the audio domain using a double balanced mixer. A lowpass filter (or better a so called diplexer) must be used at the IF port of the mixer. The frequency variation in the downmixed signal stays the same, so with this arrangement you have shifted the scenario from 1 MHz, where a 5 Hz variation is a difficult to detect 5*10E-6 effect to a 10 Hz audio signal where 5 Hz variation is a easy to detect 50 % effect. This scheme is the usual one for comparing ultra stable oscillators against each other, where variations smaller by some orders of magnitude have to be measured. No matter what scheme you will use: Keep in mind that a "normal" x-tal oscillator has a tempco of app. 1*10E-6/K. So a normal x-tal oscillator will give you a 1 Hz variation per Kelvin @ 1MHz, well in the region of the Doppler that you want to measure. This is a indication that a "better" oscillator has to be used. Don't go for a TCXO, look out for a cheap OCXO. Rgegards Ulrich Bangert "Ben Marpe" <Ben.Marpe@gmx.de> schrieb im Newsbeitrag news:1137597178.426492.225110@z14g2000cwz.googlegroups.com... > Dear experts in this newsgroup, > > in my diploma thesis i'm using a FPGA for baseband signal generation. > I'm interested in generating and varying a clock of 1Mhz which is > DOPPLER shifted +/- 5Hz due to movements between receiver and > transmitter. > > The +/- 5Hz Doppler must be applied in a very "smooth" way, the step > resolution should be as fine as possible. > > Any ideas how to do this on a (Xilinx) FPGA ? > The sine output of Xilinx LogiCore DDS isn't necessary and the step > resolution might be even a little bit finer for my application. > > Thanks a lot for every single hint you can give to me ! > > Greetings, BEN >Article: 94901
Petter Gustad <newsmailcomp6@gustad.com> writes: > I can't find out how to play XSVF files in batch mode, there is a > play command but it does not seem to take a filename as an argument. The solution was to use addDevice to add the file and then use play: setMode -bscan setCable -port lpt1 addDevice -p 1 -part file.xsvf play quit Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 94902
Hi, I am working on an ML403 with virtex4 FX12 and ISE7.1i.3 and EDK7.1i.2. I would like to use profiling on the powerpc and there is a problem during linking (the ld program fails saying there is a problem with connect2). The error message is about a file that would be truncated !?!? I use the PIT of the virtex4 as a counter and I have set the option for profiling in the SW platform settings. I used the same (almost) options for microblaze and the generation and use of profiling was just fine. Does anyone have a clue ? Best regards, JFArticle: 94903
"Carl Smith" <cdsmith69NOSPAM@gmail.com> schrieb im Newsbeitrag news:MPG.1e38bfdf3eafc9fc98968a@news.west.earthlink.net... > > OK, I just have to vent a bit. > > I am laying out a board with an XC9536. The schematic capture > program I am using is a major program, not some fly by night > outfit. They claim their component library is done by an ISO > 9000 organization. > > So my perfectionist tendencies didn't like the fact that they > used a different font for the pin names on the XC9536 schematic > symbol than they usually do in the libraries. I went into the > "Library Executive" to change the font and when I went to save > the part the program told me that the pin numbers in the > component pin list didn't match what was entered into the > schematic capture symbol. > > So I checked the XC9536 data sheet and found out that their pin > numbers for the schematic symbol were ALL WRONG. I had to spend > about half an hour relabeling all the pins, and then moving > things around to make it look nice again. > > So if I hadn't decided to change that font, I could have done a > board layout with all the pins connected wrong. > > I'm starting to think it would be better if board layout > programs just shipped with no pre-made components. I just end > up fixing things on nearly every single part I use anyway. > Sometimes I think it would be better if I just did it all > myself. > my trust in CAD programs to be accurate is: 0% the schematic libraries are wrong the PCB components pads are wrong, etc.. always check ALL pin mapping in schematic libs, and the PCB symbols as well, you may end up re-doing both of them !! after having a wrong PCB symbol in PADS i never ever again trust blindly any pre-made CAD library components -- Antti Lukats http://www.xilant.comArticle: 94904
Incorrect footprints can also be very annoying, that has caught me out once or twice. LeonArticle: 94905
Hello, Thanks for your answer and advices. What you describe is pretty much like what I have planned to do, just not to say this is what I wanted to do !! Stéphane. "Gabor" <gabor@alacron.com> a écrit dans le message de news: 1137626090.900239.283190@g47g2000cwa.googlegroups.com... Stéphane, I do similar designs to this (framegrabber cards) and haven't found a ready-made SDRAM FIFO, although I haven't looked in a long time since rolling my own many designs ago. I think that getting good performance from SDRAM in this situation involves tuning the burst accesses to allow continuous use of the data bus when not changing direction between read and write. Peter was on the right track with the read / write ping-pong machine, but for SDRAM you need to read multiple words / write multiple words to get any sort of performance. A design I re-use frequently has a constant 21-cycle loop in which 16 of the cycles are used for either read or write (not both) during one loop. Un-needed loops are replaced by a 21-cycle NOP and auto refresh. Start-up code counts refresh loops until 8 refreshes occur and then sets the mode register. For simplicity, the address pins are reset to the state required for the mode register set (MRS) and not clock enabled until the MRS has completed. This reduces the gate depth of the address mux. I have a simple "arbiter" that decides what to do with the next 21 clock cycles (read, write, or refresh). To reduce power on some designs I only refresh if a refresh timer has expired, then unused 21-clock loops are just completely NOP'd. Memories are set for burst length of 4 and one burst of 4 words is sent to each bank (thus overlapping data and control cycles). Think of the bank address as the least significant address bits. For better throughput you can increase the loop length and each additional 16 cycles would add 16 more memory accesses (e.g. 32 accesses in a 37-cycle loop). The basic element going in or out of this "FIFO" is then a burst of 16 words (think of this as your FIFO width if you will. Generally I use a COREgen FIFO to buffer up data at both ends of the SDRAM to deal with asynchronous data rates and differing byte widths on input and output. The whole design is remarkably small, but as I said I haven't seen such a design made generally available. Good luck, Gabor sjulhes wrote: > Hello, > > The goal is not to create delay but to handle the fact the 32 bits / 33 Mhz > bus is not always available. > > For the SDRAM controller I already have my solution in mind. > > I was only wondering if this function ( huge FIFO for FPGA using an external > SDRAM ) ,which i'm shure a lot of people would need, would already exist and > be available. > > Stéphane. > > "Peter Alfke" <peter@xilinx.com> a écrit dans le message de news: > 1137514850.769502.197970@f14g2000cwb.googlegroups.com... > > Give more details: > > depth, width, clock rate for write and for read. Asynchronous clocks? > > Peter Alfke, Xilinx > >Article: 94906
> Yes, that's the point of uCLinux, to support machines > that have a flat address space. >> I had to deal with this kind of problems in vxWorks days, it was >> a nightmare. > >Me too, man. I don't think the problem is the shape of the address space, it's the read/write protection and a user/system mode bit. I've written a lot of code that ran without memory protection and we didn't have any serious problems. The trick is to use a compiler with (very) strong type checking and that excludes pointer arithmetic. That catches almost all the memory smashing type bugs at compile time. Much easier to find/fix them that way. I remember my early days with type checking. I was writing code without really understanding what was going on. One night the compiler slapped my wrist because I had forgotten a layer of indirection and I (finally) figured out what was going on. "Thank you, thank you, thank you" oh compiler. That would have been a real pain to debug. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94907
>So if I hadn't decided to change that font, I could have done a >board layout with all the pins connected wrong. I never trust anything direct from the vendor library. I keep my own set of libraries. When I need a new part, I often start with pieces I find in the vendor libraries, but everything gets checked. It's generally sane to get a friend to double check things. It's too easy to fool yourself. Most of the time, you can do a layer of sanity checking at the board layout stage. You wired signal-foo up to pin 98 because it's in the top right corner... or you swapped signals foo and bar because that made the board easier to route. After they have been used on a board with no problems I become more trusting. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94908
>Incorrect footprints can also be very annoying, that has caught me out >once or twice. My straw man is to print the gerber layer out 1:1 and see if the part fits cleanly. You may have to tweak the scale factor to get things to print at the right size. Check the board outline with a ruler or something like that. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 94909
"Ulrich Bangert" <df6jb@ulrich-bangert.de> wrote in message news:dqndk9$8g0$01$1@news.t-online.com... > > No matter what scheme you will use: Keep in mind that a "normal" x-tal > oscillator has a tempco of app. 1*10E-6/K. So a normal x-tal oscillator > will > give you a 1 Hz variation per Kelvin @ 1MHz, well in the region of the > Doppler that you want to measure. This is a indication that a "better" > oscillator has to be used. Don't go for a TCXO, look out for a cheap OCXO. > > Rgegards > > Ulrich Bangert > OF COURSE, use an ordinary XTAL and control its temperature with the FPGA. Perhaps some pins driving resistors stuck to the XTAL case? Some other pin driving a servo controlled can of freezer spray? If Ulrich's figures are correct, +/- 5K gets you what you want! :-) Cheers, Syms.Article: 94910
The CCLK pin goes High-Z after configuration and this lets me use the signal put in parallel to work with the same DSP input, what about the DONE pin? It seems I can't I convert it to High-Z too, right? ThanksArticle: 94911
On 2006-01-18, Phil Tomson <ptkwt@aracnet.com> wrote: > Thanks for the info. what Linux distro are you running? > > The drivers you referred to: linuxdrivers2.6.tar.gz was that something you had > to download from Xilinx's site? I'm using Suse 9.3. The linuxdriver2.6.tar.gz information is found in answer record 22648. /AndreasArticle: 94912
hi joey,
> When you say "when i try to open the file i am not able to", what
> happens?
the function returns -1 indicating failure to open the file.
>How are you opening the files?
using the mfs_file_open("src.mnt", MFS_MODE_READ);
>What flags are you using to generate image.mfs?
$ mfsgen -cvbfs imagemnt.mfs 30 mnt
mfsgen
Xilinx EDK 7.1.2 EDK_H.12.5.1
Copyright (c) 2004 Xilinx, Inc. All rights reserved.
mnt:
des.mnt 3072
src.mnt 3072
MFS block usage (used / free / total) =3D 14 / 16 / 30
Size of memory is 15960 bytes
Block size is 532
mfsgen done!
> Are you using a PPC or microblaze?
PPC
> One more thing to try is sticking a small (few chars) txt file in your
> file system and see if you can peek at it with XMD to see the correct
> values.
created dow.txt with the content "dow TestApp_Memory/executable.elf"
then created the imagefile as below
$ mfsgen -cvbfs dummy.mfs 30 mnt
mfsgen
Xilinx EDK 7.1.2 EDK_H.12.5.1
Copyright (c) 2004 Xilinx, Inc. All rights reserved.
mnt:
dow.txt 35
MFS block usage (used / free / total) =3D 3 / 27 / 30
Size of memory is 15960 bytes
Block size is 532
mfsgen done!
and then downloaded the image
dow -data dummy.mfs 0x22000000
and then read back the value at 0x22000000 thru XMD as below
XMD% mrd 0x22000000 35 b
22000000: 4D M
22000001: 46 F
22000002: 53 S
22000003: 32 2
22000004: 00
22000005: 00
22000006: 00
22000007: 00
22000008: 02 =E2=98=BB
22000009: 00
2200000A: 00
2200000B: 00
2200000C: 00
2200000D: 00
2200000E: 00
2200000F: 00
22000010: 00
22000011: 00
22000012: 00
22000013: 00
22000014: 00
22000015: 00
22000016: 00
22000017: 00
22000018: 03 =E2=99=A5
22000019: 00
2200001A: 00
2200001B: 00
2200001C: 2E .
2200001D: 2E .
2200001E: 00
2200001F: 00
22000020: 00
22000021: 00
22000022: 00
the contents doesn't map to the contents of the file dow.txt
thanx for your patience and help.
Rajashekar
Joseph wrote:
> When you say "when i try to open the file i am not able to", what
> happens? How are you opening the files? What flags are you using to
> generate image.mfs? It may be necessary to use the -s flag (see Answer
> Record:19867 on the xilinx site). That flag switches the endianess.
>
> Are you using a PPC or microblaze? My only experience is with the PPC.
>
> One more thing to try is sticking a small (few chars) txt file in your
> file system and see if you can peek at it with XMD to see the correct
> values.
>
> Let me know how it goes... I know it took me a while to get my file
> system working like I wanted it to.
>=20
> Joey
Article: 94913"Carl Smith" <cdsmith69NOSPAM@gmail.com> wrote in message news:MPG.1e38bfdf3eafc9fc98968a@news.west.earthlink.net... > OK, I just have to vent a bit. > > I'm starting to think it would be better if board layout > programs just shipped with no pre-made components. I just end > up fixing things on nearly every single part I use anyway. > Sometimes I think it would be better if I just did it all > myself. If I need a new component I don't even check to see if it's available, I do it myself and get it reviewed. That way you know it's definitely right (probably). Nial ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 94914
"Phil Tomson" <ptkwt@aracnet.com> wrote in message news:dqnd2611rjo@enews1.newsguy.com... > If I understand correctly, I only need the driver if I want to be able to > program the FPGA through the PCI - is that a correct assumption? No, in Windows at least you need a driver installed or the OS won't let you access the board. This is all decided when the OS boots up. From what I understand in Linux you can install/remove drivers on the fly (you might be able to do this in Windows if you know what you're doing). > Sounds good (if I could program the FPGA through the PCI bus, that would be > great, but it's not absolutely needed I think). I don't know about the Xilinx config devices that John uses for Raggedstone, but I can do this with Cyclone's and EPCS4's with my boards/PCI core. (Note I'm not set up to sell boards in volume, this isn't an ad for boards). Nial ------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 94915
When I had to interface an Altera device to an ADSP-2187, I simply bit-banged the configuration into the FPGA., rather than use the SPORT. The latter was also needed for data transfer, and it seemed easier to do it that way. LeonArticle: 94916
Hi, i tried to install it on a Debian Sarge with a 2.6.12 kernel but without success. It complained about a missing libqt_qt.so (or similar). Which packages are missing? Thanks in advance. Thomas "Dan" <mekmon@gmail.com> schrieb im Newsbeitrag news:1137628581.049694.49240@g49g2000cwa.googlegroups.com... >> * Impact does not work out of the box with kernel >> version 2.6.15.1. I had to download linuxdrivers2.6.tar.gz >> and compile it. Furthermore, I had to edit the configure >> script in windrvr and make sure that UDEV was not used. >> (The udev interface seems to have changed in later 2.6.x >> series. The relevant symbols are also GPL-only now, so I don't >> think a binary only module can be distributed using UDEV in later >> 2.6.x kernels.) > I wrestled similarly with windrvr. It apparently uses some class_simple > functions removed Jun. 20 2005. I subscribe to the LKML and was easily > able to reverse patch it. > > Project manager and some other window were converted to QT I think. All > other windows use the hideous WindU lib, so you can start the ise > executable without fooling with DISPLAY but you still need it set to > ":0" for all those secondary programs. Other than the subpar hotkey > junk, the interface is much more natural. > > Everything much more usable now. (Gentoo, 2.6.14-gentoo-r4 w/ > class_simple unpatch, WebPack 8.1, Spartan-3 starter kit w/ parallel > cable III). >Article: 94917
Leon, sorry, could you explain me more in detail what you've done? ThanksArticle: 94918
Yes jpdull, that's what I thought, and this was the instantation of my component: i_br_clk_out_BUFGMUX : BUFGMUX_1 port map(O => br_clk_out, I0 => dsp_clk_a, I1 => zero, S => o_BR.output_nTri); I replaced it with the following (as suggested by Syms): i_br_clk_out_BUFGMUX : FDDRCPE port map( Q => br_clk_out, C0 => dsp_clk_a, C1 => not(dsp_clk_a), CE => o_BR.output_nTri, CLR => rst, D0 => '1', D1 => '0', PRE => zero ); Now it detects dsp_clk_a as a global clock using dedicated clock lines. How can we explain that? JL.Article: 94919
Sorry, I didn't mention that you'll find the aforementioned option in Xilinx FPGA Editor.Article: 94920
I agree, my trust in the pre packaged libraries is 0%. I always use a datasheet and enter the symbol and footprint patterns and then I like to double check it the part against a 1:1 print.Article: 94921
Piotr Wyderski wrote: > Now the SMD components in TQFP/SO/TSSOP are no longer a > problem. But we still don't know how to solder BGAs and QFNs... I showed my homebrew club how to reball and attach Xilinx BG560's here in my wifes digital convection oven well over a year ago. It takes a small amount of practice, which gets manageable when you also are willing to bake and reball. There are lots of trash FPGA's to be had on boards for a few dollars, and Solderquik preforms make reballing easy. KISS projects can frequently be pulled off with double sided boards, which are cheap from a number of sources. If doing BGA, they need to be solder mask over bare copper (SMOBC) to prevent the balls from wicking under the mask. There should not be ANY expensive home project from a parts perspective, as recycling motherboards, industrial boards, disk drives, graphics cards, etc are a wealth of nearly zero cost parts. Design with what you can salvage, and that is a lot. I strongly suggest forming a home brew club locally, or even across the net, and pooling designs onto a PCB panel ... especially when 4, 6, and 8 layer projects are needed. Most of the budget pcb shops refused panelled designs, but you can lower your individual costs by sharing NRE's and setup charges across 3-10 project boards on the same panel. Just be sure that you can cut them apart :) > Hmm, really? ;-) As far as I know the only "pure" hobbyists > here are Antti and myself, the rest is more or less professional. I'm pretty sure there are a LOT more than just a few of us. I made PCB's in high school (1967) with masking tape for resist, and stoped making them at home when the pcb program showed up for my MacIntosh 128 from Douglas Electronics. I even stopped wirewrapping about that time because it was just quicker and easier to turn one PCB with data paths and most control paths in place, and finish the design with point to point wiring and PAL's. My first BIG hobby project was a Z80 based 9-track tape formatter for the TMS100 tape drive I had on my LSI11/23 Unix home computer, which I had to go buy a TRS-80 to write the firmware for. My current home computer project is a couple thousand FPGA home super computer, which I've been working toward for a couple years now, mostly because I like big fast computers, it's one hell of a challenge, and I needed retraining in building state of the art computer systems after being a Unix systems programmer for too many years. I do knock off flat fee contract hardware and software designs from time to time, and I'm also currently looking for projects. I will also be turning some of the smaller spare fpga's from my home computer project into low cost student boards - using environmentally friendly recycled parts. JohnArticle: 94922
prav wrote: > Hi all, > > I have got a doubt in PCI arbiter operation . > Assume that a particular device issues a REQ(REQ0) and GRANT(GRANT 0) > is issued to that particular deivce , that device pulls the FRAME > signal low indicating it is using th PCI bus.Now during the entire > duration for which the FRAME signal is low GRANT(GRANT 0) should be > held low for that particular device. > > My doubt is if in the FRAME low held duration if any other device > issues a REQ (i.e pulls it low and again pulls it high before the FRAME > has gone high.IS this a valid request OR does the REQ line need to be > held until the GRANT is issued to that particular device. > > Thanks in advance, > Praveen The PCI 2.3 spec says REQ# can be de-asserted at any time. The situation you mention is not typical, but allowed. Because of this, the arbiter needs to deal with it. Specifically if the arbiter issues a GNT# to a master that has de- asserted its REQ#, it should de-assert GNT# and allow other masters to use the bus. In fact even if a master doesn't de-assert REQ# , but fails to assert FRAME# within 16 clock cycles of the bus becoming idle, the arbiter should de-assert that master's GNT#. The arbiter may in this situation ignore further requests from the "broken" master. This is all described in section 3.4.1 of the spec. Hope this helps, GaborArticle: 94923
Piotr Wyderski wrote: > But they do not provide free simulators, so they are virtually useless for > hobbyists. I should probably add that Steve's Icarus Verilog (IV) solves that problem in the low cost open source tools department. And it works well targeting fairly good sized XC4K's and Spartan chips which are easy to design with since they only require a 3.3V supply. Pick off an older Seagate drive, and you will have a dual 1a linear regulator, 2MB SDRAM, EEPROM with boot sector, cap's, and a few other parts to build an interesting robot controller, stomp box effects processor, home controller, or other project with a 5V recycled wall wart. And FpgaC for open source reconfigurable computing (read executing C code as circuits) is getting off the ground to do the same for C coders not interested in learning VHDL/Verilog as their only way to program fpgas. You will find both FpgaC and IV on sourceforge.Article: 94924
Ray Andraka wrote: > I'm not sure I see what the big push for having bitstream access is. > I've yet to see a compelling need for it that is not addressed by the > existing tools (there is always XDL if you really want to bit bang). > The only reason that seems to surface is to allow outside parties to > develop their own place and route tools. Frankly, I don't think the > complexity of modern FPGAs is such that this type of undertaking can > improve on or even compete with the free place and route tools already > offered by the FPGA vendors in the timeframe between device introduction > and obsolescence. Anyway, for those hadry enough to try, as I said, the > XDL tools do give you enough access to every step of the design flow to > allow you to play with any step you feel compelled to play with. Actually, I would like to compile, load and go fair sized algorithms without having to spend hours in place and route. I would also like to dynamically link library elements on the fly without having to do a xilinx style design partition. But these are what software guys want using FPGA's as computers. I'm willing to constrain the compiler into bin sorting logic blocks into acceptable clock domains, and cross clock domain synchronize when the execution switches clock domains. I'm pretty sure that the compiler can generate logic blocks in RPM's that will have reasonable performance for testing, and would be just happy as a lark if I didn't have to wait for place and route till a project was completely done. It comes down to the difference between hardware guys needing to optimize cycle times for production needs, and software guys just wanting something that will work for testing - two very different ends of the spectrum. I would be very happy with place and route tools that I could give a polygon constraint, and a few interconnect points to the existing design, and have it return and xor'able bit stream referenced to a null design for the polygon that i could load on demand. Oh, and it would be really cool, IE necessary, to do that in under a second or two, preferably milliseconds. When there is an fpga vendor that can support partial reconfiguration on the fly with dynamic linking of modules with times in the microseconds or milliseconds then we will see reconfigurable computing go main stream big time. Right now it still feels like compiling my 1401 programs with an N-Pass card deck compiler to punched cards. The level of reconfigurability and the granularity of the tools is completely bent toward hardware design processes .... some of us would like a LOT more.
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