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Sounds good. Thanks a lot for the info, John. -TonyArticle: 94726
Hi Weng, In the XST Properties under the Xilinx Specific Options you find "Pack I/O Registers into IOBs". The default value is Auto. Maybe setting it to Yes improves the synthesis result. Also, as mentioned before by Michael Rhotert, you may disable the "Equivalent Register Removal" option. Also you should check if your CLK66M can be routed to the IOBs. Is it on a global clock net? Have a nice synthesis EilertArticle: 94727
Hi , I have got a basic doubt in PCI arbiter regarding the GRANT signal of the PCI arbiter. When exactly should the PCI arbiter remove the GRANT signal of a particular device , is it totally dependent on the REQ signal of that particular device or does it also depend on FRAME and IRDY. Thanks in advance . Regards, PraveenArticle: 94728
"Drily Lit Raga" <midicad2001@yahoo.com> schrieb im Newsbeitrag news:1137474383.369314.144310@g43g2000cwa.googlegroups.com... > As I mentioned in another thread, I received a project from a > consultant who supplied the design files, in fact everything. I'm > thinking there MUST be a way to simply program the device (XC95144XL) > from the JEDEC file, but after rummaging around for an hour I could NOT > figure this out! > > Am I missing something besides my brain? No, your brain is OK. when I first tested ISE 8.1 it took me exactly 3 minutes to crash-self termination fatal error. PLD programming in Impact 8.1 seems to be disable, you can only erase and verify, not program the device, this is now added to our public Xilinx bug tracking database as bug #1: http://bugs.xilant.com/view.php?id=1 this may be fixed in SP1, but I can not test with SP1 as Xilinx website has problems at the monent. So far the solution for you is to install ISE 7.1 or older in order to program your PLD -- Antti Lukats http://www.xilant.comArticle: 94729
Tobias Weingartner schrieb: >>so there are reasons for keeping the bitstream non public. > I happen to disagree. We are all entitled to our opinions of course. > If the vendors would have a well defined format to "compile" to, and > a good library/port for a program to be able to take this format and > then generate a bitstream, that would be a start. Note, I'd want to > have the source available to be so that I could port this last bit of > "technology" to my favourite OS (by choice or necessity). > > I can't believe that these things are anything but simple portable ANSI > C (or some derivative)... JBits is a solution to all this. Maybe not a particulary good one, but you can read, modify, write bitstreams in a platform independant way. There is no source code available, but java bytecode that you can essentially call by any language you want on any platform you want. There are even people at xilinx working on a virtual file system to mount and modify the configuration of a virtex-4 by the embedded PowerPC. Kolja SulimmaArticle: 94730
On 17 Jan 2006 00:18:42 -0800, "prav" <praveen.kantharajapura@gmail.com> wrote: >Hi , > >I have got a basic doubt in PCI arbiter regarding the GRANT signal of >the PCI arbiter. >When exactly should the PCI arbiter remove the GRANT signal of a >particular device , is it totally dependent on the REQ signal of that >particular device or does it also depend on FRAME and IRDY. > >Thanks in advance . > >Regards, >Praveen According to PCI 2.1, grant should be removed when FRAME is asserted. Best regards ZaraArticle: 94731
Drily Lit Raga <midicad2001@yahoo.com> wrote: > Got a project from a consultant using ISE 4.1 but of course the latest > download is 8.1. > If it matters, target device is XC95144-XL. > There is no obvious way to open this older project. Oddly, ISE doesn't > seem to create ANY file associations in Windows. > I do have all of the original pieces from 4.1, but it's not clear to me > which of these are critical input and which are output, log, or > intermediate files. Xilinix has a library of old ISE versions to download. Look araound... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94732
Joseph,
You could try to insert Chipscope into your design. Chipscope is
like a logic analyzer you insert into the FPGA. I think if you capture
a waveform during an anomalous XMD poke/peek sequence, it would shed
light on the problem. I think a 60 day evaluation comes with the EDK
CD.
-Newman
Article: 94733Adam Elbirt wrote: > Is there any way to get gate counts for a Quartus implemented design? I > know Xilinx will give gate counts out of place and route but I can't > seem to figure out anything other than LUT counts and logic element > usage from Quartus. In the report window, click the 'Fitter' item, then select the "Resource usage" item. Best regards, BenArticle: 94734
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dqia3e$p9n$01$1@news.t-online.com... > "Drily Lit Raga" <midicad2001@yahoo.com> schrieb im Newsbeitrag > news:1137474383.369314.144310@g43g2000cwa.googlegroups.com... >> As I mentioned in another thread, I received a project from a >> consultant who supplied the design files, in fact everything. I'm >> thinking there MUST be a way to simply program the device (XC95144XL) >> from the JEDEC file, but after rummaging around for an hour I could NOT >> figure this out! >> >> Am I missing something besides my brain? > > No, your brain is OK. > > when I first tested ISE 8.1 it took me exactly 3 minutes to crash-self > termination fatal error. > > PLD programming in Impact 8.1 seems to be disable, you can only erase and > verify, not program the device, this is now added to our public Xilinx bug > tracking database as bug #1: > > http://bugs.xilant.com/view.php?id=1 > > this may be fixed in SP1, but I can not test with SP1 as Xilinx website > has problems at the monent. > workaround available (tested with 8.1 SP1) device programming is possible by double clicking on impact processe-program this brings up programming options, now clicking on OK will launch device programming main menu-operations-programming remains DISABLED and popup menu for device operations still does not have program menu item so the bug is still but there is a workaround (I also updated bug botes in our bugtracking database to reflect this workaround) -- Antti Lukats http://www.xilant.comArticle: 94735
Hello, We need to implement a FIFO using an SDRAM within a V2PRO. I guess this function already exists, so does someone has links, information.... ??? Thank you Stéphane.Article: 94736
"Scott & Brenda Burris" <slburris@earthlink.net> wrote in message news:MPG.1e35a2bc8d29b5c7989680@news.west.earthlink.net... > I'm also one of those rebirth hobbyists. > > I was a hobbyist up until the mid to late 80's. Probably the most > ambitious stuff I tried was a 68020 board with dynamic ram, running at > 16Mhz, all on a big wire-wrap board. Back then, the board was stuffed > with LSTTL chips. The board was none too reliable -- flex it the wrong > way, and something broke. But on a good day, it worked. > Scott, I'm genuinely surprised. In my experience, wire-wrap boards were the most reliable boards I've ever had. Especially if you took the time to train the technician how to wire-wrap properly. The hardest point was trying to stop them grouping the wires together into "crosstalk-of-death" busses instead of just connecting them point-to-point. Second hardest was banging into their heads to connect multi-drop traces every other section first, so you can rip up and re-route easier later on. Happy days! Cheers, Syms.Article: 94737
rk ha escrito: > On 16 Jan 2006 01:15:40 -0800, "al82" wrote: > > > > >> > >> Some info in this presentation particularly with respect to long-life > >> critical systems. > >> > > > >Don't worry. > > > >Military electronics is not covered by the RoHS directive. ;-) > > Airbus. Most of the Airbus electronics is not covered by the RoHS directive either. Only the communications equipment (and I'm not sure). The list of categories that the RoHS applies to is: Categories of electrical and electronic equipment covered by Directive 2002/95/EC 1. Large household appliances 2. Small household appliances 3. IT and telecommunications equipment 4. Consumer equipment 5. Lighting equipment 6. Electrical and electronic tools (with the exception of large-scale stationary industrial tools) 7. Toys, leisure and sports equipment 10. Automatic dispensers Categories 8 and 9 : 8. Medical devices (with the exception of all implanted and infected products) 9. Monitoring and control instruments are covered by Directive 2002/96/EC but not by 2002/95/EC (RoHS)Article: 94738
Hi I wonder if anyone (Xilinx?) has actual information on Spartan3e fabric speeds? I have done some actual measurements and as far of the results the LUT propagation delay seems to be about 10% bigger than in S3? This info seems to be obmitted in Spartan3e datasheets. Oh well, it looks like will have to rely on our measurements when the manufacturer does not publish the timing info. I was hoping to see a little speed improvment so seeing 10% decrease was a small surprise. Well I have not tested all the S3e I have yet maybe other parts are actually faster than the one used for LUT speed testing. -- Antti Lukats http://www.xilant.comArticle: 94739
John Williams wrote: > Hi Tony, > > tony.p.lee@gmail.com wrote: > >> Is it true that uCLinux does not have protected kernel memory? >> A simple programming loop index comparision error can wipe out the >> system memory including kernel. > > Yes, that's true. The "uC" in uClinux implies no MMU, so no memory > mapping or protection. That's not true for uClinux in general. If your target has MMU uClinux can/will use it. Take a look at the uClinux source tree and you'll find all kinds of targets with or without MMU.Article: 94740
Hi, I need to perform configuration-memory readback on an active (not shutdown) virtex 4 device. Does anyone know if on Virtex 4 is it still the case that readback should not be performed on active devices, for frames that are prior to memory element frames? For Virtex 2 and Spartan 3 this can lead to configuration memory corruption. The Virtex 4 documentation is unclear on this point. Thanks, VivianArticle: 94741
"Brian Davis" <brimdavis@aol.com> wrote in message news:1137459183.572092.73410@z14g2000cwz.googlegroups.com... > Symon wrote: >> >> Aha, now I see what you're saying, there's a new feature! Cool, I'll try >> it, >> even though it goes against my principle of waiting for SP3! >> > > Any wagers whether they've changed the #@%$&!! pan & zoom functions > (again) in FPGA editor 8.x ? > > Also, for other 7.1i FPGA Editor "features", see Answer Records > 22469, 21667, and 22217 ( loss of config info on manual comp edits ) > > Brian > Hi Brian, So that's interesting. It's getting to the point where I no longer trust the FPGA editor to do anything useful. I think the directed routing feature is used by a lot of Xilinx's own IP developers so it has a fighting chance of being OK! Whatever happened to those great days of the 3000 series and XACT? yours cynically, Syms. p.s. For some reason I missed the 'PCI compliance' thread a couple of weeks back. Still, I was lol when I read it yesterday! Thanks!Article: 94742
On 17 Jan 2006 02:10:40 -0800, "al82" <yscdi62k001@sneakemail.com> wrote:
>
>rk ha escrito:
>
>> On 16 Jan 2006 01:15:40 -0800, "al82" wrote:
>>
>> >
>> >>
>> >> Some info in this presentation particularly with respect to long-life
>> >> critical systems.
>> >>
>> >
>> >Don't worry.
>> >
>> >Military electronics is not covered by the RoHS directive. ;-)
>>
>> Airbus.
>
>Most of the Airbus electronics is not covered by the RoHS directive
>either.
[ snip ]
The question is when only lead-free components are available or when they
get slid in over time unintentionally during maintanence, upgrades, or new
production runs of equipment years after the initial build. I think that
the device manufacturers should have distinct part numbers (perhaps in the
suffix) that unambiguously identify the plating. This is an accident
waiting to happen.
Article: 94743Symon wrote: > > Whatever happened to those great days of the 3000 series and XACT? > A little nostalgic bug reporting: Back in the good old days, I entered designs directly in XACT and simulated the lca file using ViewSim. The last versions of XACT had a very annoying bug, where occasionally a seemingly random CLB in the design would be wiped out; you'd have to go back and re-create the logic each time this happened. I finally caught on that the problem only occured when you had done an EditBlock, followed by a SWItch, and then done a process like DRC that shelled out, without first doing an ENDBLOCK. Once I started closing any open blocks first, the problem vanished, never to return; and the designers rejoiced. BrianArticle: 94744
Hello, I have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It is connected to AHC573 latch output pins. In the test phase pins of CPLD are unassigned, and 573 has ca. 0,xxx on the output ( 5 on input), and is getting hot quite fast. First I thought that the chip is broken so I have desoldered it and now with 2nd latch I have the same results. So I thought that it is result of unassigned CPLD pins. Is it true ? (configured as outputs with 0 by default ???) BTW. I'm using Quartus II 5.1Article: 94745
Just to be clear: The PPC in Virtex-4 DOES have the MMU, right? "Larry Doolittle" <ldoolitt@localhost.localdomain> wrote in message news:slrndso1rb.d3k.ldoolitt@localhost.localdomain... > On 2006-01-16, tony.p.lee@gmail.com <tony.p.lee@gmail.com> wrote: > > John, > > > > Is it true that uCLinux does not have protected kernel memory? > > A simple programming loop index comparision error can wipe out the > > system memory including kernel. > > Yes, that's the point of uCLinux, to support machines > that have a flat address space. > > > I had to deal with this kind of problems in vxWorks days, it was > > a nightmare. > > Me too, man. > > > I am using PPC with Linux and it has been a joy to use. There > > were one bugs shows up in test group that crash one program - first > > crash in 6 months. It is solved in 5 mintues after looking a the > > core dump. > > So choose a processor supported by (non-uC) Linux. > There are a dozen architectures to choose from. > Leon Sparc can target an FPGA, I'm pretty sure it > has virtual memory. Presumably slower and bigger > than microBlaze for FPGA work, but it should be more > reliable from your perspective. > > - LarryArticle: 94746
Hi Jaroslaw Pawelczyk a =E9crit: > have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It > is connected to AHC573 latch output pins. In the test phase pins of CPLD = are > unassigned, and 573 has ca. 0,xxx on the output ( 5 on input), and is get= ting > hot quite fast. This is a very common problem: by default, QuartusII (and before QII, Max+PlusII) drives unassigned pins to ground. Just uncheck the option and recompile the design. I get stung by this on half my projects and I still don"t understand why Altera keeps this default behavior. NicolasArticle: 94747
finally the free Sample Pack info is available from Xilinx directly http://www.xilinx.com/products/boards/s3esamplepack/index.htm there is no note that there is no availability in Europe so it still makes sense to contact the distributors also in Europe, maybe there is availabily. After one more attempt to use the flashwriter.tcl it worked, so the EDK/XMD/tcl method of programming the onboard flash also works. -- Antti Lukats http://www.xilant.comArticle: 94748
Thank you, I was quite angry when I found out about it. I desoldered 573 once, burned up one of SMD pads for it, got it repaired and lost two days because of it !!! Maybe pulling to ground all unconnected pins reduce noise ? Jarek "Nicolas Matringe" <nic_o_mat@msn.com> wrote in message news:1137505700.633708.296000@g49g2000cwa.googlegroups.com... Hi Jaroslaw Pawelczyk a écrit: > have a (ok, not a fpga but at least pld) Altera MAX7064 in my project. It > is connected to AHC573 latch output pins. In the test phase pins of CPLD > are > unassigned, and 573 has ca. 0,xxx on the output ( 5 on input), and is > getting > hot quite fast. This is a very common problem: by default, QuartusII (and before QII, Max+PlusII) drives unassigned pins to ground. Just uncheck the option and recompile the design. I get stung by this on half my projects and I still don"t understand why Altera keeps this default behavior. NicolasArticle: 94749
A note to anyone who tries to use ISE 7.1 and CPLDs: make sure to either download the patch for 7.1 (no SP or SP1) or the latest service pack. This is needed to correct a problem where the CPLD is programmed with all outputs inverted. Xilinx does not directly list this problem with 7.1 on their download page. See http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21168 If this link does not work, search the Xilinx help system for "7.1 cpld inverted". Marc
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