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Messages from 94600

Article: 94600
Subject: Re: Don't even get me started on lead,
From: Eric Smith <eric@brouhaha.com>
Date: 13 Jan 2006 17:34:54 -0800
Links: << >>  << T >>  << A >>
Roel <electronics_designer@hotmail.com> writes:
> First of all: ROHS is not only about Lead! Itís also about mercury,
> cadmium, hexavalent chromium, PBB or PBDE, etc.
> 
> It's amazing that there are still people saying that such substances
> may just be dumped permanently in the environment

Lead, mercury, and cadmium all came from the environment.  We didn't make
them out of something else.

It obviously makes sense to regulate the use and disposal of hazardous
substances.  It doesn't make sense for that regulation to be a blanket
ban on certain uses of them, without regard to how those uses actually
affect the environment.

> that should be the
> environment for the next million years of civilization.

Anyone worrying about the next million years of civilization is crazy,
or perhaps ignorant.  The rate of technological change is such that
we can't predict things five years out, much less a million.  That
doesn't mean that we shouldn't worry about things that might have
negative affects past five years, but it means that it's much more
important to worry about the next 25 years or the next 100 years than
the next million.

The cost of eliminating lead in paint, plumbing, and gasoline was
relatively moderate, and had huge benefits.  The cost of eliminating it
from all electronics is enormous, and has questionable benefits, slim
at best.

Article: 94601
Subject: Re: how do I minimize the logic in this function?
From: austin <austin@xilinx.com>
Date: Fri, 13 Jan 2006 18:30:35 -0800
Links: << >>  << T >>  << A >>
Brannon,

Ah.  I see.  No clock.

Seems strange that somewhere in this whole design there is no clock that 
tells you when the data is valid, but then, it isn't something I am 
working on.

Even a strobe that tells you the address is valid could be used to clock 
the BRAM....

But, if you are doing something totally asynchronous, I will bow out 
immediately.

Austin

Brannon wrote:
> "one cycle" is the whole issue. I don't have any spare cycles. This has
> to be done asynchronously.
> 

Article: 94602
Subject: Re: how do I minimize the logic in this function?
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 13 Jan 2006 18:39:03 -0800
Links: << >>  << T >>  << A >>
Hi - 

It's easy to try out.  Here's an inelegantly-written Verilog module:

module comb_function (
   // Outputs
   out_val,
   // Inputs
   in_val,
   );

//-----FPGA I/O

  output [7:0] out_val;
  input  [5:0] in_val;

  reg    [7:0] out_val;

  always @(in_val)
    case(in_val)
       0:  out_val =  0  ; 
       1:  out_val =  66 ;
       2:  out_val =  128;
       3:  out_val =  0  ;
       4:  out_val =  64 ;
       5:  out_val =  65 ;
       6:  out_val =  66 ;
       7:  out_val =  64 ;
       8:  out_val =  130;
       9:  out_val =  128;
      10:  out_val = 136 ;
      11:  out_val = 130 ;
      12:  out_val = 0   ;
      13:  out_val = 66  ;
      14:  out_val = 128 ;
      15:  out_val = 0   ;
      16:  out_val = 68  ;
      17:  out_val = 69  ;
      18:  out_val = 65  ;
      19:  out_val = 68  ;
      20:  out_val = 80  ;
      21:  out_val = 81  ;
      22:  out_val = 69  ;
      23:  out_val = 80  ;
      24:  out_val = 64  ;
      25:  out_val = 65  ;
      26:  out_val = 66  ;
      27:  out_val = 64  ;
      28:  out_val = 68  ;
      29:  out_val = 69  ;
      30:  out_val = 65  ;
      31:  out_val = 68  ;
      32:  out_val = 138 ;
      33:  out_val = 136 ;
      34:  out_val = 160 ;
      35:  out_val = 138 ;
      36:  out_val = 130 ;
      37:  out_val = 128 ;
      38:  out_val = 136 ;
      39:  out_val = 130 ;
      40:  out_val = 162 ;
      41:  out_val = 160 ;
      42:  out_val = 168 ;
      43:  out_val = 162 ;
      44:  out_val = 138 ;
      45:  out_val = 136 ;
      46:  out_val = 160 ;
      47:  out_val = 138 ;
      48:  out_val = 0   ;
      49:  out_val = 66  ;
      50:  out_val = 128 ;
      51:  out_val = 0   ;
      52:  out_val = 64  ;
      53:  out_val = 65  ;
      54:  out_val = 66  ;
      55:  out_val = 64  ;
      56:  out_val = 130 ;
      57:  out_val = 128 ;
      58:  out_val = 136 ;
      59:  out_val = 130 ;
      60:  out_val = 0   ;
      61:  out_val = 66  ;
      62:  out_val = 128 ;
      63:  out_val = 0   ;
    endcase

endmodule

The resource usage is:

Mapping to part: xc2v40fg256-4
LUT2            6 uses
LUT3            3 uses
LUT4            11 uses

Synplify estimates an in-to-out delay of 2.865ns, NOT including I/O
buffers.  Note, too, that I used -4, which should be the lowest speed
grade.

Seems pretty fast and cheap.

Bob Perlman
Cambrian Design Works


On 13 Jan 2006 14:22:20 -0800, "Brannon" <brannonking@yahoo.com>
wrote:

>I have an async function with six bits in and eight bits out (listed
>below). I need to minimize the logic usage (in a Virtex2) for this
>function. It appears that most kmap tools will support six bits in but
>only one bit out. Anyone have a tool or method they would recommend to
>help with my problem?
>
>I do it currently with two three bit subtracters (in LUTs, not
>CarryChain) and a 6bit x 16 element mux (using muxf prims) running as a
>lookup table. The output of one adder drives the mux S input. It just
>takes too much time and space.
>
>In      Out
>0       0
>1       66
>2       128
>3       0
>4       64
>5       65
>6       66
>7       64
>8       130
>9       128
>10      136
>11      130
>12      0
>13      66
>14      128
>15      0
>16      68
>17      69
>18      65
>19      68
>20      80
>21      81
>22      69
>23      80
>24      64
>25      65
>26      66
>27      64
>28      68
>29      69
>30      65
>31      68
>32      138
>33      136
>34      160
>35      138
>36      130
>37      128
>38      136
>39      130
>40      162
>41      160
>42      168
>43      162
>44      138
>45      136
>46      160
>47      138
>48      0
>49      66
>50      128
>51      0
>52      64
>53      65
>54      66
>55      64
>56      130
>57      128
>58      136
>59      130
>60      0
>61      66
>62      128
>63      0
>
>Thanks for your time.

Article: 94603
Subject: Any FPGA with programming info available?
From: weingart@cs.ualberta.ca (Tobias Weingartner)
Date: Sat, 14 Jan 2006 03:04:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
No, I'm not talking which pins to toggle how fast and when, but is
there any 600K+ gate (roughly) FPGA available which also gives the
layout and programming information for their bitstreams/etc?

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Article: 94604
Subject: Re: FPGA Journal Article
From: weingart@cs.ualberta.ca (Tobias Weingartner)
Date: Sat, 14 Jan 2006 03:09:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kevin Morris wrote:
> 
> Any takers?

Real/Complete programming information would be a very good start to a new
hobby phase.  But I think that all the FPGA vendors are too scared to give
out this information.  Come on, xilinx, altera, etc, etc.  What could there
possibly be so secret in the format for how to program your parts?  :)

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Article: 94605
Subject: Re: FPGA Altair Advice
From: weingart@cs.ualberta.ca (Tobias Weingartner)
Date: Sat, 14 Jan 2006 03:17:48 +0000 (UTC)
Links: << >>  << T >>  << A >>
logjam wrote:
> 
> Basically what I'm looking for is an FPGA development board that would
> be suited to hold the 8080.  I would also like to integrate an
> "optional" boot ROM, RAM, serial card, cassette card, etc.  These
> devices wouldn't take up too many resources I'd think.

There are various fpga/retro boards out there.  In particular, there is
one from a woman in germany, who wanted to replicate the C64/C128 in an
fpga board.  I forget the exact name.  Anyways, they've got things going
to the point of having a number of different cores availabe, I believe
even some atari/etc ones.  I'm sure they'd welcome someone doing an
altair "port"...

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Article: 94606
Subject: Re: How to create a delay BUF?
From: "Rob" <robnstef@frontiernet.net>
Date: Sat, 14 Jan 2006 03:51:45 GMT
Links: << >>  << T >>  << A >>
Typically any combinatorial equation, like a conditional statement, will get 
placed within a LUT.


<wuyi316904@gmail.com> wrote in message 
news:1137168099.684612.164140@o13g2000cwo.googlegroups.com...
> can you give me a verilog code,thank u!
> 



Article: 94607
Subject: Re: FPGA Journal Article
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Fri, 13 Jan 2006 20:24:57 -0800
Links: << >>  << T >>  << A >>
On Sat, 14 Jan 2006 01:55:00 +0100, "Piotr Wyderski"
<wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote:

>Kevin Morris wrote:
>

>>  Radio Shack shifted their focus from 50-in-1 project kits
>
>I think that kits are a big misunderstanding, because you just need to
>connect provided parts as described on a provided diagram. Even
>a chimp could do it.

But you want something for kids to build when they're young, before
they're capable of designing something themselves.  Lots of us cut our
teeth on the 50-in-1 sets and Heathkits.

If a kid between the ages of 8 and 15 asked me how to get started in
electronics, I'd:

1) send them to Ramsey Electronics
(http://www.ramseyelectronics.com/), which makes nice, relatively
inexpensive kits of varying complexity.

2) ask them to get off my lawn.  (Sort of obligatory at my age.)

Bob Perlman
Cambrian Design Works  

Article: 94608
Subject: Re: Don't even get me started on lead,
From: Al Clark <dsp@danvillesignal.com>
Date: Sat, 14 Jan 2006 06:19:56 GMT
Links: << >>  << T >>  << A >>
Roel <electronics_designer@hotmail.com> wrote in news:dq9g76$ndq$1
@news4.zwoll1.ov.home.nl:

> dp wrote:
> >
> > This whole ROHS thing is such an idiotic thing to do that it
> > is really frightening how easy it was to drag the whole industry
> > into it...
> >
> 
> Austin Lesea wrote:
> > There is absolutely no reason to go through this nonsense when
> > automotive lead acid car batteries are thrown away by the roadside 
and
> > in landfills every day...
> 
> Al Clark wrote:
> > Just imagine if the billions of dollars being spent on converting
> > electronics to lead free could have been spent on something that 
would
> > actually have an impact on improving the environment.
> >
> > Just a simple, back of the envelope calculation would have shown that 
> this
> > whole initiative is crazy.
> >
> 
> First of all: ROHS is not only about Lead! Itís also about mercury, 
> cadmium, hexavalent chromium, PBB or PBDE, etc.

I agree its not just about lead. Removing all the lead from circuit 
boards is not going to have a big impact on the environment. 


> 
> It's amazing that there are still people saying that such substances 
may 
> just be dumped permanently in the environment that should be the 
> environment for the next million years of civilization.

> 
> There is done amazingly much research of the effect to humans of these 
> kinds of substances in the environment. Read the background stories of 
> RoHS and WEEE and you probably finally will understand it all. And yes 
> there is much more to do, but this is a very good start.

This is a very bad start. Products are either completely exempt due in 
part to reliability concerns or they are subject to zero tolerance. 

I think a reasonable plan that reduced the lead content would be much 
better than a total ban. If I have one 0603 non RoHS resistor on my 
board, the board is probably am not in compliance. As I understand it, if 
a company in the EU has existing inventory, they can continue to use it 
(provided it is already in Europe). I'm supposed to throw away all my 
lead based inventory (in a landfill?), and in many cases, completely 
redesign my product. 

It is still hard to buy many components lead free, even when they 
theoretically exist. 

I have a connector that I buy maybe 3000 pieces a year of. The mfr of 
this part will make it lead free if I purchase 20000 pieces! I can't even 
tell that the part has any lead content. Its entirely gold plated. My 
guess is that it is in the plastic.

> 
> The EU was late already with these kind of regulations. Japan was 
> smarter already for years. Lucky enough China is the first big one to 
> follow. It's a shame that US, far the largest polluter in the world, 
> still hasn't regulations in this area (the only serious exception is 
> California).
> 
> Roel
> 



-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Article: 94609
Subject: Re: OT: RoHS and Lead?
From: Al Clark <dsp@danvillesignal.com>
Date: Sat, 14 Jan 2006 06:25:52 GMT
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.co.nz> wrote in
news:43c83fd8@clear.net.nz: 

> Al Clark wrote:
> 
>> "Martin" <0_0_0_0_@pacbell.net> wrote in
>> news:XiBxf.287$or4.4@newssvr12.news.prodigy.com: 
>> 
>> 
>>>Excuse the OT post, but I figured people in this group may have an
>>>answer for this odd question:
>>>
>>>In transitioning to RoHS, can you mix Lead-free parts into a standard
>>>PbSn process?  The idea is to start buying RoHS parts while depleting
>>>the existing stock of PbSn components.
>>>
>>>Good? Bad? Ugly?
>>>
>>>Thanks,
>>>
>> 
>> 
>> You are going to have no real problems soldering leadfree parts with
>> tin- lead solder. The big exception to this are BGAs. The ball of a
>> BGA is solder. If it is leadfree, it will need to be soldered at a
>> higher temperature. You CM will need to know this.
>> 
>> Many parts have been supplied leadfree for several years. This
>> includes many of the passives that you probably are already using.
>> They might not have been labeled as such.
>> 
>> We have started using lead free pcbs as well. In our case we have
>> opted for ENIG (electroless nickel/immersion gold). They are easy to
>> solder with PbSn 
>> 
>> No one really knows the long term effects of moving to RoHS. I am
>> hoping that the EU decides that July is too soon since industry is
>> not really ready. Nevertheless, I think it is prudent to plan for it
>> to happen. For example, try buying Altera PLDs. They seem to be
>> readily available in lead but not available in the lead free versions
>> (of course, Altera claims they have both). Part of this situation is
>> caused because everyone (distributors, manufacturers, etc) wants to
>> get rid of their non RoHs inventory. It's hardest on those of us on
>> the end of the chain, since we have the least amount of time to
>> transition. 
>> 
>> I think one of the biggest problems will be for products that have 
>> relatively long lives and small volume. I have already seen parts
>> that were discontinued just because the mfr didn't want to change to
>> a lead free process. How many designs will have to be completely
>> redone, just to deal with a part that has been obsoleted prematurely.
>> Even if you could buy enough existing material, you still couldn't
>> ship the existing design because there it will never be a RoHS
>> compliant part. 
> 


>   I think there are enough escape clauses in the RoHS, that you do not
> have to terminate and dump a product line, due to one non complying
> part. 
>   If you can prove that there IS no lead free alternative (yet), ( and
> that you are diligent in using lead Free, where avaialable) then
> that's one path.

This is the first that I have heard of this. Can you point to the a 
reference?


> 
>   Another is that a single part, in a Lead-free flow, is unlikely to
> trigger lead threshold alarms.

In other words, cheat?




>   Product reliability is a different question....
> 
> -jg
> 
> 
> 



-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Article: 94610
Subject: Re: FPGA Altair Advice
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 14 Jan 2006 08:05:48 +0100
Links: << >>  << T >>  << A >>
"Tobias Weingartner" <weingart@cs.ualberta.ca> schrieb im Newsbeitrag 
news:slrndsgrat.i5.weingart@irricana.cs.ualberta.ca...
> logjam wrote:
>>
>> Basically what I'm looking for is an FPGA development board that would
>> be suited to hold the 8080.  I would also like to integrate an
>> "optional" boot ROM, RAM, serial card, cassette card, etc.  These
>> devices wouldn't take up too many resources I'd think.
>
> There are various fpga/retro boards out there.  In particular, there is
> one from a woman in germany, who wanted to replicate the C64/C128 in an
> fpga board.  I forget the exact name.  Anyways, they've got things going
> to the point of having a number of different cores availabe, I believe
> even some atari/etc ones.  I'm sure they'd welcome someone doing an
> altair "port"...
>

that woman is Jeri and he is not from Germany but from the US, he designed
and VERY UNSUCCESFUL C1- computer, sold some distribution rights
to an german guy who paid her in advance, manufactred the boards and
got financial loss afterwards as Jeri did not keep her part of the deal
(did not deliver anything working ip cores).

there was later a guy Tobias from Germany who did that what Jeri was 
commited
todo, eg write functional IP cores for C1, including several retro engines.

but Tobias also got really pissed on Jeri and the C1, so he is currenty 
supporting
more the TREX C1 board

I do have the old C1 board, its just collecting dust somewhere. do not buy 
the C1
take eiter TREX C1 or Trenz retro or somethin else

antti










Article: 94611
Subject: Re: OT: RoHS and Lead?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Sat, 14 Jan 2006 20:44:16 +1300
Links: << >>  << T >>  << A >>
Al Clark wrote:
> Jim Granville <no.spam@designtools.co.nz> wrote in
> 
>>  I think there are enough escape clauses in the RoHS, that you do not
>>have to terminate and dump a product line, due to one non complying
>>part. 
>>  If you can prove that there IS no lead free alternative (yet), ( and
>>that you are diligent in using lead Free, where avaialable) then
>>that's one path.
> 
> 
> This is the first that I have heard of this. Can you point to the a 
> reference?

  In the RoHS docs, they talk about what lead-content items are
exempt, and also comment this is subject to availability of
no practical alternative. ie if the alternative is that
without this item, the product cannot exist.
  Some solders are included in this.
The exemptions seem to be growing every time I read them....


>>  Another is that a single part, in a Lead-free flow, is unlikely to
>>trigger lead threshold alarms.
> 
> 
> In other words, cheat?

No. "lead free" does not mean 0.00% Lead.

-jg


Article: 94612
Subject: Re: Don't even get me started on lead,
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Sat, 14 Jan 2006 20:57:28 +1300
Links: << >>  << T >>  << A >>
ahh.. Anybody who doesn't consider the environment is a fool.  You may say a
million years is too far to consider.. but it only is if you don't think
Humanity will kill itself off by then.  Did you know over a million children
a year die in Asia due to air pollution?  How about by the time they reach
20 the air quality has reduced their lifespan by 5 years ?  Its important to
care about what we put into the atmosphere or into our ground.
The main problem is the lobby groups.. I'd say the battery makers have a
better lobby group than the electronics.  Or it would be an offence to dump
any kind of battery by now, you would have to take them to an approved
recycler that has sufficient protection on its plant to avoid contamination
of the surrounding area.

Protect the planet.. its the only one we've got.  Don't rely on finding
another to pollute  :-)

Simon


"Eric Smith" <eric@brouhaha.com> wrote in message
news:qh1wzbsibl.fsf@ruckus.brouhaha.com...
> Roel <electronics_designer@hotmail.com> writes:
> > First of all: ROHS is not only about Lead! It's also about mercury,
> > cadmium, hexavalent chromium, PBB or PBDE, etc.
> >
> > It's amazing that there are still people saying that such substances
> > may just be dumped permanently in the environment
>
> Lead, mercury, and cadmium all came from the environment.  We didn't make
> them out of something else.
>
> It obviously makes sense to regulate the use and disposal of hazardous
> substances.  It doesn't make sense for that regulation to be a blanket
> ban on certain uses of them, without regard to how those uses actually
> affect the environment.
>
> > that should be the
> > environment for the next million years of civilization.
>
> Anyone worrying about the next million years of civilization is crazy,
> or perhaps ignorant.  The rate of technological change is such that
> we can't predict things five years out, much less a million.  That
> doesn't mean that we shouldn't worry about things that might have
> negative affects past five years, but it means that it's much more
> important to worry about the next 25 years or the next 100 years than
> the next million.
>
> The cost of eliminating lead in paint, plumbing, and gasoline was
> relatively moderate, and had huge benefits.  The cost of eliminating it
> from all electronics is enormous, and has questionable benefits, slim
> at best.



Article: 94613
Subject: Re: FPGA Journal Article
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 14 Jan 2006 00:55:46 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> I have struggled for decades to come up with enticing demo projects for
> digital circuits, and I have made my rules:
> It must be something that cannot be done with just a microprocessor.
> That means it must be something fast. Audio, video, radio, robotics
> come to mind.

I can think of two ideas.

One is an audio digital delay.  A CODEC, some analog for the front and
back ends, a rotary encoder, some buttons, an LCD and/or some LEDs for
the user interface, an FPGA for the delay engine and the logic to
handle the user interface, and a couple of SRAM chips for the delay
memory.   The delay engine is a pair of address counters and you need a
state machine to handle the memory access, and a couple of shift
registers to do the I2S interface.  Hell, while you're at it, add a
digital input level meter and blink some LEDs.

A second is a simple logic analyzer.  Of course, the hard part here is
writing a Windows (or Mac OS X or Linux) host program.

-a


Article: 94614
Subject: Re: Any FPGA with programming info available?
From: "Antti Lukats" <antti@openchip.org>
Date: Sat, 14 Jan 2006 10:11:30 +0100
Links: << >>  << T >>  << A >>
"Tobias Weingartner" <weingart@cs.ualberta.ca> schrieb im Newsbeitrag 
news:slrndsgqh6.i5.weingart@irricana.cs.ualberta.ca...
> No, I'm not talking which pins to toggle how fast and when, but is
> there any 600K+ gate (roughly) FPGA available which also gives the
> layout and programming information for their bitstreams/etc?
>
> -- 
only Atmek AT40K/At94 info is available (under NDA from Atmel) or open 
sourced info - almost complete

someone in germany has reversed most of the V2 lut+interconnect

there are still some componiey offering embedded FPGA cores, so for those I 
assume the programing info is available

except that nothig is public

Antti
http://www.xilant.com



Article: 94615
Subject: Re: Xilinx Virtex-4 BRAM-16 Simulation
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sat, 14 Jan 2006 10:46:03 +0100
Links: << >>  << T >>  << A >>
Your BRAM is configured as 36bits width. So the
5 LSBs bit address should be zeroes all the time.

Cfr ug070.pdf page 120.


Sylvain


Brad Smallridge wrote:
> Thanks for words of encouragement Ray.
> 
> I went back to double check if all the simulation
> and libraries were downloaded and installed. It
> seems as if they are.  All from the download page
> that Xilinx is advertising on the home page right
> now for the 8.i software. Three packages in all,
> the ISE, ModelSim III, and it's library.
> 
> I am still not getting any output from the RAMB16
> primitive.  Seems to get stuck on the 0th address.
> I have wiggled all the signals but I all I can see is
> is the init value and the 0th address value.  Please
> take a look at my wrapper file and I also included
> the VHDL generated from the Waveform tool after
> the Generate Expected Value option. I know it is
> probably some silly mistake.
> 
> Brad Smallridge aivision
> 
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> 
> library UNISIM;
> use UNISIM.VComponents.all;
> 
> entity bram9p is
>  port (
>    clkb   :  IN std_logic;
>    enb    :  IN std_logic;
>    ssrb   :  IN std_logic;
>    regceb :  IN std_logic;
>    addrb  :  IN std_logic_VECTOR(14 downto 0);
>    web    :  IN std_logic_VECTOR( 3 downto 0);
>    doutb  : OUT std_logic_VECTOR(31 downto 0) );
> end bram9p;
> 
> architecture Behavioral of bram9p is
> 
> begin
> 
>    -- RAMB16: Virtex-4 16k+2k Parity Paramatizable BlockRAM
>    -- Xilinx  HDL Language Template version 8.1i
>    RAMB16_inst : RAMB16
>    generic map (
>       DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
>       DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
>       INIT_A => X"000000000", --  Initial values on A output port
>       INIT_B => X"000000003", --  Initial values on B output port
>       INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output 
> registers (TRUE or FALSE)
>       INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output 
> registers (TRUE or FALSE)
>       RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
>       RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
>       READ_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
>       READ_WIDTH_B => 36, -- Valid values are 1,2,4,9,18 or 36
>       SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", 
> "WARNING_ONLY", "GENERATE_X_ONLY
>                                    -- or "NONE
>       SRVAL_A => X"000000000", --  Port A ouput value upon SSR assertion
>       SRVAL_B => X"CCCCCCABC", --  Port B ouput value upon SSR assertion
>       WRITE_MODE_A => "READ_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
>       WRITE_MODE_B => "READ_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
>       WRITE_WIDTH_A => 36, -- Valid values are 1,2,4,9,18 or 36
>       WRITE_WIDTH_B => 36, -- Valid values are 1,2,4,9,18 or 36
>       -- The following INIT_xx declarations specify the initial contents of 
> the RAM
>       INIT_00 => 
> X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
>       INIT_01 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_02 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_03 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_04 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_05 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_06 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_07 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_08 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_09 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0A => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0B => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0C => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0D => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0E => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_0F => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_10 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_11 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_12 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_13 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_14 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_15 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_16 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_17 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_18 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_19 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1A => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1B => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1C => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1D => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1E => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_1F => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_20 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_21 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_22 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_23 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_24 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_25 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_26 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_27 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_28 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_29 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2A => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2B => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2C => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2D => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2E => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_2F => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_30 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_31 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_32 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_33 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_34 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_35 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_36 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_37 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_38 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_39 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3A => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3B => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3C => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3D => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3E => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INIT_3F => 
> X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
>       -- The next set of INITP_xx are for the parity bits
>       INITP_00 => 
> X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112",
>       INITP_01 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_02 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_03 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_04 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_05 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_06 => 
> X"0000000000000000000000000000000000000000000000000000000000000000",
>       INITP_07 => 
> X"00D00A0100010B01000100010001000100010001000100010001DEAD00100112")
>    port map (
>       CASCADEOUTA => open,                  -- 1-bit cascade output
>       CASCADEOUTB => open,                  -- 1-bit cascade output
>       DOA         => open,                  -- 32-bit A port Data Output
>       DOB         => doutb(31 downto 0),    -- 32-bit B port Data Output
>       DOPA        => open,                  -- 4-bit  A port Parity Output
>       DOPB        => open,                  -- 4-bit  B port Parity Output
>       ADDRA       => (others=>'0'),         -- 15-bit A port Address Input
>       ADDRB       => addrb(14 downto 0),    -- 15-bit B port Address Input
>       CASCADEINA  => '0',                   -- 1-bit cascade A input
>       CASCADEINB  => '0',                   -- 1-bit cascade B input
>       CLKA        => '0',                   -- Port A Clock
>       CLKB        => clkb,                  -- Port B Clock
>       DIA         => (others=>'0'),         -- 32-bit A port Data Input
>       DIB         => (others=>'0'),         -- 32-bit B port Data Input
>       DIPA        => (others=>'0'),         -- 4-bit  A port parity Input
>       DIPB        => (others=>'0'),         -- 4-bit  B port parity Input
>       ENA         => '0',                   -- 1-bit  A port Enable Input
>       ENB         => enb,                   -- 1-bit  B port Enable Input
>       REGCEA      => '0',                   -- 1-bit A port register enable 
> input
>       REGCEB      => regceb,                -- 1-bit B port register enable 
> input
>       SSRA        => '0',                   -- 1-bit  A port Synchronous 
> Set/Reset Input
>       SSRB        => ssrb,                  -- 1-bit  B port Synchronous 
> Set/Reset Input
>       WEA         => "0000",                -- 4-bit  A port Write Enable 
> Input
>       WEB         => web );                 -- 4-bit  B port Write Enable 
> Input
> 
> end Behavioral;
> 
> 
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
> library UNISIM;
> use UNISIM.VComponents.all;
> USE IEEE.STD_LOGIC_TEXTIO.ALL;
> USE STD.TEXTIO.ALL;
> 
> ENTITY waveform IS
> END waveform;
> 
> ARCHITECTURE testbench_arch OF waveform IS
>     FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
> 
>     COMPONENT bram9p
>         PORT (
>             clkb : In std_logic;
>             enb : In std_logic;
>             ssrb : In std_logic;
>             regceb : In std_logic;
>             addrb : In std_logic_vector (14 DownTo 0);
>             web : In std_logic_vector (3 DownTo 0);
>             doutb : Out std_logic_vector (31 DownTo 0)
>         );
>     END COMPONENT;
> 
>     SIGNAL clkb : std_logic := '0';
>     SIGNAL enb : std_logic := '0';
>     SIGNAL ssrb : std_logic := '0';
>     SIGNAL regceb : std_logic := '0';
>     SIGNAL addrb : std_logic_vector (14 DownTo 0) := "000000000000000";
>     SIGNAL web : std_logic_vector (3 DownTo 0) := "0000";
>     SIGNAL doutb : std_logic_vector (31 DownTo 0) := 
> "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
> 
>     SHARED VARIABLE TX_ERROR : INTEGER := 0;
>     SHARED VARIABLE TX_OUT : LINE;
> 
>     constant PERIOD : time := 200 ns;
>     constant DUTY_CYCLE : real := 0.5;
>     constant OFFSET : time := 0 ns;
> 
>     BEGIN
>         UUT : bram9p
>         PORT MAP (
>             clkb => clkb,
>             enb => enb,
>             ssrb => ssrb,
>             regceb => regceb,
>             addrb => addrb,
>             web => web,
>             doutb => doutb
>         );
> 
>         PROCESS    -- clock process for clkb
>         BEGIN
>             WAIT for OFFSET;
>             CLOCK_LOOP : LOOP
>                 clkb <= '0';
>                 WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
>                 clkb <= '1';
>                 WAIT FOR (PERIOD * DUTY_CYCLE);
>             END LOOP CLOCK_LOOP;
>         END PROCESS;
> 
>         PROCESS
>             PROCEDURE CHECK_doutb(
>                 next_doutb : std_logic_vector (31 DownTo 0);
>                 TX_TIME : INTEGER
>             ) IS
>                 VARIABLE TX_STR : String(1 to 4096);
>                 VARIABLE TX_LOC : LINE;
>                 BEGIN
>                 IF (doutb /= next_doutb) THEN
>                     STD.TEXTIO.write(TX_LOC, string'("Error at time="));
>                     STD.TEXTIO.write(TX_LOC, TX_TIME);
>                     STD.TEXTIO.write(TX_LOC, string'("ns doutb="));
>                     IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, doutb);
>                     STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
>                     IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_doutb);
>                     STD.TEXTIO.write(TX_LOC, string'(" "));
>                     TX_STR(TX_LOC.all'range) := TX_LOC.all;
>                     STD.TEXTIO.writeline(RESULTS, TX_LOC);
>                     STD.TEXTIO.Deallocate(TX_LOC);
>                     ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
>                     TX_ERROR := TX_ERROR + 1;
>                 END IF;
>             END;
>             BEGIN
>                 -- -------------  Current Time:  85ns
>                 WAIT FOR 85 ns;
>                 ssrb <= '1';
>                 addrb <= "000000000000001";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  115ns
>                 WAIT FOR 30 ns;
>                 CHECK_doutb("00000000000000000000000000000011", 115);
>                 -- -------------------------------------
>                 -- -------------  Current Time:  285ns
>                 WAIT FOR 170 ns;
>                 ssrb <= '0';
>                 addrb <= "000000000000010";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  485ns
>                 WAIT FOR 200 ns;
>                 enb <= '1';
>                 addrb <= "000000000000011";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  515ns
>                 WAIT FOR 30 ns;
>                 CHECK_doutb("00000000000100000000000100010010", 515);
>                 -- -------------------------------------
>                 -- -------------  Current Time:  685ns
>                 WAIT FOR 170 ns;
>                 regceb <= '1';
>                 addrb <= "000000000000100";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  885ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000000101";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  1085ns
>                 WAIT FOR 200 ns;
>                 regceb <= '0';
>                 addrb <= "000000000000110";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  1285ns
>                 WAIT FOR 200 ns;
>                 enb <= '0';
>                 addrb <= "000000000000111";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  1485ns
>                 WAIT FOR 200 ns;
>                 regceb <= '1';
>                 addrb <= "000000000001000";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  1685ns
>                 WAIT FOR 200 ns;
>                 regceb <= '0';
>                 addrb <= "000000000001001";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  1885ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000001010";
>                 web <= "1111";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  2085ns
>                 WAIT FOR 200 ns;
>                 enb <= '1';
>                 addrb <= "000000000001011";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  2285ns
>                 WAIT FOR 200 ns;
>                 enb <= '0';
>                 regceb <= '1';
>                 addrb <= "000000000001100";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  2485ns
>                 WAIT FOR 200 ns;
>                 regceb <= '0';
>                 addrb <= "000000000001101";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  2685ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000001110";
>                 web <= "0000";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  2885ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000001111";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  3085ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010000";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  3285ns
>                 WAIT FOR 200 ns;
>                 ssrb <= '1';
>                 addrb <= "000000000010001";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  3485ns
>                 WAIT FOR 200 ns;
>                 ssrb <= '0';
>                 addrb <= "000000000010010";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  3685ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010011";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  3885ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010100";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  4085ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010101";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  4285ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010110";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  4485ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000010111";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  4685ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000011000";
>                 -- -------------------------------------
>                 -- -------------  Current Time:  4885ns
>                 WAIT FOR 200 ns;
>                 addrb <= "000000000011001";
>                 -- -------------------------------------
>                 WAIT FOR 315 ns;
> 
>                 IF (TX_ERROR = 0) THEN
>                     STD.TEXTIO.write(TX_OUT, string'("No errors or 
> warnings"));
>                     STD.TEXTIO.writeline(RESULTS, TX_OUT);
>                     ASSERT (FALSE) REPORT
>                       "Simulation successful (not a failure).  No problems 
> detected."
>                       SEVERITY FAILURE;
>                 ELSE
>                     STD.TEXTIO.write(TX_OUT, TX_ERROR);
>                     STD.TEXTIO.write(TX_OUT,
>                         string'(" errors found in simulation"));
>                     STD.TEXTIO.writeline(RESULTS, TX_OUT);
>                     ASSERT (FALSE) REPORT "Errors found during simulation"
>                          SEVERITY FAILURE;
>                 END IF;
>             END PROCESS;
> 
>     END testbench_arch;
> 
> 
>  
> 
> 

Article: 94616
Subject: Re: FPGA Altair Advice
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 14 Jan 2006 12:54:55 -0000
Links: << >>  << T >>  << A >>
Grant

If you are looking for a development board with lots of uncommitted I/O to 
add modules then have a look at our Raggedstone1 and Broaddown2 products. 
Our MINI-CAN product also has a lot I/O but is slightly harder to use. There 
should be details of a pile of add-on modules appearing on our website 
sometime this week for Raggedstone1 and Broaddown2 which may also be of use.

If you don't need the PCI on these boards we have a connection module that 
allows the use of the interface to create 50 I/O which is 5V tolerant. We 
also have a I/O connection SODIMM that fits the socket on Broaddown2 giving 
a large pile of extra I/O on that product.

If those are not enough Broaddown4 (Virtex-4 - various up to LX160) will on 
sale shortly soon to be followed by Broaddown3 (XC3S4000/5000). Both these 
product will offer very large I/O counts.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"logjam" <grant@cmosxray.com> wrote in message 
news:1137186601.951204.325810@g43g2000cwa.googlegroups.com...
>I was working on a Macintosh clone project (a clone of the original
> 128k), but I'm not willing to invest any more time in something that
> Apple would probably kill with a C&D order.
>
> I'm now working on a hardware replica of the Altair.  I'm scanning the
> PCB layout and creating historically accurate replicas.  I've come to
> the conclusion that the average person is not going to be able to
> afford a kit "just for the fun of it".  There are literally square feet
> of PCBs required and a lot of the components will be expensive.
>
> This leads me to the idea of putting the Altair into an FPGA for people
> who want the blinking light effect but could care less about the guts.
> This would be similar to the PDP-8 clone that is an inch thick and can
> be hung on a wall like an interactive picture.  I don't have any
> experience designing logic for FPGAs, but like learning
> C/Assembler/Visual basic...I can probably use code examples to teach
> myself.
>
> Basically what I'm looking for is an FPGA development board that would
> be suited to hold the 8080.  I would also like to integrate an
> "optional" boot ROM, RAM, serial card, cassette card, etc.  These
> devices wouldn't take up too many resources I'd think.
>
> The only possible problem I can think of for an Altair FPGA is that I
> would want all the bus signals brought out for the front panel and for
> optional interface cards.  Is the T80 core accurate enough to produce
> the two clock phases and all of the bus signals?
>
> What development board would you suggest I buy for this purpose?  I've
> heard about schematic entry for the logic, and I'd like to have that
> tool as an option.
>
> Thanks for your time,
> Grant
> 



Article: 94617
Subject: Re: Don't even get me started on lead,
From: "Symon" <symon_brewer@hotmail.com>
Date: 14 Jan 2006 06:47:01 -0800
Links: << >>  << T >>  << A >>

Austin Lesea wrote:
> Dimiter,
>
> As for "does RoHs make my life any safer applied to electronics?" I
> would have to agree with you:  it does not.
>
> There is absolutely no reason to go through this nonsense when
> automotive lead acid car batteries are thrown away by the roadside and
> in landfills every day...
>
I believe that in Germany you can't get a new car battery unless you
take the old one back. I heard they get >99% recycling this way.
Cheers, Syms.


Article: 94618
Subject: Student Pricing Now on our Website
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Sat, 14 Jan 2006 18:40:57 -0000
Links: << >>  << T >>  << A >>
As a prelude to our new website going live there is now a webpage with
outline details of our University Access Program (UAP) including student
board pricing,  University and School packs, loan programs and our visiting
lecturer scheme. Details here http://www.enterpoint.co.uk/uap/uap.html.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Student FPGA Development Board.
http://www.enterpoint.co.uk




Article: 94619
Subject: Re: Xilinx Virtex-4 BRAM-16 Simulation
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sat, 14 Jan 2006 10:45:07 -0800
Links: << >>  << T >>  << A >>
Aha! Thank you.

> Your BRAM is configured as 36bits width. So the
> 5 LSBs bit address should be zeroes all the time.



Article: 94620
Subject: Re: Don't even get me started on lead,
From: Sylvain Munaut <com.246tNt@tnt>
Date: Sat, 14 Jan 2006 20:30:13 +0100
Links: << >>  << T >>  << A >>
John_H wrote:
> "Roel" <electronics_designer@hotmail.com> wrote in message 
> news:dq9g76$ndq$1@news4.zwoll1.ov.home.nl...
> <snip>
> 
>>It's amazing that there are still people saying that such substances may 
>>just be dumped permanently in the environment that should be the 
>>environment for the next million years of civilization.
> 
> <snip>
> 
> It's amazing anyone thinks civilization would last a million years. 
> 
> 

Exactly what I thought when I saw the post ...

Come on, at the rate we're going I expect no more than a few hundred
years ...


	Sylvain

Article: 94621
Subject: Re: FPGA Journal Article
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 14 Jan 2006 14:45:48 -0600
Links: << >>  << T >>  << A >>
>A second is a simple logic analyzer.  Of course, the hard part here is
>writing a Windows (or Mac OS X or Linux) host program.

USB seems like the obvious choice, but I don't think any of the low cost
demo boards support that.

Some of them have VGA connectors.  If you have a spare monitor you
could do the display output in the FPGA too.

RS-232 is probably good enough to have a lot of fun.  115K works
fine with not-long cables.  1000 points is a reasonably size.
If you have 8 channels, that's 8K bits.  Under a second.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 94622
Subject: Mistake in Xilinx dsp-book.pdf?
From: Holger Blum <usenet0106@kennsch.net>
Date: Sat, 14 Jan 2006 23:00:05 +0100
Links: << >>  << T >>  << A >>
Hello!

While working with a MAC-FIR I came across an equation in Xilinx'
DSP-book (http://www.xilinx.com/publications/books/dsp/dsp-book.pdf)
which seems to be wrong in my eyes.

On page 65 equation 4.4 for the generic saturation level says
Output width = ceil(log2(2^(b-1)*2^(c-1)*N))+1
Where b/c are the numbers of data/coefficient bits and N is the filter
length.

This formula is, apart from a missing parenthesis, ok, but the next one
for known coefficients says
Output width = ceil(log2(2^(b-1)*abs(sum(coef))*N))+1

Again missing right parenthesis and the N is in my eyes wrong, because
it is already included in the sum of coefficients. Could anyone approve
this? I have to cite this paper in a thesis in lack of another source
for this equation (though it seems to be obvious, but I have to be sure).

Thanks,
Holger

Article: 94623
Subject: Re: Don't even get me started on lead,
From: rk <stellare@nospamplease.verizon.net>
Date: Sun, 15 Jan 2006 01:11:57 GMT
Links: << >>  << T >>  << A >>
On Fri, 13 Jan 2006 10:53:38 -0800, Austin Lesea <austin@xilinx.com> wrote:

>Dimiter,
>
>As for "does RoHs make my life any safer applied to electronics?" I 
>would have to agree with you:  it does not.
>
>There is absolutely no reason to go through this nonsense when 
>automotive lead acid car batteries are thrown away by the roadside and 
>in landfills every day...
>
>I would say clean up the major polluters first, and then go after the 
>next tier.  To go after electronics, and electronics assemblies when 
>they conrtibute practically no lead to the environment is just silly.
>
>I can understand not using lead in paint for homes!  Or no lead water pipes!
>
>But is this a case of over zealousness?
>
>How about requiring a non-polluting lithium or nickel hydride battery to 
>start the cars, first?  Maybe we should go back to a hand crank (with a 
>super capacitor/generator)?
>
>Talk about removing 99.99% of the lead from our environment!


Some info in this presentation particularly with respect to long-life
critical systems.

"The Negative Impact of Lead-Free Products on Aerospace and Military
Electronics Reliability"
Andrew D. Kostic1 and Charlie Minter2
1 Northrop-Grumman
2 BMPCOE/Willcor

2004 MAPLD International Conference
September, 2004, Washington, D.C.

http://klabs.org/mapld04/presentations/session_p/p103_kostic_s.ppt

-- 
rk, Just an OldEngineer
"The number of people having any connection with the project must be
restricted in an almost vicious manner.  Use a small number of good people."
-- Kelly Johnson in Skunk Works

Article: 94624
Subject: Re: Student Pricing Now on our Website
From: kd (kdfake@spam.com)
Date: 15 Jan 2006 01:32:42 GMT
Links: << >>  << T >>  << A >>
Whats the direct link to this info?
I cannot find it on your site!
-- 
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