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"Petter Gustad" <newsmailcomp6@gustad.com> schrieb im Newsbeitrag news:7dpsmyrawe.fsf@www.gratismegler.no... > Antti.Lukats@xilant.com writes: > >> http://wiki.openchip.org/index.php/Altera:JTAG >> >> MAXII is similar to Cyclone, I have verified that in silicon > > Thanks! > > BTW, is there a way to make quartus_pgm play SVF files (or convert SVF > into some other format I can play)? I would like to play the following > file: > > SIR 10 TDI (007); > SDR 32 TDI (FFFFFFFF); ! or some other pattern > > I would then expect to observe the USERCODE value being shifted out of > the maxii_jtag module from my user logic. > > > Petter > -- you can defenetly use jam/stapl with quartus, its a bit pain as it requres CRC I think it can be ignored and after warning quartus programmer will accept the file but its generically more pain than using SVF you can connect Cable III to the JTAG and use impact, or I could search my hard disk and upload a XSVFplayer that supports byteblaster cable -- Antti Lukats http://www.xilant.comArticle: 94426
The way we do it over here is through Linux Device Drivers...I dont know which board are you using but if you have GPIO on your board then Xilinx gives you the source for the device driver for GPIO's. -- ParagArticle: 94427
Antti Lukats <antti@openchip.org> wrote: > I dont find any english description any more, it used to be online > also a evaluation version was available, what I have tested and > it worked - the commercial version of MITOUJTAG is most > likely much better than the very old version what was available > as free version. Missing english documents make MITOUJTAG hard to use... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94428
Antti Lukats <antti@openchip.org> wrote: > as more and more customers are getting their Sample Packs so I decided to > pre release the standalone programming utility for the board, available for > immediate download > http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ > this has fully working base functionality for FPGA config and Flash > programming. > both for FPGA and Flash there is no need to worry about startup clock > and for flash there is also no need to invoke and promgen or anything > same .BIT files can be used for FPGA and Flash, the startup clock > is automatically fixed to either JTAG of CCLK and the preparation > for flash is also automatic startup clock auto-fix is now also supported > in compressed bitstream (CRC is properly recalculated) > only Cable III is supported for the moment, next releases may have > wider hardware support included Probably most of the Flash programming is already available in jtagtools: http://blackfin.uclinux.org/projects/jtagtools/ -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94429
I'm surprised that the Webpack 8.1 only supports one Virtex-II Pro part. All of the other families seem to have OK coverage on the lower-end parts, why is this family supported so poorly? I wonder if Xilinx has any plans to expand support for the V2Pro family? Of course, I'm using the XC2VP7, so I can't try out the new s/w. Sigh. John ProvidenzaArticle: 94430
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:dq3gip$v5i$1@lnx107.hrz.tu-darmstadt.de... > Antti Lukats <antti@openchip.org> wrote: >> as more and more customers are getting their Sample Packs so I decided to >> pre release the standalone programming utility for the board, available >> for >> immediate download > >> http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,8/ > >> this has fully working base functionality for FPGA config and Flash >> programming. > >> both for FPGA and Flash there is no need to worry about startup clock >> and for flash there is also no need to invoke and promgen or anything > >> same .BIT files can be used for FPGA and Flash, the startup clock >> is automatically fixed to either JTAG of CCLK and the preparation >> for flash is also automatic startup clock auto-fix is now also supported >> in compressed bitstream (CRC is properly recalculated) > >> only Cable III is supported for the moment, next releases may have >> wider hardware support included > > Probably most of the Flash programming is already available in jtagtools: > > http://blackfin.uclinux.org/projects/jtagtools/ > defenetly not. the sample pack utility takes care of many aspects, namly in order to load the FPGA with flash programming IP core it may be required to set the Flash into read status mode, then trigger reconfig in parallel mode what is not seeing the signature - this will allow the JTAG port to be used to configure the FPGA. After that the flash-programming ip core can be used. if config signature is seen by FPGA at close proximity of where the parallal mode config starts then some tools like Impact, etc are not anymore able to configure the PFGA unless the config mode is changed away from BPI and power cycled. things like that are defenetly not handled by blackfin tools. they are also not handled by Impact or any other tool AnttiArticle: 94431
johnp <johnp3+nospam@probo.com> wrote: > I'm surprised that the Webpack 8.1 only supports one Virtex-II Pro > part. All > of the other families seem to have OK coverage on the lower-end parts, > why > is this family supported so poorly? > I wonder if Xilinx has any plans to expand support for the V2Pro > family? > Of course, I'm using the XC2VP7, so I can't try out the new s/w. Sigh. Did you klick on the devices filed in "project properities? Yes with webpack 8.1 the XC2VP7 is offered too. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94432
Uwe -
Thanks for the quick response. I got my info from the Xilinx Web page:
http://www.xilinx.com/ise/products/webpack_config.htm
Sounds like the Xilinx web site may be wrong.
John Providenza
Article: 94433"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:dq3gcd$v56$1@lnx107.hrz.tu-darmstadt.de... > Antti Lukats <antti@openchip.org> wrote: > >> I dont find any english description any more, it used to be online >> also a evaluation version was available, what I have tested and >> it worked - the commercial version of MITOUJTAG is most >> likely much better than the very old version what was available >> as free version. > > Missing english documents make MITOUJTAG hard to use... > exactly my point i have the last free MITOUJTAG software that can beused to some degree, but it mostly guessing. so the total lack of english docs is a pitty. he has several nice products, including download cables, etc.. but lack of docs is a pain. for me it was actually big surprise that mitoujtag support flash programming, the free version did not. well I guess he sees no market outside japan hence the missing support AnttiArticle: 94434
Thanks. But that brings up another question: Is it better to go with ucLinux or use the PPC version of linux? I suspect the latter if I have the FX part, right? "Antti Lukats" <antti@openchip.org> wrote in message news:dq3cvk$o1n$00$1@news.t-online.com... > "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag > news:MM9xf.5246$Kp.178@southeast.rr.com... > > Can anyone suggest the best evm board for virtex-4 and linux? How has > > people's experience been with it? Are USB drivers included in the linux os > > builds they provide? > > > > Thanks, > > Clark > > > I may be mistaken but I think there are no Virtex4 linux ready currently > shipping with both device and host support drivers for USB > > Virtex-4 based modules from > http://www.hydraxc.com/ > > eg LX15, LX25 and FX12 based units are currently all shipping, but the > included ucLinux reference design does not include USB drivers, this will be > supplied later on, currently only some standalone USB firmware samples are > included. > > There are possible other boards or modules with partial USB support, but > with device and host (OTG) support already included I doubt that you find > anything at the moment, you can possible find something with host support > only > > Antti > >Article: 94435
Brian, I have to weigh in on Austin's side on this one. A parallel termination is going to burn a set amount of power for a given impedance. Nothing you can do about it and still have that termination there. Period. So the choice is do you dissipate that power on-chip to save board space and parts count, or do you dissipate it in resistors on the board (that if you have enough lines, frankly, may not fit and still be close enough to the chip to do a lot of good). On designs where we are going to be burning a lot of dynamic power, I encourage my customers to not use the DCIs if they are concerned about the temperature of the die, which can become a real concern with 400 MHz clocks clocking a pretty full device. The point is, the power required for the terminations is not something that is variable, so it isn't fair to lump it in with the power dissipation of the rest of the FPGA. What Xilinx does with the DCI is give you alternatives to the resistor farm surrounding devices with lots of terminated lines coming into it. Options is a good thing, and it doesn't mean you have to do it that way.Article: 94436
Hi Antti, Do you use special tool(s) to solder a BGA pulled IC ? Or only a magnifying glass ? "Antti Lukats" <antti@openchip.org> wrote in message news:dq33oj$4pp$03$1@news.t-online.com... > "maxascent" <maxascent@yahoo.co.uk> schrieb im Newsbeitrag > news:DfmdnUpOU__8lljeRVn-uA@giganews.com... >> Can you get samples from Xilinx, Altera or Lattice? Or where is the >> cheapest place to buy small quantities? >> >> Thanks >> >> Jon > > it is possible to get samples from: Atmel (FPSLIC), Actel, Altera, Lattice > and Xilinx however you are probably easier to just buy what you want, both > xilinx and altera have FPGAs in their online shops, prices start from > about 10USD > > optionally it may actually make more sense to buy some low low cost eval > board > > avnet S3e board is 69USD > > http://www.oho-elektronik.de/ > 89EUR spartan3 module > > http://www.hardware-design.de/produkte.html > > there are lattice cheap boards 60EUR or so > > at 99-149 USD price there are many more > > you can of course do the board yourself > http://xilant.com/content/view/35/2/ > > sometimes ebay has FPGAs are low low price, so I made my first 2Million > Gate FPGA board with 49USD pulled BGA what I got from ebay > > its all up to you, if you have no FPGAs and no FPGA boards I suggest > buying the first eval board, either TREX C1 or then wait for the Xilinx > Spartan3E, of if your budget is below 100USD then choose from other > offerings > > -- > Antti Lukats > http://www.xilant.com > >Article: 94437
Austin, The subject was your repeated habit of posting the same misleading, demonstrably false information about your I/O performance in multiple threads across multiple years. I used that particular "apologize or else" thread as an example of your outrageous newsgroup postings. > > There is no apology required. > An apology is long overdue. When I pointed out in detail exactly what 'facts' in your attack posts were misleading, innacurate, and just plain wrong, you failed to deliver on the promised apology. If Xilinx management really thinks your over-the-top, attack-dog postings are winning them any new customers, or improving their credibility, they are far more out of touch than this "novice" has ever been. For examples of how to properly respond to a question about Xilinx PCI compliance, without invoking the Great Specification Conspiracy Theory, Google Steven Knapp's and Eric Crabill's old posts on PCI compliance. Brian p.s. > >DCI parallel power is fact. >Multiply the number of DCI by the power, and you get an answer. > Plus the per bank overhead of ~200 mW/bank in V2 and S3 Darn, you "forgot" that one again, didn't you? Maybe you can remind the S/W weenies to actually review the outstanding three year old CR's before the next release.Article: 94438
Ray Andraka wrote:
> I have to weigh in on Austin's side on this one. A parallel termination
> is going to burn a set amount of power for a given impedance. Nothing
> you can do about it and still have that termination there. Period.
>
As usual, Austin's response was a diversionary tactic that didn't
actually address the DCI issues I raised in that old thread.
The concern is not the parallel terminator power itself, but:
- the barely documented 200 mW per bank DCI overhead
- the barely documented 20% hit from FreezeDCI problems
- the non-repeatable, config-to-config variations in static DCI power
due to the random end state of the DCI control logic
On my first DCI design several years ago, this totalled a couple amps
of undocumented static VCCO current.
Brian
Article: 94439Brian Davis wrote: > > As usual, Austin's response was a diversionary tactic that didn't > actually address the DCI issues I raised in that old thread. > > The concern is not the parallel terminator power itself, but: > > - the barely documented 200 mW per bank DCI overhead > > - the barely documented 20% hit from FreezeDCI problems > > - the non-repeatable, config-to-config variations in static DCI power > due to the random end state of the DCI control logic > > On my first DCI design several years ago, this totalled a couple amps > of undocumented static VCCO current. > > Brian > OK, I wasn't aware of those issues. So far, I haven't used DCI because of die temperature concerns, so I haven't stumbled across the hidden issues.Article: 94440
"Brian Davis" <brimdavis@aol.com> wrote in message news:1137004586.996353.111830@g47g2000cwa.googlegroups.com... <snip> > If Xilinx management really thinks your over-the-top, attack-dog > postings are winning them any new customers, or improving their > credibility, they are far more out of touch than this "novice" has > ever been. Austin's posts aren't typically "over-the-top, attack-dog postings." When his buttons get pushed he tends to react - a human trait. You're just more effective at pushing his buttons than most. His beliefs may be skewed by what he's come to believe - another human trait - resulting in declarations of fact rather than "lets ponder this more with this new information I'm giving you." Along those lines, I love the riddle that leaves most americans perplexed but non-Americans laughing: "Q: What does an American do with a question? A: He answers it." I personally try to see the multiple sides of an issue and understand where someone else might be getting their (mis/pre)conceptions from. But not everyone takes that generic perspective. There are things I know, darnit, and those who don't know what I know are wrong when they say otherwise. Conspiracy theory aside, have you been involved with standards development? I haven't but I've seen some rather strange stuff over the years with my exposure to Telecom standards in addition to the usual electrical stuff like PCI. I don't doubt that there are compromises made that favor existing silicon because the owners of that silicon (or those transmission systems) want to revamp less of their technology. A good compromise is reached when nobody's happy.Article: 94441
"Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag news:43c54fb6$0$11500$636a15ce@news.free.fr... > Hi Antti, > Do you use special tool(s) to solder a BGA pulled IC ? > Or only a magnifying glass ? > no tools and no magnfier either :) 1.27mm BGAs are pretty easy to handle, but it balls up solder the GND at the corners then some VCCINT and VCCAUX, the JTAG some IO pins and eval board is ready ! I had some pictures of one such board online sometimes ago but at the moment I cant find them 1mm BGAs are harder, and with 0.8mm is better not to try it at all. I tried once to solder the PCI interface pins of the TI's TMS6205 DSP in 0.8mm BGA and there I failed, maybe was too impatient. AnttiArticle: 94442
johnp <johnp3+nospam@probo.com> wrote: > Uwe - > Thanks for the quick response. I got my info from the Xilinx Web page: > http://www.xilinx.com/ise/products/webpack_config.htm > Sounds like the Xilinx web site may be wrong. I got my information from the installed 8.1 webpack ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94443
Brian, Ah, finally we have some facts! -snip- > - the barely documented 200 mW per bank DCI overhead Each bank requires two reference resistors. The original power in these was not documented, nor included in the power estimator. > - the barely documented 20% hit from FreezeDCI problems FreezeDCI solved a problem with the jitter introduced by amplitude shift due to DCI. Freezing it also stopped the reference resistor search, which could (randomly) increase the ref resistor power (in V2). This has since been fixed in later families so that freeze is done better. > - the non-repeatable, config-to-config variations in static DCI power > due to the random end state of the DCI control logic as above > On my first DCI design several years ago, this totalled a couple amps > of undocumented static VCCO current. 8 banks, time 200 mW = 1.6 watts. At 1.5 volts that would be one ampere. A little exageration here? At 3.3 volts, that would be less amperes? I can appreciate your being bitten by DCI in your application. In its first appearance there were some issues (all of which mentioned above) which led to some problems with specific applications (primarily wide buses with extremely critical timing using HSTL or SSTL parallel standards). Standards which crossed a bank also had issues, as the controllers were independent (one for each bank, not synchronized). The latest family DCI is improved in these areas. But, the power is still there. AustinArticle: 94444
"Antti Lukats" <antti@openchip.org> wrote in message news:dq3cvk$o1n$00$1@news.t-online.com... > "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag > news:MM9xf.5246$Kp.178@southeast.rr.com... >> Can anyone suggest the best evm board for virtex-4 and linux? How has >> people's experience been with it? Are USB drivers included in the linux >> os >> builds they provide? >> >> Thanks, >> Clark >> > I may be mistaken but I think there are no Virtex4 linux ready currently > shipping with both device and host support drivers for USB > > Virtex-4 based modules from > http://www.hydraxc.com/ > > eg LX15, LX25 and FX12 based units are currently all shipping, but the > included ucLinux reference design does not include USB drivers, this will > be supplied later on, currently only some standalone USB firmware samples > are included. > > There are possible other boards or modules with partial USB support, but > with device and host (OTG) support already included I doubt that you find > anything at the moment, you can possible find something with host support > only > > Antti > > Interesting board! Do you know other "mini" modules? Many Thanks MarcoArticle: 94445
"Marco T." <marcotoschi@nospam.it> schrieb im Newsbeitrag news:dq3nck$v19$1@nnrp.ngi.it... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dq3cvk$o1n$00$1@news.t-online.com... >> "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag >> news:MM9xf.5246$Kp.178@southeast.rr.com... >>> Can anyone suggest the best evm board for virtex-4 and linux? How has >>> people's experience been with it? Are USB drivers included in the linux >>> os >>> builds they provide? >>> >>> Thanks, >>> Clark >>> >> I may be mistaken but I think there are no Virtex4 linux ready currently >> shipping with both device and host support drivers for USB >> >> Virtex-4 based modules from >> http://www.hydraxc.com/ >> >> eg LX15, LX25 and FX12 based units are currently all shipping, but the >> included ucLinux reference design does not include USB drivers, this will >> be supplied later on, currently only some standalone USB firmware samples >> are included. >> >> There are possible other boards or modules with partial USB support, but >> with device and host (OTG) support already included I doubt that you find >> anything at the moment, you can possible find something with host support >> only >> >> Antti >> >> > > Interesting board! Do you know other "mini" modules? > > Many Thanks > Marco > there are, but not with so complete set of features on board. * memec mini-modules * suzaku * and one v4 module comes in CF card format * with Altera there one small format thing on the hydraxc webpage isnt much online, but there are also 2 different evaluation base boards available for easy getting started the low cost only has the connectors mainly, the high end base board has Virtex4+DDR2 and DVI out and header for camera AnttiArticle: 94446
Just try anode <= lclk; to see if the problem goes away.Article: 94447
"Antti Lukats" <antti@openchip.org> writes: > you can defenetly use jam/stapl with quartus, its a bit pain as it requres > CRC I think it can be ignored and after warning quartus programmer will > accept the file but its generically more pain than using SVF Is there a way to convert SVF to JAM/STAPL using Qaurtus? I was hoping I could just do something like quartus_pgm --play-svf file.svf or similar. > you can connect Cable III to the JTAG and use impact, or I could search my I'll just make a jumper and use the JTAG Techologies BV software... Thanks. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 94448
Hi everybody, I downloaded it at 250kb/s. Regards MehdiArticle: 94449
Brian, I give up. Just when I get serious with you (and treat you like the experienced designer you purport to be), you move onto another subject, and pour forth more vehemence. ... http://xgoogle.xilinx.com/search?getfields=*&btnG=Google+Search&output=xml_no_dtd&sort=date%3AD%3AL%3Ad1&ie=UTF-8&client=xilinx&oe=UTF-8&proxystylesheet=xilinx&filter=0&requiredfields=status%3Aactive&q=Virtex+II+DCI&submit2.x=28&submit2.y=9&submit2=Search&site=AnswersDatabase is the link to the 117 answers on Virtex II DCI... (to counter your "poorly documented" comment..." I acknowledge you had a less than satisfactory experience (with Virtex II DCI), and I am unlikely to change your mind about Xilinx, or their business practices, or Xilinx honesty policy. For that, I am truly sorry. Austin
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