Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 94350

Article: 94350
Subject: Re: How to keep the design from Synplify or XST optimizing
From: Ray Andraka <ray@andraka.com>
Date: Tue, 10 Jan 2006 11:48:57 -0500
Links: << >>  << T >>  << A >>
zephyrer wrote:

> thank u for ur tips,the synthesis command "syn_keep" "syn_noprune" and
> "syn_preserve" can prevent instances or reg or wire from optimizing.
> Now I hope to keep the net connections and stop optimizing the whole
> design, fit the design to a FPGA, is there any solution?
> 

You can also use syn_hier ="hard" for Xilinx in synplicity to force it 
to respect the component boundaries so that it doesn't share stuff 
between hierarchical components.

Article: 94351
Subject: Re: tcam implemented in fpga
From: "Peter Alfke" <peter@xilinx.com>
Date: 10 Jan 2006 08:57:14 -0800
Links: << >>  << T >>  << A >>

bjzhangwn wrote:
> Now I want a Tcam ,
I suppose you mean a Content Addressable Memory, normally referred to
as a CAM.
Search the Xilinx website. You will find, among others, XAPP201 and
XAPP202, and also interfaces to external CAMs.
Peter Alfke, Xilinx


Article: 94352
Subject: Re: tcam implemented in fpga
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 10 Jan 2006 18:13:24 +0100
Links: << >>  << T >>  << A >>
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag 
news:1136912234.087351.229830@f14g2000cwb.googlegroups.com...
>
> bjzhangwn wrote:
>> Now I want a Tcam ,
> I suppose you mean a Content Addressable Memory, normally referred to
> as a CAM.
> Search the Xilinx website. You will find, among others, XAPP201 and
> XAPP202, and also interfaces to external CAMs.
> Peter Alfke, Xilinx
>

I guess he means Ternary CAM, and for his application its implementation in 
FPGA would be real huge

Antti 



Article: 94353
Subject: Re: FPGA configuration time for PCI identification ?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 10 Jan 2006 18:15:22 +0100
Links: << >>  << T >>  << A >>
"sjulhes" <t@aol.fr> writes:

> Does someone has information on this allowed time ?

It's in the PCI spec. It's 2^25 clock cycles if memory serves me
right.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 94354
Subject: FPGA configuration time for PCI identification ?
From: "sjulhes" <t@aol.fr>
Date: Tue, 10 Jan 2006 18:22:28 +0100
Links: << >>  << T >>  << A >>
Hello,

We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits
90ns flash by a CPLD.
I try to find what time has the PCI IP to respond to PCI boot board
identification process before been ignored ?
This will give the time I have to configure my FPGA.

Does someone has information on this allowed time ?

Thanks.

Stéphane.



Article: 94355
Subject: Altera MAX-II: User logic access to USERCODE_REGISTER?
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 10 Jan 2006 18:23:01 +0100
Links: << >>  << T >>  << A >>

I would like to do something like:

module maxii (..pin1,pin2..);
...
output pin1;
output pin2;
...
assign pin1 = USERCODE_REGISTER[0];
assign pin2 = USERCODE_REGISTER[2];
...
endmodule

Which should cause pin1 and pin2 to change to reflect the values of
USERCODE_REGISTER scanned in through the JTAG port. Is this possible,
if so how do I access the USERCODE_REGISTER from my logic?

TIA
Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 94356
Subject: Xilinx Routing & Clock/Data Skew
From: "Brendan Illingworth" <billingworth@electrascan.com>
Date: Tue, 10 Jan 2006 09:24:42 -0800
Links: << >>  << T >>  << A >>
I am working on a timing simulation of an array of source synchronous
flip-flops with all D inputs connected to the same net. The design requires
a small (~10ps) skew between the arrival of the clock to each F/F. In
regards to this topology I have several questions:

1) Is there a means to specify a MINIMUM skew between elements? (Or a means
to create this effect?).

2) In operation, what degree of changes in skew can be expected? (The
simulator specifies skews of 5ps to 100ps between succssive F/F's what range
of values can be expected in operation?).


Thanks,
Brendan



Article: 94357
Subject: Re: ISE 8.1i WebPack available
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 10 Jan 2006 17:26:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
Christopher Cole <cole@scoob.coledd.com> wrote:
> I like the new Xilinx Webpack 8.1i interface under Linux, it works great.
> I am running the Webpack under Gentoo Linux with a 2.6.14 kernel.  The
> Impact tool works well with the parallel port under Linux.  I updated the
> Gentoo HOWTO-Xilinx at: 

> http://gentoo-wiki.com/HOWTO_Xilinx 

> with the steps that I took to get everything installed and working properly,
> including the kernel modules needed to get the parallel port JTAG working.

On Suse 10.0 with Kernel 2.6.13-15.7-default, Windriver 
WD700.tgz didn't compile. Insight UK offers a free download for WD702 after
registration:  
http://shop.directinsight.co.uk/catalog/product_info.php?products_id=722
udev is active on my Suse machine, I didn't have to disable it for windriver
to compile, so perhaps with 702 your FAQ needs to be revised with regards to
udev.

I hope XILINX will use ppdev for parallel port access sometimes, like
libusb could be used for the USB access. This windriver things is a constant
source of trouble...

I didn't had to change the DISPLAY variable as I had before up to 7.1. Is
setting $DISPLAY to :0 still needed on your setup?

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 94358
Subject: Re: PCI compliance ?
From: "Brian Davis" <brimdavis@aol.com>
Date: 10 Jan 2006 09:53:06 -0800
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
>
> Since you don't know this, I suggest you go and volunteer to chair a
> committee, and learn something about the real world.
>
 I already know plenty about the real world, thanks.

 Your suggestion that the bus loading specs of PCI are there
specifically to exclude FPGA vendors was, is, and remains, absurd.

  Almost as absurd as your previous posting tactic of repeatedly
claiming that you "meet all specs and standards" in spite of hard
facts to the contrary.

Brian


Article: 94359
Subject: Re: FPGA configuration time for PCI identification ?
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 10 Jan 2006 09:59:53 -0800
Links: << >>  << T >>  << A >>
Petter,

I had read somewhere 80ms was all the time you had before the PCI bus 
was definitely allowed to ignore you (forever).

2^25 clocks is considerably longer than this.  Even at 133 MHz.

Austin

Petter Gustad wrote:

> "sjulhes" <t@aol.fr> writes:
> 
> 
>>Does someone has information on this allowed time ?
> 
> 
> It's in the PCI spec. It's 2^25 clock cycles if memory serves me
> right.
> 
> Petter

Article: 94360
Subject: Re: Asynch. signal
From: "john" <conphiloso@hotmail.com>
Date: 10 Jan 2006 10:04:10 -0800
Links: << >>  << T >>  << A >>
Hi,

yes, I do not have any signal form USB device to tell me that the data
is valid or done or data is about to come. I have eight bit data line
and a clock signal. when the USB device ouputs the data it outputs
clock. else clock is zero and data is nothing. So, If I clock the whole
thing on the local clock then is there a chance that the local clock
will miss the buffer ready signal.

John
Ray Andraka wrote:
> john wrote:
>
> > Hi,
> >
> > Thanks for the reply! But do not have "we" signal or input pin
> > available. Please advice.
> >
> > John
> >
>
> Surely you have something that indicates the usb data is valid, no?
> 
> If not, then just clock the whole thing at your local clock.


Article: 94361
Subject: Re: PCI compliance ?
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 10 Jan 2006 10:16:50 -0800
Links: << >>  << T >>  << A >>
Brian,

Well, we have agreed to disagree:  you have labeled me "absurd" and I 
will consider you a "novice."

And please be so kind to keep us apprised of all of the "facts."

Austin

Brian Davis wrote:

-snip-

>  I already know plenty about the real world, thanks.

Article: 94362
Subject: Re: FPGA configuration time for PCI identification ?
From: "John McCaskill" <junkmail@fastertechnology.com>
Date: 10 Jan 2006 10:26:20 -0800
Links: << >>  << T >>  << A >>

sjulhes wrote:
> Hello,
>
> We have a 2VP40 ( 15.5Mbits configuration ) to configure through a 8 bits
> 90ns flash by a CPLD.
> I try to find what time has the PCI IP to respond to PCI boot board
> identification process before been ignored ?
> This will give the time I have to configure my FPGA.
>
> Does someone has information on this allowed time ?
>
> Thanks.
>
> St=E9phane.


For PCI 2.3, and revision 1.0a of the PCI-X spec:

100 ms from power valid to RST# high.

For PCI 2^25 clocks from RST# high to first configuration access.

For PCI-X 2^26 clocks from RST# high to first configuration access.

Regards,

John McCaskill


Article: 94363
Subject: Re: Breaking of Ethernet Frames
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 10 Jan 2006 10:42:04 -0800
Links: << >>  << T >>  << A >>
kedarpapte@gmail.com wrote:

> I am very new to the Ethernet area.
> I am trying to design and Implement an Ethernet switch or Multiplexer.

Read every link here to start with:
http://www.erg.abdn.ac.uk/users/gorry/course/syllabus.html

    -- Mike Treseler


Article: 94364
Subject: Re: Asynch. signal
From: mk<kal*@dspia.*comdelete>
Date: Tue, 10 Jan 2006 18:51:42 GMT
Links: << >>  << T >>  << A >>
On 10 Jan 2006 10:04:10 -0800, "john" <conphiloso@hotmail.com> wrote:

>Hi,
>
>yes, I do not have any signal form USB device to tell me that the data
>is valid or done or data is about to come. I have eight bit data line
>and a clock signal. when the USB device ouputs the data it outputs
>clock. else clock is zero and data is nothing. So, If I clock the whole
>thing on the local clock then is there a chance that the local clock
>will miss the buffer ready signal.

This doesn't make any sense. What device are you talking about ? I
think you're missing something in your reading of the datasheet. Is
the clock you mention the output of the usb clock recovery ? Are we
talking about FS or HS USB here ? Some more information would be
helpful to help you :-|


Article: 94365
Subject: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Tue, 10 Jan 2006 18:58:18 GMT
Links: << >>  << T >>  << A >>
http://direct.xilinx.com/direct/webpack/81/WebPACK_81i_SFD.sh

server maxes out at 30 kB / second (= > 7 hours)?
(My DSL can do > 10 x that).

Should I try some otrher time or leave it overnight?
Or is it so hot that now everybody is at it :-)?

Article: 94366
Subject: Re: Asynch. signal
From: Ray Andraka <ray@andraka.com>
Date: Tue, 10 Jan 2006 14:10:20 -0500
Links: << >>  << T >>  << A >>
john wrote:

> Hi,
> 
> yes, I do not have any signal form USB device to tell me that the data
> is valid or done or data is about to come. I have eight bit data line
> and a clock signal. when the USB device ouputs the data it outputs
> clock. else clock is zero and data is nothing. So, If I clock the whole
> thing on the local clock then is there a chance that the local clock
> will miss the buffer ready signal.
> 
> John
> Ray Andraka wrote:
> 
>>john wrote:
>>
>>
>>>Hi,
>>>
>>>Thanks for the reply! But do not have "we" signal or input pin
>>>available. Please advice.
>>>
>>>John
>>>
>>
>>Surely you have something that indicates the usb data is valid, no?
>>
>>If not, then just clock the whole thing at your local clock.
> 
> 

Ok, so the USB "clock" is really a data strobe.

Use that strobe signal to write the eight bit data line into a register 
and also to toggle an additional bit.  You might have to use 
falling_edge instead, depending on which is the active edge.

process(strobe)
begin
    if rising_edge(strobe) then
       usb_register <= usb_data;
       toggle_ff <= not_toggle_ff;
    end if;
end process;

then in your local clock domain, you want to resynchronize the toggle 
signal and then synchronously detect an edge on it to generate a 1 clock 
wide load pulse:

process(clk)
begin
    if rising_edge(clk) then
       sync_toggle <= toggle_ff;
       toggle_z <= syn_toggle;
       load <= sync_toggle xor toggle_z;
       if load = '1' then
          shift_register <= usb_register;
       else
          shift_register <= left_shift(shift_register);
       end if;
    end if;
end process;

That's all there is to it!  One sync register should be sufficient at 
usb data rates in current FPGAs to get your probability of a metastable 
upset down into the infinitesimal range.

Article: 94367
Subject: Re: ISE 8.1Evaluation
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 10 Jan 2006 20:15:34 +0100
Links: << >>  << T >>  << A >>
"Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag 
news:v9wwf.621$o7.562@newsfe3-win.ntli.net...
> Requires money = Buy
>
not exactly

has price tag = can be purchased (eg can buy)
has no price tag = can not buy, even if you have to pay to get it, and if 
you pay for the shipping then it doesnt mean you paid for the product - 
because if you paid for the products you must obtain some rights to the 
product, if you only paid for shipping then you dont get any rights and no 
warranty no return, etc..

also for example if you buy 1 PLD device from from Xilinx online shop, and 
take the ISE eval CD as side order then its free right?

you paid for the PLD device and for the shipping for the PLD device and you 
get in the same shipping the eval CD as well, wihtout paying a dime for it, 
of course, it would be better if free means free as no payment for product 
and no payment for shipping, but well the free CDs from Xilinx are not so 
free anymore as shipping charges apply.

> I don't want the webpack version as if I do decide to go for the tools, 
> the projects will be for the larger devices not supported by Webpack. I 
> want to be able to target the larger devices with my code now and run some 
> simulations.
>
> I hope this is precise enough.
>
> Rog.

yes it is precise enough, if you need big parts testing then you sure need 
the full eval not webpack

too my very surprise there was just a message on german forum

http://www.mikrocontroller.net/forum/read-9-282971.html#new

about ISE 8.1 FULL being on emule as free download !??

Antti
PS I dont even know what that emule is, really.
There was some mule character in some Asimov's book but I dont think this is 
related.





Article: 94368
Subject: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
From: "Antti Lukats" <antti@openchip.org>
Date: Tue, 10 Jan 2006 20:16:47 +0100
Links: << >>  << T >>  << A >>
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> schrieb im Newsbeitrag 
news:dq104s$h0r$1@news.datemas.de...
> http://direct.xilinx.com/direct/webpack/81/WebPACK_81i_SFD.sh
>
> server maxes out at 30 kB / second (= > 7 hours)?
> (My DSL can do > 10 x that).
>
> Should I try some otrher time or leave it overnight?
> Or is it so hot that now everybody is at it :-)?

try again, should be faster than that, I did download it also just for fun, 
download time less than 2 hours

Antti 



Article: 94369
Subject: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
From: Antti.Lukats@xilant.com
Date: 10 Jan 2006 12:08:45 -0800
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> I would like to do something like:
>
> module maxii (..pin1,pin2..);
> ...
> output pin1;
> output pin2;
> ...
> assign pin1 = USERCODE_REGISTER[0];
> assign pin2 = USERCODE_REGISTER[2];
> ...
> endmodule
>
> Which should cause pin1 and pin2 to change to reflect the values of
> USERCODE_REGISTER scanned in through the JTAG port. Is this possible,
> if so how do I access the USERCODE_REGISTER from my logic?
>
> TIA
> Petter

google: "cyclone bscan" - to find what I antti (me) have written about
this

http://wiki.openchip.org/index.php/Altera:JTAG

MAXII is similar to Cyclone, I have verified that in silicon

antti


Article: 94370
Subject: application running on the top of Linux on virtex-ii pro
From: "Eric" <dasani8888@hotmail.com>
Date: 10 Jan 2006 13:13:54 -0800
Links: << >>  << T >>  << A >>
Hi All,

I successfully ported Linux to the powerpc on a virtex-ii pro board.
Now I'm having trouble writing sample applications that can test
devices on the board (switches, LEDs, etc). Is there a way that we
can port elf files generated by EDK to run on Linux? I'm able to
cross compile simple programs using standard C libraries, but
things don't work out when I use Xilinx libraries. I've tried cross
compiling a sample program that tests some devices on the board,
but couldn't get libraries to work correctly. Is there any work needs
to be done to the libraries before I can use them? I'm new to this sort
of
embedded environment. Any pointers? Thanks plenty.


Article: 94371
Subject: Re: "failed to create empty document"
From: robnstef@frontiernet.net
Date: 10 Jan 2006 14:08:56 -0800
Links: << >>  << T >>  << A >>
Ray,
When this happens is there ANY process that is taking an obsurd amount
of CPU processing, like CSRSS.EXE?
Rob


Article: 94372
Subject: Re: ISE Timing
From: Russ Panneton <pannetron@hotmail.com>
Date: Tue, 10 Jan 2006 15:22:13 -0700
Links: << >>  << T >>  << A >>
Rob wrote:
> Hello.
> 
> How can I see what the the clock skew is between a set of register?  The 
> clock is an output of a DCM.  Also, how can I force the PAR to maintain a 
> certain timing spec?
> 
> Thanks,
> Rob 
> 
> 

Try placing a PERIOD constraint on the DCM output in which you are 
interested -- the precise time value isn't important.  The timing 
analyzer will report on that constraint and hopefully show you what you 
want to see.  You may need to use the "-v nnn" verbose reporting option 
(where nnn is the number of items to report) in the fanout is very large 
and you want to see everything.

Here's a link to some Xilinx documentation that may or may not help -- 
http://www.xilinx.com/xlnx/xil_tt_product.jsp?sProduct=Timing%2FConstraints

Cheers,

Russ

Article: 94373
Subject: Re: Downloading WebPack-8.1, server maxes out at 30 kB / second (= > 7 hours)?
From: "Leon" <leon_heller@hotmail.com>
Date: 10 Jan 2006 14:39:40 -0800
Links: << >>  << T >>  << A >>
Took me about 30 minutes. I do have 4 Mbit/s broadband, though.

Leon


Article: 94374
Subject: Re: "failed to create empty document"
From: Russ Panneton <pannetron@hotmail.com>
Date: Tue, 10 Jan 2006 15:42:58 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Mike,
> 
> It is like there is a limit on the number of files that can be open.  I 
> jsut ran into it trying to open Xilinx ISE7.  Memory usage was only at 
> around 790M out of 2GB.  It just wouldn't let Xilinx project manager 
> open.  Closing Synplify let me open Xilinx.

My money is on WinXP running out of available file or registry key 
handles.  You may get a hint on what failing by looking at the system 
event log under Control Panel -> Administrative Tools -> Computer 
Management -> System Tools -> Event Viewer -> System.

Some other interesting links:

http://support.microsoft.com/?kbid=870677
http://www.tauris.cc/windowsxp.htm

I dunno if either of those works or are even in the ballpark so use 
caution!!

Good luck,

Russ



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search