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Dear, I received last week a Xilinx USB Platform Cable. Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel 2.6.6-1.435.2.3smp, the precompiled driver is not suitable. I successfully made the cable working by using the Jungo windrvr6 driver. I successfully run impact and programmed more than 10 fpga and PROM. Then i tried to use XMD (we bought the cable for PPC405 debugging purpose) and the application apply a firmware update to the cable. Since nothing working, neither impact or XMD. When i try to detect JTAG chain in Impact, it give me a lot of "unknown" devices. This is my impact log : ************************************ CABLE DETECTION ************************************ // *** BATCH CMD : setPreference -pref UserLevel:NOVICE // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE // *** BATCH CMD : setPreference -pref UseHighz:FALSE // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION // *** BATCH CMD : setPreference -pref AutoSignature:FALSE // *** BATCH CMD : setPreference -pref KeepSVF:FALSE // *** BATCH CMD : setPreference -pref svfUseTime:FALSE // *** BATCH CMD : setPreference -pref UserLevel:NOVICE // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE // *** BATCH CMD : setPreference -pref UseHighz:FALSE // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION // *** BATCH CMD : setPreference -pref AutoSignature:FALSE // *** BATCH CMD : setPreference -pref KeepSVF:FALSE // *** BATCH CMD : setPreference -pref svfUseTime:FALSE // *** BATCH CMD : setMode -bs GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. CB_PROGRESS_START - Starting Operation. Connecting to cable (Parallel Port - parport0). WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall the cable drivers. See Answer Record 18612. Cable connection failed. Connecting to cable (Parallel Port - parport1). WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall the cable drivers. See Answer Record 18612. Cable connection failed. Connecting to cable (Parallel Port - parport2). WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall the cable drivers. See Answer Record 18612. Cable connection failed. Connecting to cable (Parallel Port - parport3). WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall the cable drivers. See Answer Record 18612. Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA. File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), 03FA. Max current requested during enumeration is 150 mA. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1018. CPLD file version = 0006h. CPLD version = 1648h. CB_PROGRESS_END - End Operation. Elapsed time = 7 sec. *********************************************** JTAG IDENTIFICATION *********************************************** // *** BATCH CMD : Identify PROGRESS_START - Starting Operation. Identifying chain contents ....read count != nBytes, rc = 20000015. read failed 20000015. '1': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. '2': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. '3': : Manufacturer's ID =Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part. '4': : Manufacturer's ID =Unknown , Version : 14 INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- GUI --- ************* Process Interrupted by User ************* Process Interrupted by User---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- write cmdbuffer failed 20000015. Validating chain... write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. Boundary-scan chain validated successfully. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. write cmdbuffer failed 20000015. I have tried to force CPLD update several times but i allways get the same working. Can someone help please. I there a possibilty to reprogram the CPLD with the default firmware ? Best regards, GillesArticle: 94251
I discovered that I had to provide feedback from CLK0 to CLKFB to get CLKFX from the DFS.. I dont know if this is a requirement, but at least it gave me the CLKFB I needed. <debashish.hota@gmail.com> wrote in message news:1136472616.867657.280820@g47g2000cwa.googlegroups.com... > Hi all, > > i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which > you need to provide a feedback clock for phase alignmen). So my DCM is > working in without feedback (internal as well as external) mode. > > I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most > of the time it works fine but sometimes after giving a reset to FPGA or > reprogramming the FPGA the DCM is not able to multiply the clock to > give a 32Mhz clock and gives the same input 16Mhz clock as the output. > > But according to Xilinx DCM datasheet, in DFS mode we should be able to > multiply or divide clocks with frequency > 1 Mhz. > > So if anyone has faced any such problem or if there is any synthesis > attribute which I need to set etc then please guide me. > > Thanks in advance > Debashish >Article: 94252
I called one of my design 'chef' just to symbolize that it was "cooking" all incoming signals into something "digestable". (at the same time thinking of Chef in the South Park series :) This name was never used in daily speech cause it was the only FPGA design, and I was the only FPGA programmer in our company at that time. I guess this naming was kinda inspired by the chipset of the Amiga computer wich I used to know very well. I also found the messages written on the PCB's mysteriously interesting :) <fourbeans@gmail.com> wrote in message news:1136477878.639809.167900@f14g2000cwb.googlegroups.com... > I've known lots of ASIC designers that name their device something cool > like vader or dilbert. Do people name their FPGA designs as well? > Anyone know how or why this got started other than the fact that EEs > are geeks? Was is driven by marketings folks, or maybe the mood the > designer was in at the time of the design such as ATI's Rage? > > Enjoy, > Beanut >Article: 94253
I can't figure out how to use alias to create vectors of arbitary signals... What I want to do is this (Using ISE 6) signal lcdbufadr:std_logic_vector(10 downto 0); alias lcdbufburst:std_logic_vector(2 downto 0) is lcdbufadr(1) & lcdbufadr(0) & lcdbufadr(8); but the compiler is complaining - what is the correct syntax, or can't it be done ?Article: 94254
On 8 Jan 2006 00:14:18 -0800, "Nitesh" <nitesh.guinde@gmail.com> wrote: >I had posted earlier my issues with Fpga card. > >http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74 > >The AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The >powerpc inside teh fpga has linux running..I have some data in my PLB >master/slave module which has to be transferred to the host pc. So I >was suggested to llok into DMA transfer part. I went through the >powerspan II manual . It doesnt provide the details of data cycle for >the DMA . i.e it only says to write the DMA configuration registers >with the source address , destination address... and then raisethe go >signal. Now my problem is that the source address needs to be the >on-board RAM address. I dont want to use the onboard RAM.I dont want to >use the powerpc either. I wanted to write a module in vhdl to do the >confguration adn the forward the data to the bridge. I dont know >whether this is possible. I > > I dont have experience in this field. How can I do a transfer of data >from my master/slave module to the host computer? >Is there a way ? You first need to find out if the PCI interface on your board has this capability. How is it implemented? One block diagram of an AMIRIX board shows an external PCI bridge, and a photo shows a chip marked "PLX" but I can't read the number. So start with the supplied documentation, and if that proves inadequate, look at the board, find the PLX chip, and go to http://www.plxtech.com/ for further information on that chip and example driver software. - BrianArticle: 94255
On Sun, 08 Jan 2006 23:26:47 -0500, Ray Andraka <ray@andraka.com> wrote: >Rob wrote: >> Does it always happen (not dependent on running applications) or only when >> you have certain applications running, like Aldec or Xilinx ISE? I'll >> forward your note onto to some XP people that I know and see what I get >> back. If I get back anything worth while I'll post it. >> >> Not that I'm an XP expert, but this kind of smells like a memory (mother >> board RAM) issue. Open up the Task Manager and take a look at available >> system memory when you start to experience this problem, just for grins. >> > >Rob, thanks! > >Hard to tell, If I am at the computer it is because I am doing design >work, which means one or more of those apps is open. It doesn't seem to >be tied to any one of those apps though. I've seem MSword do it too >with a long document (50 page book chapter with about 50 drawings). It >is as though there is a memory leak, but it isn't showing up on the task >manager. Closing apps one by one, watching Task Manager, might yield a culprit (sudden release of a GB or so). But this sounds more like W98 than XP. One of the apps isn't from that era by any chance? Stating the obvious, but maybe worth checking for malware. My own work machine doesn't even have a modem! :-) And when I later took a W2000 machine online, I was very glad of that... - BrianArticle: 94256
"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag news:dpteh3$9hk$1@amma.irisa.fr... > Dear, > > I received last week a Xilinx USB Platform Cable. > Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel > 2.6.6-1.435.2.3smp, the precompiled driver is not suitable. > I successfully made the cable working by using the Jungo windrvr6 driver. > I successfully run impact and programmed more than 10 fpga and PROM. > > Then i tried to use XMD (we bought the cable for PPC405 debugging purpose) > and the application apply a firmware update to the cable. > Since nothing working, neither impact or XMD. When i try to detect JTAG > chain in Impact, it give me a lot of "unknown" devices. > from 2 of cables here, one of them started to fail after firmware update, but multiply firmware updates did not help, etc.. to my very very very big surprise the reason for the failure was the Fairchild buffer chip on TMS being dead. so I ended up soldering a short circuit over it, then it worked again. you can test if your cable is electrically intact with the impact debug chain first make short TDO-TDI and check that the readback is echoed, then measure the TMS and TCK with some multimeter, and force them from impact hum,. if you CPLD is really bad bad then you may get communication error even before that > This is my impact log : > > ************************************ > CABLE DETECTION > ************************************ > > // *** BATCH CMD : setPreference -pref UserLevel:NOVICE > // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED > // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE > // *** BATCH CMD : setPreference -pref UseHighz:FALSE > // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP > // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION > // *** BATCH CMD : setPreference -pref AutoSignature:FALSE > // *** BATCH CMD : setPreference -pref KeepSVF:FALSE > // *** BATCH CMD : setPreference -pref svfUseTime:FALSE > // *** BATCH CMD : setPreference -pref UserLevel:NOVICE > // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED > // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE > // *** BATCH CMD : setPreference -pref UseHighz:FALSE > // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP > // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION > // *** BATCH CMD : setPreference -pref AutoSignature:FALSE > // *** BATCH CMD : setPreference -pref KeepSVF:FALSE > // *** BATCH CMD : setPreference -pref svfUseTime:FALSE > // *** BATCH CMD : setMode -bs > GUI --- Auto connect to cable... > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > CB_PROGRESS_START - Starting Operation. > Connecting to cable (Parallel Port - parport0). > WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall > the cable drivers. See Answer Record 18612. > Cable connection failed. > Connecting to cable (Parallel Port - parport1). > WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall > the cable drivers. See Answer Record 18612. > Cable connection failed. > Connecting to cable (Parallel Port - parport2). > WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall > the cable drivers. See Answer Record 18612. > Cable connection failed. > Connecting to cable (Parallel Port - parport3). > WARNING:iMPACT:2377 - Module parport_pc is not loaded. Please reinstall > the cable drivers. See Answer Record 18612. > Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA. > File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), > 03FA. > Max current requested during enumeration is 150 mA. > Cable Type = 3, Revision = 0. > Setting cable speed to 6 MHz. > Cable connection established. > Firmware version = 1018. > CPLD file version = 0006h. > CPLD version = 1648h. that is weird on WinXP the file version and CPLD version are the same as displayed > CB_PROGRESS_END - End Operation. > Elapsed time = 7 sec. > > *********************************************** > JTAG IDENTIFICATION > *********************************************** > > // *** BATCH CMD : Identify > PROGRESS_START - Starting Operation. > Identifying chain contents ....read count != nBytes, rc = 20000015. > read failed 20000015. > '1': : Manufacturer's ID =Unknown > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > '2': : Manufacturer's ID =Unknown > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > '3': : Manufacturer's ID =Unknown > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > INFO:iMPACT:1588 - '4':The part does not appear to be Xilinx Part. > '4': : Manufacturer's ID =Unknown , Version : 14 > INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > GUI --- ************* Process Interrupted by User ************* > Process Interrupted by > User---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > ---------------------------------------------------------------------- > write cmdbuffer failed 20000015. > Validating chain... > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > Boundary-scan chain validated successfully. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > write cmdbuffer failed 20000015. > > I have tried to force CPLD update several times but i allways get the same > working. > I dont think xilinx ever tried CPLD update on Linux, so get and Windows box and try again yes I know Linuxfans dont like this type of advice, but some things are the way they are, and FPGA tools come with Windows support in first line, and all Linux support is a bit behind, this may get better (for linuxfans) but currently there are less problems on non-linux hosts > Can someone help please. > > I there a possibilty to reprogram the CPLD with the default firmware ? > take the old firmware file from old Xilinx install replace it and force update that should write the old version 6.3 has CPLD version 0004 included, all never have CPLD ver 0006, if you dont have it I can send optionally the CPLD can be reprogrammed by another cable as the PCB inside the platform cable has an unfitted Cable IV header so you can connect another cable to it and program the CPLD I have a JEDEC readback of CPLD ver 0006 which I can send, if you need, but it is only helping if you have another working cable and are willing to open the platform cable casing > Best regards, > > Gilles -- Antti Lukats http://www.xilant.comArticle: 94257
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dptig7$jk$01$1@news.t-online.com... > "Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag > news:dpteh3$9hk$1@amma.irisa.fr... >> Dear, >> >> I received last week a Xilinx USB Platform Cable. >> Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel >> 2.6.6-1.435.2.3smp, the precompiled driver is not suitable. [snip] >> Firmware version = 1018. >> CPLD file version = 0006h. >> CPLD version = 1648h. > > that is weird on WinXP the file version and CPLD version are the same as > displayed sorry I meant displayed should be CPLD file version = 0006h. CPLD version = 0006h. anttiArticle: 94258
Antti Lukats wrote: > > No, I dont think your board is different of what I have and you can > not use JP2 for serial config, its not wired to proper pins > Oops, you're right; the Rev C. board pictures in the user's guide label those connector pins "MOSI, MISO" etc so I thought they'd brought out the serial boot pins. The schematic also labels that connector as "Alternate Programming", but I hadn't checked the FPGA pin connections. BrianArticle: 94259
From: "" <jonathan.a.clarke@gmail.com> Newsgroups: comp.arch.fpga Subject: Re: Help! FIR Filter - MATLAB fdatool - VHDL Date: Mon, 09 Jan 2006 05:04:35 -0800 Hi Emel, You could instead use Synplify DSP (http://www.synplicity.com/products/synplifydsp/) to generate either HDL or Verilog code for a filter design from a filter specification given to the fdatool in Matlab. The software is integrated into Matlab and allows you to develop more complex systems (which your filter could be a part of) for implementation on an FPGA using the block-based Simulink environment, and can generate code that is optimized for different FPGAs from both Altera and Xilinx. Best wishes, JonathanArticle: 94260
Hi, I have to acquire 9 couples of differential signals inside my Spartan3 fpga. How should I handle them? Should i use IBUFDS (with I and IB as true and inverted inputs, while O as my "decoded" output)? Is it 2.5V (with the inverted being -2.5V) the maximum allowed differential input voltage with XC3S200 FT256? Thanks, MarcoArticle: 94261
I am comparing 2s15 and lx25 now for a SCDMA BTS. But I heard that = Xilinx's step1 chips are engineering samples and with some bugges.=20 Is it true?=20 Can someone explain the step policy of xilinx for me? Thank you very much!Article: 94262
"Marco" <marco@marylon.com> schrieb im Newsbeitrag news:1136813430.918916.193820@f14g2000cwb.googlegroups.com... > Hi, I have to acquire 9 couples of differential signals inside my > Spartan3 fpga. How should I handle them? Should i use IBUFDS (with I > and IB as true and inverted inputs, while O as my "decoded" output)? Is basically yes > it 2.5V (with the inverted being -2.5V) the maximum allowed > differential input voltage with XC3S200 FT256? > Thanks, Marco > S3 doesnt allow any more 3.3V differential outputs, but for inputs I think 3.3V LVDS is still supported. just try out if not the tools will throw an error ah, there is no -2.5 of course, the inputs + and - should be in some allowed common mode DC range from somewhere inbetween 0 and 2.5V, swinging around the common mode voltage a few hundred millivolts -- Antti Lukats http://www.xilant.comArticle: 94263
>"Jude Wu" <mailwz@263.net> schrieb im Newsbeitrag > >news:dptq6c$8r7>$1@news.cn99.com... >I am comparing 2s15 and lx25 now for a SCDMA BTS. But I heard that Xilinx's >step1 >chips are engineering samples and with some bugges. >Is it true? >Can someone explain the step policy of xilinx for me? > >Thank you very much! ES is usually Step 0, but there are several die runs for each step, sometimes there is JTAG ID code change also, sometimes not. both ES (step 0) and non ES LX25 silicon works ok, we have used both the stepping doesnt mean that the earlier silicon has bugs, it has some behaviour that is explained in the documents and errata, if that issues have been taked care then a bitstream for lower stepping will be compatible with no changes in later stepping. well there are a few exceptions, where the ES bitstreams are not fully upwards compatible. from step 1, and above the compatibility is maintained ASFAIK AnttiArticle: 94264
Hi Sirs, For two days n a row, I've been trying to download Nios II Eval from Altera website, starting from here: https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp Or from here: https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp >From either url, the link directs me to here: https://www.altera.com/servlet/download?swcode=WWW-SWD-NIO2-51-ALL&referer=https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp And then, nothing happens. Can somebody help? Thanks, ------------------------------ Jaime Andrés Aranguren Cardona jaac@sanjaac.com SanJaaC Electronics Soluciones en DSP www.sanjaac.comArticle: 94265
Does anyone know when the Evaluation version of 8.1 is going to be available to buy? TIA, RogArticle: 94266
"Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag news:AUtwf.3$kt2.1@newsfe1-win.ntli.net... > Does anyone know when the Evaluation version of 8.1 is going to be > available to buy? > > TIA, > > Rog there is no eval to buy! the 8.1 webpack links are now online, but pointing to dev0 I bet as soon as Xilinx webmaster wakes up it will be fixed... -- Antti Lukats http://www.xilant.comArticle: 94267
An Evaluation version would cost me approx. USD20 in shipping. I was wondering when the Evaluation version would be there to obtain. Rog. "Antti Lukats" <antti@openchip.org> wrote in message news:dptpu5$c09$03$1@news.t-online.com... > "Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag > news:AUtwf.3$kt2.1@newsfe1-win.ntli.net... >> Does anyone know when the Evaluation version of 8.1 is going to be >> available to buy? >> >> TIA, >> >> Rog > > there is no eval to buy! > > the 8.1 webpack links are now online, but pointing to dev0 > I bet as soon as Xilinx webmaster wakes up it will be fixed... > > > -- > Antti Lukats > http://www.xilant.com >Article: 94268
Subhasri krishnan wrote: > Hi all, > I am designing a memory controller and I want to use concurrent auto > precharge. I am using a micron SDR-SDRAM ( > http://download.micron.com/pdf/datasheets/dram/sdram/64MSDRAMx32.pdf ). > The datasheet doesnot specify how to activate a row in bank m when the > current state is bank n. Is there a way I can specify the row that > should be activated? and which row will be activated (figure 24 in > pg:23) when current state of bank m is page active at T0 (same figure) > ? Please tell me where I can learn more about this. > Thanks for any help. > Subhasri > Precharging means 'closing' a row so that a different row in that bank can be opened. The auto precharge example in Figure 24 assumes that the rows are already activated - remember, there can be several rows active at the same time as long as each row is in a different bank. In Figure 24, there is a row active in Bank n and a row active in Bank m. Figures 3 and 4 on page 12 show how to activate a row. --- Joe Samson Pixel VelocityArticle: 94269
"Roger" <enquiries@rwconcepts.co.uk> schrieb im Newsbeitrag news:%guwf.64944$Cj5.57950@newsfe6-win.ntli.net... > An Evaluation version would cost me approx. USD20 in shipping. I was > wondering when the Evaluation version would be there to obtain. > > Rog. well, then be precise with wording eval version does not have a 'buy' price, shipping costs do apply, but it doesnt make the eval as 'purchaseable product' order webpack 8.1 links are there, and I assume you should be able to obtain the webpack from online download very soon, it should actually provide evaluation of almost all the featueres of the full ISE so try that first in case the 8.1 eval CD order is not available yet -- Antti Lukats http://www.xilant.comArticle: 94270
Brian Drummond wrote: > > Closing apps one by one, watching Task Manager, might yield a culprit > (sudden release of a GB or so). But this sounds more like W98 than XP. > One of the apps isn't from that era by any chance? > > Stating the obvious, but maybe worth checking for malware. > My own work machine doesn't even have a modem! :-) > And when I later took a W2000 machine online, I was very glad of that... > > - Brian The task manager isn't showing any unexpected large memory users, and doesn't indicate that I am running out of memory. The apps are all latest versions. I am also using zonealarm and Grisoft antivirus, and run spybot search&destroy. None of those are discovering any malware, doesn't mean there isn't any, just means they are not detecting any. My work machine doesn't have a modem either :-) , but it does have a network connection to a cable modem through 2 layers of hardware firewallsArticle: 94271
Please just buy the EDK. For the $500 its costs, the printf problem will be solved in about 30 minutes. The EDK its so much simple to do what you want. If you can't afford it and are a student, you can get a free University donation to the Lab. ma wrote: > Hello, > > I have a Veritex-4 PCI board and I like to program the PowerPC on it. I > don't have the EDK from Xilinx. Here are my questions: > > > > How can program the PowerPC without buying EDK? > > As I know the compiler and linker is free (part of GNU) where can I get them > for free? > > How can I download the compiled program to PowerPC? > > How can I get the output? For example if I write a hello world type of > program, can I see the STDIO on screen? > > > > Any help is much appreciated. > > > > Best regards > > > >Article: 94272
Instead of using INIT_XX=>"...." I would like to write like "INIT(W,A)=>D" where W is the buswidth and D is the initial value (including parity bus) at the port at adress A. This is a plain mapping function and maybe someone has done this before me so I dont have to rewrite it?Article: 94273
Hi all, At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed is 20 times lower than in the bram. I couldn't endure it. Who knows how to speed up the programming in the ddr sdram? Please help me. Thank you very much! AthenaArticle: 94274
Micron MT46V16M16 is the ddr sdram that I am using. Athena
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