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Machine vision morphological operators like erosion and dilation? Real time means that the machine keeps up with images, I suppose, rather than storing the images, processing them at a later time, and reporting and viewing the results at leisure. Brad Smallridge AiVision.comArticle: 92426
Has anyone been able to successfully simulate a test of the MGT on the Virtex-4? I've been trying to instantiate the GT11_custom for a while, and it just does not seem to work. Basically I've instantiated two MGT's and have tied them together via the RXN/P - TXN/P. I've tried to use 8B/10B encoding and that didn't seem to work. This lead me to strip the MGT completely and use it only as a SERDES device, yet it still does not seem to work. (Assuming that whatever data I send on TXData_IN is what should be on RXDOUT.) I've been told to try the Aurora primative and I've followed the "Getting Started" document and it will not simulate using a Virtex-4. However, if I choose a Virtex 2 device, such as in the example document, then it simulates fine. Is this an issue with the Virtex-4? If anyone out there has ever got the Virtex 4 to simulate the MGTs, can you please help me? Thanks, JPArticle: 92427
Andy Peters wrote: > damir wrote: > >>I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external >>single-port SRAM connected to the FPGA (Spartan II/III). >> >>Does anyone have similar FIFO controller (sync/async) implemented using >>VHDL? > > > A FIFO in a single-port RAM? Neat trick, although I suppose the slow > speed makes it do-able. Most Video systems are essentially FIFOs - the simplest ones just alternate R/W slots, at 2x the bandwidth - with the caveats that most of the available WRITE slots are ignored, and the READ slots will pause during non-display time zones. To ease the EMC, the WRITE slot should activate the WR address only when actually needed. Normally, what needs the most attention is the WR_Enable pulse setup and hold times, so that becomes narrower than the 1/2 time slot (50ns) Peter's idea of 50MHz state engine, would allow you to allocate 2 tw to read, and 3 tw to write, with a centred 20ns WRN pulse width, using simple sync designs - or you could go to 60MHz and do 3tw+3tw, - decreases tWRN to 16.6ns, but increases tRdCYC to 50ns..... -jgArticle: 92428
Is there any alternative to Cypress driver available in the source, or I'll have to go and write driver (WinXP) by myself :(((( I've done some windows drivers several years ago and I don't like it at all. Damir "Ricardo" <spamgoeshere1978@yahoo.com> wrote in message news:3v3qjgF137kthU1@individual.net... > damir escreveu: >> We have developed data acquisition system which uses Cypress FX2 as the >> USB 2.0 interface. State machine for control and conversion of data >> between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. >> The problem is that with higher data rates (up to 25 Mbit/s) we >> experience FX2 internal FIFO stalls and missing data on the receiving >> side. Small FIFO implemented inside FPGA does not help to resolve the >> problem. On the PC, data acquisition is implemented using CyAPI & CyUSB. >> USB bulk mode is used for transfer. >> >> As mentioned data rate is only a fraction of USB 2.0 bandwidth, I don't >> know if the mentioned problem is related to the implementation of the >> receiver side (CyAPI) or lacking capability to sustain such bandwidth >> within Cypress FX2. >> >> Did anyone have similar problems using FX2 and how you manage to solve >> it? >> >> I will appreciate any help to resolve this problem, if possible in >> software - hardware solution will require redesign of the PCB and >> implementation/addition of large size FIFO to buffer FX2 stalls (which >> may, according to our experience, extend up to 50 ms). >> >> Thanks, >> >> Damir >> >> >> > I use the SX2 and could get around 25Mbit/s of sustained transfer in bulk > mode, but remember that bulk transfers have absolutely no time guaranty. > Even interrupt and isochronous that should have timeliness have a > disclaimer in the USB specification that real timeliness is dependant upon > SO. Windows and Linux can take a very long time without giving the > processor to any specific task. I did no test at all regarding latency in > this case. Depending on how critical is the data, you may need over 1s of > buffering. Using drivers in windows i've seen sub-ms response times, but > there's no way to be sure it will allways be so. I think the Cypress > driver is quite slow also. In the test I achieved 25mBit/s the FPGA > driving the SX2 could deliver over 120Mbit/s to the SX2, which sould be > capable of even more.... > > RicardoArticle: 92429
has anyone used this board, what do you think of it? does anyone have a linux driver for it? a schematic? thanksArticle: 92430
[Please do not mail me a copy of your followup]
Having googled around, I see that there are a number of papers (and
even an out of print book) on bit-serial arithmetic and VLSI/FPGA.
Is there a library of arithmetic blocks that is freely available for
the Spartan II chip?
--
"The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ:
<http://www.xmission.com/~legalize/book/>
Pilgrimage: Utah's annual demoparty
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Article: 92431
[Please do not mail me a copy of your followup]
Has anyone implemented a Q-bus or Unibus bus interface logic in an
FPGA that is freely available or documented? I am interested in
making a board for an LSI-11 computer that looks to the LSI-11 like a
disk drive, but is really a communication circuit back to a PC that
serves the drive image from a file on the PC.
Any ideas on implementation strategies would be appreciated!
--
"The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ:
<http://www.xmission.com/~legalize/book/>
Pilgrimage: Utah's annual demoparty
<http://pilgrimage.scene.org>
Article: 92432After some thinking: 1. You can divide the input load by using "zero-delay buffer chips" with up to 8 outputs and very little skew betrween them. And you can even compensate for the (assumed constant) skew between the outputs.(see below) 2. You can drive all IDELAYs from the fabric, using internal fan-out. Again, you an compensate away the routing delay differences. The compensation is done by setting all IDELAY values be to the same, and then observing the parallel captured word. It should always be either all zeros or all ones. If it's different, change the responsible IDELAY accordingly. Obviously, this compensation deos not cover drift with temperature and Vcc. Peter Alfke, Xilinx ApplicationsArticle: 92433
Andy Peters wrote: > > A FIFO in a single-port RAM? Neat trick, although I suppose the slow > speed makes it do-able. > > -a > Andy, Sure, I've done that many times, as well as virtual multi-port memory. The key is to time multiplex the ports into the single port using a faster memory clock than the access rate you need on any one port. Damir, It isn't really a hard problem, you basically have two address counters muxed into the single address of the RAM. An additional up/down counter will give you the population count needed for a synchronous FIFO, and a little bit of extra logic to decode the flags from the population count is all that it takes. An async FIFO can only be approximated by a single ported memory, because by definition all accesses to the memory happen on the same clock domain. For an 'async' fifo you will need to implement a syncrhonous fifo in the memory with a small on-chip async fifo cascaded to the input or output to take care of the clock domain crossing.Article: 92434
Phil Hays wrote: > Ray Andraka <ray@andraka.com> wrote: > > >>This is not safe as presented, as you can't guarantee all the flip-flops >>in the counter will be released from reset on the same clock cycle. > > > Then please show how it fails. > > If bit 0, the LSB, is released last, then it works. None of the > other bits can go high until bit 0 goes high. Agree? > > If bit 1, the next bit, is released last, then the bit 0 goes high > first, reset is released, then it works. Agree? > > Even if two clocks could come into the LSB FF before the release of > reset to the next bit, then the count sequence would be: > > 0000 > 0001 > 0000 > 0001 > 0010 > 0011 > etc > > And it works. > > Same thing for each bit up to the MSB. > > > >>In Xilinx >>FPGAs, it is easier and more compact to use the SRL16 as a shift >>register to delay the reset, and it avoids the reset signal time of >>arrival issue inside the reset circuit. > > > I disagree. SRL16's are wonderful for logic, but have horrible > metastable charactistics. This really is a metastable problem, so > SRL16's are a bad idea. Use slice FFs to make a shift register. Or > use a SRL16, and follow it with FFs. > > The problem is that if the reset is released right at the clock edge at any one flip-flop, that flip-flop can go metastable, and can result in it landing in the '1' state instead of the '0' state. I saw this exact failure on an SDRAM controller provided as part of the infrastructure IP on one of the high-end 3rd Party FPGA boards two years ago. The fix, BTW, was to add a synchronizing flip-flop to make removal of the reset to the whole counter synchronous with the counter's clock. For the SRL16, yes, you are correct, the metastable performance sucks. I should have been more exact by stating the SRL16 should be preceded by a flip-flop. The SRL16 is essentially being used as a counter to delay the reset. You want the FF before the SRL16, as that is where the clock domain crossing is. You will also want a FF after the SRL16, but that one is for timing closure, not metastability reasons.Article: 92435
Richard wrote: >[Please do not mail me a copy of your followup] > >Has anyone implemented a Q-bus or Unibus bus interface logic in an >FPGA that is freely available or documented? I am interested in >making a board for an LSI-11 computer that looks to the LSI-11 like a >disk drive, but is really a communication circuit back to a PC that >serves the drive image from a file on the PC. > > Not on an FPGA (PDP-11 was before their time) but the bus protocol is quite simple. Unibus has separate data and address, Q-bus has multiplexed A/D. The master sends out an address and a transfer request, and when the target is done it sends an acknowledge. It is all async, there is no bus clock. JonArticle: 92436
Ray Andraka wrote: > Andy Peters wrote: > > > > > A FIFO in a single-port RAM? Neat trick, although I suppose the slow > > speed makes it do-able. > > > > -a > > > Andy, > > Sure, I've done that many times, as well as virtual multi-port memory. > The key is to time multiplex the ports into the single port using a > faster memory clock than the access rate you need on any one port. OK, of course you're right :) I wasn't thinkin'. I built an audio digital delay out of a CPLD, an audio CODEC (DAC and ADC in the same chip) and a couple of async SRAMs. Basically, it's a big FIFO. Two address pointers are maintained, one for read, one for write. Empty and full flags are irrelevant. A state machine, running at the CODEC MCLK frequency, handles interleaving the memory reads and writes. It's pretty neat. A microcontroller handles the interface to an LCD and a rotary encoder. It'd be a good homework assignment for a VHDL or Verilog class. -aArticle: 92437
I believe the PLB in GSRD design is special in a way that it supports only 1 master and 1 slave. This is done to save some space. For you purposes you need to use the regular PLB from EDK.Article: 92438
HI, In my mind, xaw files have to be used within your ISE project. You have to synthesize, translate, map and place&route before be able to generate an bitstream or an MCS file which then could be used to program your FPGA or PROM. If you have the ISE project, you should add this xaw file into it.Article: 92439
Softice would be able to do the trick but not a real easy program to master. "g.wall" <wallge@eng.fsu.edu> schreef in bericht news:dmi1pr$ksh$1@news.fsu.edu... > im trying to reverse engineer a windows driver > for a PCI fpga development board so i can use it on a linux machine (write > my own driver) > all i need are the command and control signals > in order to configure, do dma, reset, etc... > i need to capture these things as they are being sent from > the windows kernel to the PCI bus, then to the pci bridge on the board. > > anyone have any ideas?Article: 92440
<electronics_designer@hotmail.com> wrote in message news:1133256655.320119.255470@f14g2000cwb.googlegroups.com... > > Frank schreef: > > > The machine is 16702B Logic analyzer, but the module inside > > is 16750A 400MHz State 2GHz Timing zoom 4MSa Analyzer. > > I am pretty new to this machine, where can I download the > > operating manuals? > > Seach the agilent website: > http://www.agilent.com/ > > Beste Regards, > Roel > Thank you. I have got the manual for 16750A.Article: 92441
Gabor - There are no TIG constriants on the nets. I don't see any conflicting constraints that would move the signals into this 'unconstrained period' section of the report. I'm suspecting a bug in the Xilinx tools, but I'll keep poking around a bit. John ProvidenzaArticle: 92442
[Please do not mail me a copy of your followup]
Jon Elson <jmelson@artsci.wustl.edu> spake the secret code
<438CE854.8010104@artsci.wustl.edu> thusly:
>Richard wrote:
>>
>>Has anyone implemented a Q-bus or Unibus bus interface logic in an
>>FPGA that is freely available or documented? [...]
>>
>Not on an FPGA (PDP-11 was before their time) but the bus protocol
>is quite simple. [...]
Well, I didn't mean to imply that the FPGA was concurrent with the
PDP-11 :-), I was more hoping that another retro computing hobbyist
would have made something I could bootleg!
I suppose I'll have to do my own bus handshake implementation from the
Q-bus docs (I think my processor or peripheral handbook that came with
the 11/03 has one in there somewhere).
I wonder how hard it would be to get a PCB fabbed with the bus edge
connector?
--
"The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ:
<http://www.xmission.com/~legalize/book/>
Pilgrimage: Utah's annual demoparty
<http://pilgrimage.scene.org>
Article: 92443Hello Peter, I found your appnote about async fifos: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=pa_fifo Very interesting and helpful, but one thing is not quite clear to me. You write: "FULL is of interest only to the write logic, where it must stop further writes. FULL goes active as a result of the last write operation, which makes the rising edge of FULL a synchronous signal, [...] Therefore, we only need to synchronize the falling edge of FULL..." Then you describe how to make the falling edge synchronous to the write clock. But why is this necessary? If I connect the writing system to this async falling edge signal directly what would be the problem? An "again availabe fifo" possible would be detected one clock earlier but this shouldn't be a problem, because the effect (falling edge of FULL) is still behind the cause (read pointer was increased). Where is my error? Thanks, MichaelArticle: 92444
Hi all, At present I am using EDK7.1 to do projects. By EDK I get a file "download.bit". If i use the "impact" of ISE7.1, i can download this file to the Virtex-ii Pro50 fpga board(produced by memec insight), but the file is in ram, so I have to download it every time when the power is on. However, I want to download the file in prom or flash once, and make the the system run every time when the power is on. According to EDK document "Chapter12 Programming flash memory", I think it is possible. However i couldn't find the prom on the fpga board when using the impact to check the device. Or maybe I can use flash or system ACE, but my flash is the one I said at the beginning, It is not OK according to the edk document. I will do some tests with system ACE. Cheers. Thank you! AthenaArticle: 92445
I did one in a Xilinx XC3064... many, many years ago. Unfortunately, I ditched all the documentation a few years ago... and have done a complete brain purge. Might still have the DEC documentation, though. I'll check on Wednesday. It wasn't too hard of a bus to interface to and is quite slow. Good luck, Ed "Richard" <legalize+jeeves@mail.xmission.com> wrote in message news:dmiiik$vqn$2@news.xmission.com... > [Please do not mail me a copy of your followup] > > Has anyone implemented a Q-bus or Unibus bus interface logic in an > FPGA that is freely available or documented? I am interested in > making a board for an LSI-11 computer that looks to the LSI-11 like a > disk drive, but is really a communication circuit back to a PC that > serves the drive image from a file on the PC. > > Any ideas on implementation strategies would be appreciated! > -- > "The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ: > <http://www.xmission.com/~legalize/book/> > Pilgrimage: Utah's annual demoparty > <http://pilgrimage.scene.org>Article: 92446
Michael, FULL is a control signal for the writing (and EMPTYis a control signal for the reading). As I said, the leading edges are naturally derived from the appropriate clock, and are thus synchronous. The falling edges are caused by the "wrong" clock, and can thushave any weird phase relationship with the important clock. You do not want the FULL flag go away in an asynchronous way, since that might "confuse" the write logic, whether it can or cannot write at this moment. And the trailing edge of EMPTY should clearly communicate with the read logic, in an unambiguous way. These flags must be interpreted correctly for many millions of times, any ambiguity will bite you, sooner or later. Usually in the worst way (Murphy's Law). Peter AlfkeArticle: 92447
I'm running Xilinx ISE Webpack 7.1.04i with ISE 7.1 IP Update 3 installed on Windows XP SP2. When I run Core Generator and try to instantiate a core (e.g. Single or Dual Port Block Memory), there's a popup window saying 'Launching IP Customizer', and then another popup window saying Exception encountered. After pressing OK, status bar shows 'An Error occured during customization' and nothing else happens. Adding a core from the Project Navigator produces a similar result (without popup windows) and the status window shows 'Customizing IP... An Error occurred during Customization.' The same error occurs for many different cores (but not all), and there is no apparent regularity with respect to what cores (versions, or types of cores) cause the exception, and which don't. It also doesn't matter which device family I am targeting (I've tried Virtext-4 and Virtex-II Pro). I have tried running CoreGen with limited memory (As suggested at http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=20708 , but that doesn't help). Has anyone encountered a similar problem, or knows of any workarounds? Regards, FredArticle: 92448
Hi - First off, I've got to commend you for asking this question. Lots of first-time managers don't realize they need to build a skill set until after their first project. Good for you. I can't answer all your questions, but here are a few comments about maintaining schedules. Maybe it's been improved, but after my last experience with Microsoft Project in the mid-nineties, I vowed never to use it again. Granted, I winge and whine about all MS tools, but Project has got to be the least intuitive, most time-consuming tool I've ever encountered (and I'm including CAE tools in the mix). You want to spend time refining the schedule, not learning the peculiarities of the scheduling tool. Try to use a simpler approach, if you can. Joel Spolsky recommends using Excel; the following article may give you some ideas: http://www.joelonsoftware.com/articles/fog0000000245.html After my experience with Project, I went on the lookout for simple scheduling tools that weren't sophisticated enough to keep trying to "help" me. One that I've used successfully is Kidasa Milestones (www.kidasa.com), which costs $60 and, to its credit, does very little compared to Project. Finally, one engineer I worked with a while back made what I'd consider a key insight: the most important items on the schedule are the transfer points, i.e., dates on which you transfer work to someone else, or someone else transfers work to you. You can tell they're important by observing how much effort people put into trying to avoid filling them out on the schedule. Bob Perlman Cambrian Design Works On 29 Nov 2005 07:53:39 -0800, gretzteam@hotmail.com wrote: >Hi, >I just got chosen as 'project manager' for our next project. It seems >like most people feel 'sorry' for me around here... We are designing a >moderately large mostly digital asic and the team consists of about 6 >people. I've never managed anything before and most of the people in >the team are more senior designer than me. Right now, things are >decided from hallway conversations, and nothing is really written down >in terms of schedule and who-does-what... > >I wonder what tools if any that people use to manage a project. Is >something like MS-Project any good? I understand that the schedule we >would put in place will never hold, but I figure it's better to have >something than nothing. Also, what do people use to track down bugs and >issues. The chip is divided in 6-7 blocks, each will be assigned to >one-two person. Where should I gather the information coming out of the >weekly meeting - schedule slip, bugs to be fixed etc...email? >ms-project? hallway? > >Thanks a lot, > >DaveArticle: 92449
>No matter what, if you track the actual schedule against your original >estimate you can at least have an estimate of when you'll actually be >done. Not only can you use this estimate to motivate the troops, but >you can use it to warn your boss that things aren't going as fast as >expected. How well does that work? I'd expect it would give horrible results in two common cases. (Maybe just looking at the same thing two different ways.) One is the one-last-bug problem. All the module tests go great but then it doesn't work when you put it together. The other is that halfway through a project, the nature of the work changes. You shift from writing code to integrating/checking. Knowledge of how well things worked during the first mode doesn't tell you anything about how good your estimates for the second mode will be. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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Compare FPGA features and resources
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