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GPE wrote: > I did one in a Xilinx XC3064... many, many years ago. > Unfortunately, I ditched all the documentation a few years ago... and have > done a complete brain purge. Might still have the DEC documentation, > though. I'll check on Wednesday. > > It wasn't too hard of a bus to interface to and is quite slow. > > Good luck, > Ed > I did interfaces many years ago for both buses using PAL's for logic and 74F-series parts for bus drive. Probably 5V 74FCT parts would also work. If you're serious about Unibus, you'll need to know that the connector pin-out in the DEC documentation is for the bus extender cable and not where a board plugs in. A and B connectors are not used for plug-in cards, only C, D, E and F. I got a copy of the magic document from someone who got it from someone who did PC board work for DEC. I don't have any of my documentation now except for the Unibus pinout. You'll need a copy of the board mechanicals. For Qbus there used to be prototyping breadboards available with holes on 0.1 x 0.1" centers. If you check with some hobby places like Jameco there may still be such things available if you want to breadboard your design or just lay out a "daughtercard" to wire down to the breadboard. Good Luck, GaborArticle: 92476
Krzysztof Przednowek wrote: > g.wall napisal(a): > > im trying to reverse engineer a windows driver > > for a PCI fpga development board so i can use it on a linux machine > > (write my own driver) > > all i need are the command and control signals > > in order to configure, do dma, reset, etc... > > i need to capture these things as they are being sent from > > the windows kernel to the PCI bus, then to the pci bridge on the board. > > > > anyone have any ideas? > > If You have PCI board with FPGA, RAM and some inferface to second PC, it > would be easier to do it in hardware. > > Best Regards > Krzysztof Przednowek Easiest is to get hold of a VMETRO or CATALYST PCI bus analyzer. You can probably rent one.Article: 92477
Morten Leikvoll wrote: > Setting these attributes: > > attribute equivalent_register_removal: string; > attribute equivalent_register_removal of busA,busB: signal is "no"; > > where the buses are 96bit causes a couple of minutes of warning flood for > every permutation for bit m,n.. Is there a way to supress these warnings? I > dont want these merged for timing reasons. Try setting the environment variable: XIL_XST_HIDEMESSAGES This worked in a similar case for me on ISE 6.1 where I have a 64 bit bus and ran for more than a couple of minutes as I recall.Article: 92478
Antti Lukats wrote: > <allanherriman@hotmail.com> schrieb im Newsbeitrag > news:1133357961.011069.169040@g44g2000cwa.googlegroups.com... > GaLaKtIkUsT wrote: > > Hi, > > I just succesfully installed ISE BaseX on Linux. All is OK. > > BUT the ISE simulator is not present in the list of available > > simulators in project properties. > > Please help! > > > > Cheers > > Mehdi. > > The ISE 7 Feature Guide document > http://www.xilinx.com/ise/devsys_feature_guide.pdf > says that Modelsim is "Sold as an Option." > > Contact your Xilinx distributor. > Or you can buy a real copy from here: > http://www.model.com/ > > Regards, > Allan > -------------- > > The OP asked about the ISE built in simulator not about modelsim! > ISE Simulator possible only supported on windows version (in 7.1). Ah, yes. How is the built in simulator? Is it worth using? Regards, AllanArticle: 92479
<allanherriman@hotmail.com> schrieb im Newsbeitrag news:1133359770.522159.135600@g49g2000cwa.googlegroups.com... > Antti Lukats wrote: >> <allanherriman@hotmail.com> schrieb im Newsbeitrag >> news:1133357961.011069.169040@g44g2000cwa.googlegroups.com... >> GaLaKtIkUsT wrote: >> > Hi, >> > I just succesfully installed ISE BaseX on Linux. All is OK. >> > BUT the ISE simulator is not present in the list of available >> > simulators in project properties. >> > Please help! >> > >> > Cheers >> > Mehdi. >> >> The ISE 7 Feature Guide document >> http://www.xilinx.com/ise/devsys_feature_guide.pdf >> says that Modelsim is "Sold as an Option." >> >> Contact your Xilinx distributor. >> Or you can buy a real copy from here: >> http://www.model.com/ >> >> Regards, >> Allan >> -------------- >> >> The OP asked about the ISE built in simulator not about modelsim! >> ISE Simulator possible only supported on windows version (in 7.1). > > Ah, yes. How is the built in simulator? Is it worth using? > > Regards, > Allan > almost useless in 7.1, maybe it is better in the 8.1 AnttiArticle: 92480
I'm not talking about the ModelSim but about the "ISE Simulator". I bought ISE BaseX because in the http://www.xilinx.com/ise/devsys_feature_guide.pdf file, in the Verification section, the ISE Simulator Lite in marked YES. But it seems that it is not included with the Linux version of ISE BaseX.Article: 92481
Ok ... So what simulator to use?
-I bought the "MicroBlaze & PowerPC Development Kit" (with ML403
Board).
-I'm using Linux as OS.
-I'm a PHD Student who decided to make a sacrifice by buying that
kit. I can't afford ModelSim PE/SE (since it seems that XE is not
available on Linux).
I'm really confused and unhappy with that :(
Mehdi
Article: 92482"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1133362132.612987.233320@g49g2000cwa.googlegroups.com... > Ok ... So what simulator to use? > -I bought the "MicroBlaze & PowerPC Development Kit" (with ML403 > Board). > -I'm using Linux as OS. > -I'm a PHD Student who decided to make a sacrifice by buying that > kit. I can't afford ModelSim PE/SE (since it seems that XE is not > available on Linux). > I'm really confused and unhappy with that :( > > Mehdi > it seems that you are forced to use either some free simulator or modelsimXE on Windows OS. AnttiArticle: 92483
hi everybody I'm learning two ways of describing a system .... Either by using systemC and the other way, VHDL ! What are the differences, the real advantages of one compared to the other ?=20 thx T=F4FArticle: 92484
GaLaKtIkUs wrote: > Ok ... So what simulator to use? > ... You can try at http://www.symphonyeda.com/ there is free version with some speed limit (and perhaps some other limit) but if you use it "for fun" then it's ok! Regards SandroArticle: 92485
Richard wrote: > [Please do not mail me a copy of your followup] > > Jon Elson <jmelson@artsci.wustl.edu> spake the secret code > <438CE854.8010104@artsci.wustl.edu> thusly: > > >Richard wrote: > >> > >>Has anyone implemented a Q-bus or Unibus bus interface logic in an > >>FPGA that is freely available or documented? [...] > >> > >Not on an FPGA (PDP-11 was before their time) but the bus protocol > >is quite simple. [...] > > Well, I didn't mean to imply that the FPGA was concurrent with the > PDP-11 :-), I was more hoping that another retro computing hobbyist > would have made something I could bootleg! > > I suppose I'll have to do my own bus handshake implementation from the > Q-bus docs (I think my processor or peripheral handbook that came with > the 11/03 has one in there somewhere). > > I wonder how hard it would be to get a PCB fabbed with the bus edge > connector? There was a discussion of this on S.E.D. quite recently with one of it's denizens successfully getting a board with gold fingers fabricated at a very reasonable price. X-Posted to s.e.d. for comments Cheers PeteS > -- > "The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ: > <http://www.xmission.com/~legalize/book/> > Pilgrimage: Utah's annual demoparty > <http://pilgrimage.scene.org>Article: 92486
"Frank" <Frank@Frank.com> wrote in message news:dmk525$34f$1@reader01.singnet.com.sg... > Ah! I understand what you mean now. PHY_EN is a stable signal, while my > clock > period is 25ns, in each frame, digital side is sending some 1200 I/Q > samples, > one pair of samples each cycle and unchanged throughout the clock cycle. > > From the datasheet of ADC, I don't see there is any Rd or CD signal, it's as > plain as ADC outputs are hold stable and change every 25ns. That is correct. The rising edge of ENCa and b (clock) sample the signal and on the falling edge, a valid word can be read from the databus. So your analyzer should trigger on the falling edge of the ENC signal MeindertArticle: 92487
On Fri, 25 Nov 2005 21:16:17 +0100, Olaf Petzold <olaf@mdcc-fun.net> wrote: >Hi, > >if I synthese the followng code (substract using two's-complement and >adder) using xst and then have a look to the RTL schematic, the co >output is on ground and a 16bit adder is infered. The carry out (co) >is the interesting signal for me. Did I wrote wrong code (TB not yet)? >How to correct it? BTW, is there a way to 'tune' this entities >especially to avoid such castings and conversations? Yes there is: first note that numeric_std "signed" type is conveniently defined to be 2's complement, so it's a better choice than "unsigned" for your application; then note that if ports a, b, diff were signed, then diff <= b - a; would do the job. The only reasons go into more detailed manipulations are for exercise, OR if you need some other arithmetic, i.e. 1's complement or sign+magnitude. Then you could wrap that up in a "numeric_std" lookalike library, and let it support (e.g.) S+M subtraction as easily as "b-a"... - BrianArticle: 92488
Does anyone know if it's possible to download older versions of the Quartus web edition, such as 4.0 or 4.1? I'm inheriting a design which allegedly doesn't work in the current version...Article: 92489
Hi, i need to modify the GPIO IP (opb_gpio) (Xilinx EDK7.1) to work like a FIFO (only for input). The IPIF IP can ba configured with fifos! Can anybody help? Best regards, MichaelArticle: 92490
Without knowing either real well, at least VHDL can be used to synthesize HW with tools mentioned here. I never heard of systemC synthesis but I bet it simulates faster. my 1cArticle: 92491
ar_kf@yahoo.com wrote: > Hi every one, > > It seems that implementation of DSP algorithm In simulink is possible > not only for TI DSPs > but also XILINX FPGAs. > > I intend to implement a baseband 64 QAM modem with MATLAB/SIMULINK. > It should be added that the bandwidth of afforementioned modem is 8 KHz > and about 64 Kbps. > > It wuold be highly appreciated if some one informe me about the pros > and cons of the two mentioned solutions. > Alireza, it is a matter of numbers, the size of the manufactured batch and the costs of them. You need to be fluent in both technologies , DSP & FPGA, to actually have the choice. Otherwise you spend another couple months on the technology and its tools itself. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 92492
cs_posting@hotmail.com wrote: > Does anyone know if it's possible to download older versions of the > Quartus web edition, such as 4.0 or 4.1? I'm inheriting a design which > allegedly doesn't work in the current version... > Even if it was, would the license keys fit ? A reason to get the professional version... Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 92493
Weddick schrieb: > When using a xilinx DCM, I receive the following warning - > Xst:753 - ... Unconnected output port 'CLK2X' of component 'DCM'. > > Is there someway to let XST know that I dont want anything connected to that > port. There is about 6 ports on the DCM that I don't intend to use. Yes, it's annoying. 'port => open' doesn't suppress the warning. cheers GuntherArticle: 92494
Hi JP, The Aurora core's example testbench(sample_test) has been extensively tested and should work out of the box. Can you please give me some details about the design that you generated from CORE Gen? This will help me debug your problem. 1)What line rate and data width did you choose. 2)Is this a single lane design? 3)Which simulator are you using? 4)Are you running the example simulation provided(sample_test.do)? The instructions for running this simulation are provided in the Getting started Guide. Thanks, Nanditha "JarJarJP12" <jpnguyenk@gmail.com> wrote in message news:1133296898.478227.3900@o13g2000cwo.googlegroups.com... > Has anyone been able to successfully simulate a test of the MGT on the > Virtex-4? I've been trying to instantiate the GT11_custom for a while, > and it just does not seem to work. Basically I've instantiated two > MGT's and have tied them together via the RXN/P - TXN/P. I've tried to > use 8B/10B encoding and that didn't seem to work. This lead me to > strip the MGT completely and use it only as a SERDES device, yet it > still does not seem to work. (Assuming that whatever data I send on > TXData_IN is what should be on RXDOUT.) > > I've been told to try the Aurora primative and I've followed the > "Getting Started" document and it will not simulate using a Virtex-4. > However, if I choose a Virtex 2 device, such as in the example > document, then it simulates fine. > > Is this an issue with the Virtex-4? > > If anyone out there has ever got the Virtex 4 to simulate the MGTs, can > you please help me? > > Thanks, > > JP >Article: 92495
Have you contacted Xilinx directly about this? They have a contact email address on the GSRD webpage: http://www.xilinx.com/gsrd/ Paul electronics_designer@hotmail.com wrote: > > Hello, > > As I would like the Ethernet performance from the GSRD design in the > ML403 reference design, I would like to merge them into a single > system. I tried to use the DCR2OPB to connect the OPB bus with all the > slave's, but that will take me some more time to change all lot of > address ranges. Therefore I just took a PLB2OPB bridge and attached it > to the DPLB bus of the processor, but that gave an error in EDK "more > than 1 slave connected to PLB bus .. ". Does someone know what's wrong? > > Does someone maybe have a merged version for me ? > > Best Regards, > RoelArticle: 92496
I wouldn't modify the opb_gpio, I would use the IP Import Wizard in EDK to create a new peripheral that includes the IPIF FIFOs. I've done this several times myself. Paul Michael Bodenbach wrote: > > Hi, > > i need to modify the GPIO IP (opb_gpio) (Xilinx EDK7.1) to work like a > FIFO (only for input). The IPIF IP can ba configured with fifos! > > Can anybody help? > > Best regards, > > MichaelArticle: 92497
g.wall schrieb: > im trying to reverse engineer a windows driver > for a PCI fpga development board so i can use it on a linux machine > (write my own driver) > all i need are the command and control signals > in order to configure, do dma, reset, etc... > i need to capture these things as they are being sent from > the windows kernel to the PCI bus, then to the pci bridge on the board. Get any board that connect an FPGA to a PCI connector. This one would do: http://www.enterpoint.co.uk/moelbryn/raggedstone1.html Plug it into the same PCI-bus that your target board resides on. Use chipscope to display the PCI waveforms. You can trigger on the base address of the board you are interested in together with a falling edge of FRAME . Kolja SulimmaArticle: 92498
[Please do not mail me a copy of your followup]
hmurray@suespammers.org (Hal Murray) spake the secret code
<vaadnSJVHo9ezBDeRVn-hQ@megapath.net> thusly:
>>I suppose I'll have to do my own bus handshake implementation from the
>>Q-bus docs (I think my processor or peripheral handbook that came with
>>the 11/03 has one in there somewhere).
>
>Does it have the specs for the bus transcievers? I remember using
>some special DEC chip.
I do recall seeing the specs for the DEC bus trainceiver chip in the
handbook, yes.
--
"The Direct3D Graphics Pipeline"-- code samples, sample chapter, FAQ:
<http://www.xmission.com/~legalize/book/>
Pilgrimage: Utah's annual demoparty
<http://pilgrimage.scene.org>
Article: 92499Frank schrieb: > bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode, > bit 8,6,3,2 switches during > active, stick to 0 during idle (I expect 9:2 of both channel to behave in > this manner), bit 1:0 are > switching during idle and active (noise during idle mode). > > I double checked my settings, but found nothing wrong. How can I proceed > now? Forget the individual bits, look at the binary values in total! As I told you before, noise of an arbitrary low value can toggle all bits of the ADC. There is nothing wrong with that. If your voltage is just between 0 (0x000) and -1 (0x3FF) an error of -epsilon will result in an output of -1 and an error of +epsilon will result in an output of 0 for any epsilon greater 0. So, even if your noise level is one electron charge you can see flipping bits. Look at the binary values (all bits together!) and determine the magnitude of the noise. If it is 1 LSB, move on. Nothing to see here. If it is small, but greater than 1 LSB try to answer why you believe the analog noise on your board is smaller than what you see in your measurement. Kolja Sulimma
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