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mk wrote:
> SystemC is at version 2.1 with a free library: http://www.systemc.org
http://www.systemc.org/web/sitedocs/membership_levels.html
Free with a $4000 membership.
-- Mike Treseler
Article: 92526On Wed, 30 Nov 2005 20:42:53 -0800, "Mike Treseler" <mike_treseler@comcast.net> wrote: >mk wrote: > >> SystemC is at version 2.1 with a free library: http://www.systemc.org > >http://www.systemc.org/web/sitedocs/membership_levels.html > >Free with a $4000 membership. You don't have to be a member. You just have to be a "licensee". I certainly didn't pay $4K. http://www.systemc.org/account/register.phpArticle: 92527
"Gob Stopper" <Noone@anywhere.net> wrote in message news:oBpjf.25219$ih5.20065@dukeread11... > > While you're at it, you should order (for free) a CD with the latest SW: > > http://software.cos.agilent.com/LogicAnalyzerSW/ > > Al > > P.S. You'll probably want to install it after you get it :-) Well, the manual is pretty straightforward and I am getting on it after looking at the logic analyzer itself, as simple as switching from windows to linux. Thank you for the software link, I will forward it to the machine admin.Article: 92528
"Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message news:11orioqaohu3v71@corp.supernews.com... > "Frank" <Frank@Frank.com> wrote in message > news:dmk525$34f$1@reader01.singnet.com.sg... > > Ah! I understand what you mean now. PHY_EN is a stable signal, while my > > clock > > period is 25ns, in each frame, digital side is sending some 1200 I/Q > > samples, > > one pair of samples each cycle and unchanged throughout the clock cycle. > > > > From the datasheet of ADC, I don't see there is any Rd or CD signal, it's > as > > plain as ADC outputs are hold stable and change every 25ns. > > That is correct. The rising edge of ENCa and b (clock) sample the signal and > on the falling edge, a valid word can be read from the databus. So your > analyzer should trigger on the falling edge of the ENC signal > > > Meindert > > I was aware of this, however now I am asynchronously sampling at 400MHz, thus I am expecting each I/Q sample to be stable and correct for at least 22.5ns assuming the LA has miscaptured for one 2.5ns cycle.Article: 92529
Hi All, Can anyone please tell me about some good links or documents paprs etc. on Implementing Ethernet Multiplexers using FPGAs THanks & Regards KedarArticle: 92530
Hi All, Can anyone please tell me about some good links or documents, paprs, Case Studies etc. on Implementing Ethernet Multiplexers using FPGAs THanks & Regards KedarArticle: 92531
"Eric Smith" <eric@brouhaha.com> wrote in message news:qhacflpr6b.fsf@ruckus.brouhaha.com... > If I change one input to a LUT, and leave the other three inputs > unchanged, > such that both the original and new output will be the same (e.g., both > '1'), > can there be a glitch in the output? Hi Eric, You got a good answer from Peter. However, my smarty pants response is to never put yourself in a position where you care what the answer is! You'd never clock a FF from the output of a LUT. Would you? ;-) Cheers, Syms.Article: 92532
Hi All, Very helpful discussion going on atleast for me. Recently I had faced one problem. I was implementing a module/Entity which is intended to be used in cascaded configurations for parallel operations. (The Number of cascade Instances are limited by clock period and pipeline architecture). As it has a pipeline architecture some signals(inter_instance signals) are driven by a registered stage output for first instance and are actually combi outputs driving another combi block in the other instance and thus the pipeline works. Hope My explanation is clear...? so naturaly in the first instance which will be driving the chain of cascade instances will have both select and data lines of a mux or LUT driven by a registered stage. Here most probability is there of getting a glitch generated, which will propogate to the last instance and may create a problem where the final o/p is going to get registered in the last instance of cascade chain. I tried many was of implementing this combi structure in Altera Stratix but glitch is still there. Any guideline or suggetions will be greatly helpful... Thanks & Regards KedarArticle: 92533
"Frank" <Francis.invalid@hotmail.com> wrote in message news:438e8b5d$1@news.starhub.net.sg... > I was aware of this, however now I am asynchronously sampling at 400MHz, > thus > I am expecting each I/Q sample to be stable and correct for at least 22.5ns > assuming > the LA has miscaptured for one 2.5ns cycle. Are you saying that within one ENC cycle, the data is not stable around the falling clock edge? MeindertArticle: 92534
Okashii schrieb:
> Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx
> ISE and vhdl to build some components and no matter what the size of
> component I keep getting "number of bonded iob" exceeded. Then after some
> observation I finally realized that its the size of bits of the ports of the
> top level component :P. May I know where I can find layman information on
> fpga online that explains what are "slices, slice flip-flops, LUT, IOB" and
> all these?
> Thanks in advance!
>
>
Hi,
First of all... Read the datasheets of the device family you are about
to design for. They are available at the Xilinx homepage.
Second.. If you are working with the ISE ide (which comes with a fine
tutorial) you must know that it chooses by default the smallest device
of the selected fpga family. Just go and change your project properties
to a larger device and/or a package with more pins. That's all.
have a nice synthesis
Eilert
Article: 92535Hi, VHDL/Verilog are good for defining an FPGA/ASIC, SystemC is good for defining a System containing more (multiple ASICs, SW+HW,...). In SystemC you won't be able to squeeze a design for speed, area and power like you do in VHDL/Verilog. In VHDL/Verilog you die, if you like to simulate linux booting on your CPU-Core. In fact you have to choose the one you need, but it's most likely, that you use both, if you need SystemC, while there are enough designs left, which need only VHDL/Verilog. BTW VHDL is IMHO a bit better on closing the gap between System and ASIC, but SystemVerilog is a bit closer on system modeling than VHDL. bye ThomasArticle: 92536
So I'm a newbie to DPL, though I'm experienced w/ microcontrollers. I
wrote code for a CPLD (xilinx target, though it can change if needed)
that is supposed to run an A2D at high speed, communicate via SPI, and
take the data and convert it to a manchester-encoded stream and output
that. It seems to work fine in the simulator that I'm using (a trial
version of silos came with the veriolog book I bought), but I'm getting
warning with xilinx webpack. Also, when I run the synthesize option,
it never finishes - just sits there spinning for awhile. I'm using the
6.3v of webpack as that's the version that works with the programmer I
have, but I'm tempted to insall 7.0 just to see if that works any
better. I'll proivde the errors I get, followed by a copy of the code
I wrote. The clock (clk) is supposed externally generated, though I'm
not sure how to implement it other than the way I did. I also rely
heavily on delays in sending out the initalization strings - I'm not
sure how it'll be implemented in the CPLD. There are only 64 flipflops
in the target cpld that I want to use, so storing the init strings in
flip-flop memory seemed wasteful.
Any help, or pointers to good docs would be great!
Thanks in advance,
Reza
Analyzing top module <a2d>.
WARNING:Xst:854 - a2d.v line 22: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 32: Delay is ignored for synthesis.
WARNING:Xst:854 - a2d.v line 35: Ignored initial statement.
WARNING:Xst:916 - a2d.v line 47: Delay is ignored for synthesis.
WARNING:Xst:905 - a2d.v line 44: The signals <outClock> are missing in
the sensitivity list of always block.
WARNING:Xst:916 - a2d.v line 58: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 59: Delay is ignored for synthesis.
WARNING:Xst:916 - a2d.v line 60: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each
module.
module a2d(sck,dout,din,cs,tx);
output sck;
output dout;
input din;
output cs;
output tx;
reg [31:0] wData = 0 ;
reg wPointer;
reg sck;
reg dout;
reg cs;
reg tx;
reg clk;
reg outClock = 0;
reg init;
reg [3:0] bit;
reg [3:0] bit2;
initial begin
clk = 0;
sck = 1;
wPointer = 0;
#10 init = 1;
$monitor("data=",wData[3:0]);
end
/* TEST CLOCK */
always
#1 clk = ~clk;
initial begin
cs <= 1;
dout <= 0;
tx <= 0;
#1500 $finish;
end
/* GENERATE SCK WHEN outClock HIGH */
/* SCK = CLOCK/8 */
always @(clk) begin
if (outClock == 1) begin
sck = !sck;
#4;
end else
sck = 1;
end
/* SENT INIT ROUTINE */
always @(posedge init) begin
dout = 1;
/* FIRST DUMMY WORD */
cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* SECOND DUMMY WORD */
#16 cs = 0;
#4 outClock = 1;
#124 outClock = 0;
#4 cs = 1;
/* CONFIGURATION PARAMETERS */
#16 cs = 0;
#4 outClock = 1;
#76 dout = 0;
#8 dout = 1;
#42 outClock = 0;
#2 cs = 1;
#8 init = 0;
end
// CYCLE DATA AQUISITION AFTER INIT FINISHED
always @(negedge init) begin
#2 cs = 0;
#2 outClock = 1;
while (1) begin
wData[(16*wPointer)] = din;
/* test*/
bit =1 ;
repeat(15) begin
bit = bit + 1;
/* endtest */
// for (bit=1; bit>0; bit = bit + 1 ) begin
#4 wData[(16*wPointer)+bit] = din;
#4;
end
#8 wPointer = wPointer + 1;
cs = 1;
#4 cs = 0;
#4;
end
end
// MANCHESTER ENCODING
always @(posedge wPointer) begin
if (wData[3] || wData[2] || wData[1] || wData[0])
wData[0] = 0;
else
wData[1] = 1;
wData[1] = ^wData[15:4];
wData[2] = ^wData[15:10];
wData[3] = ^wData[9:4];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
always @(negedge wPointer) begin
if (wData[19] || wData[18] || wData[17] || wData[16])
wData[16] = 0;
else
wData[16] = 1;
wData[1] = ^wData[31:20];
wData[2] = ^wData[31:26];
wData[3] = ^wData[25:20];
tx=0;
bit2=0;
repeat(16) begin
if (wData[bit2+16] == 1) begin
tx=1;
#4 tx=0;
#4;
end else begin
tx = 0;
#4 tx = 1;
#4;
end
bit2 = bit2 + 1;
end
tx=0;
end
endmodule
Article: 92537Hallo, I should buy a phy transceiver for xilinx opb ethernet core. Which model dou you suggest? Many Thanks MarcoArticle: 92538
Hi all, I am reading a article. It mentions "multi-layer switching networks including, e.g. omega(perfect shuffle)/delta networks, log shifter networks, etc.". But why not use single-layer instead of multi-layer switch network? I know simple barrel shifter. What's omega, delta and log shifter? Any suggestions will be appreciated! Best regards, DavyArticle: 92539
Have a look at this Xilinx publication http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf . There are also handbooks for Spartan-3 etc that go into the architecture but you may have to pay for those (about $10). John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan-3 Development Board. http://www.enterpoint.co.uk "Okashii" <nordicelf@msn.com> wrote in message news:438e3387$1@news.starhub.net.sg... > Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx > ISE and vhdl to build some components and no matter what the size of > component I keep getting "number of bonded iob" exceeded. Then after some > observation I finally realized that its the size of bits of the ports of > the top level component :P. May I know where I can find layman information > on fpga online that explains what are "slices, slice flip-flops, LUT, IOB" > and all these? > Thanks in advance! >Article: 92540
I was now searching for an error in my design for hours.... As a last try I removed the folder db in the quartus project folder, compiled again and -- voila, the design worked! Weird! BTW: I'm invoking Quartus in batch mode from a Makefile. Anyone had similar experiences? MartinArticle: 92541
Thanks, this dis work after I looked up what values the environment variable could have. I found this at <http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/xst/xst0101_12.html> --- Hiding specific messages You can hide specific messages generated by XST at the HDL or Low Level Synthesis steps in specific situations by using the XIL_XST_HIDEMESSAGES environment variable. This environment variable can have one of the following values. none - maximum verbosity. All messages are printed out. This is the default. hdl_level - reduce verbosity during VHDL/Verilog Analysis and HDL Basic and Advanced Synthesis. low_level - reduce verbosity during Low-level Synthesis hdl_and_low_levels - reduce verbosity at all stages. --- "Gabor" <gabor@alacron.com> wrote in message news:1133358792.673137.216250@g47g2000cwa.googlegroups.com... > Try setting the environment variable: > > XIL_XST_HIDEMESSAGES > > This worked in a similar case for me on ISE 6.1 where I have a 64 bit > bus and ran for more than a couple of minutes as I recall. >Article: 92542
Marco wrote: > Hallo, > I should buy a phy transceiver for xilinx opb ethernet core. > > Which model dou you suggest? I use the National Semiconductor DP83865DVH. --- Joe Samson Pixel VelocityArticle: 92543
http://www.fpga4fun.com/ Okashii wrote: > Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx > ISE and vhdl to build some components and no matter what the size of > component I keep getting "number of bonded iob" exceeded. Then after some > observation I finally realized that its the size of bits of the ports of the > top level component :P. May I know where I can find layman information on > fpga online that explains what are "slices, slice flip-flops, LUT, IOB" and > all these? > Thanks in advance! > >Article: 92544
Davy schrieb: > But why not use single-layer instead of multi-layer switch network? A very abstract answer: I a single layer network every input connects to N other pins. These everage wire length for each input is at least proportional to (n*sqrt(n)), same for the capacitance. Therefor the bandwidth is reciprocal to n^3, the latency is proportional to n^3. The other extreme is a tree of 2-way switches. Each path has log(n) switches. Each connection has 2 pins. The area is n^2 (n*log(n) is only true for unbounded number of rounting layers). The average wire length is n. The bandwidth is constant, the latency is proportional to log(n). Of course the latency of the switch will have a larger constant value than the wire. But the difference between log and n^3 is extreme, so the break even point will be for rather small n. Kolja SulimmaArticle: 92545
Hi Martin,
This problem was reported by the Altera applications group on Monday
this week and we will have a fix ready. This global patch which is
undergoing testing will be made available by Friday noon and a link will
also be posted here. This problem is seen if you are compiling a design
which has encrypted IP. This affects Nios II designs and four of the
communications cores. In the meantime delete the db directory. This problem
only affects Quartus II 5.1. Earlier versions of Quartus are not afected.
We apologize for any inconvenience this may have caused.
- Subroto Datta
Altera Corp.
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message
news:438ef5fb$0$8024$3b214f66@tunews.univie.ac.at...
>I was now searching for an error in my design for hours....
> As a last try I removed the folder db in the quartus project
> folder, compiled again and -- voila, the design worked!
>
> Weird!
>
> BTW: I'm invoking Quartus in batch mode from a Makefile.
> Anyone had similar experiences?
>
> Martin
>
>
Article: 92546Subroto Datta wrote: > If your design does not compile for any reason in 5.1 and it did compile in > an earlier version, in all proabability it is a bug that we would fix. First > try compiling with Quartus II 5.1. If it fails, please open a Service > Request using mysupport. The design compiles with the new version, but allegedly doesn't work, so the author always uses 4.1 for that project. The belief is that there's a sloppy timing dependence that gets broken by more efficient assignment or something... an error in our design that probably should be fixed in the long run, but something tangential to my efforts to adopt it and make minimal functional changes.Article: 92547
Nice solution! "Arlet" <usenet+5@ladybug.xs4all.nl> wrote in message news:1133294098.430743.59950@g14g2000cwa.googlegroups.com... > damir wrote: >> I need to implement slow FIFO (16-bit wide, max. 10 MHz) using external >> single-port SRAM connected to the FPGA (Spartan II/III). >> >> Does anyone have similar FIFO controller (sync/async) implemented using >> VHDL? >> >> Thanks, >> >> Damir > > I would put two small FIFOs on the FPGA, and then have a simple, > synchronous state machine to control the external RAM. The state > machine would look at how full/empty the FIFOs are, and based on their > priority determine whether it will do a either a read or write access > to the external RAM. > > If you need an asych FIFO, then use one of the on-chip FIFOs to cross > the clock domains, and keep the rest on the same clock. >Article: 92548
Hi there, pardon me but I'm a newbie at fpga and stuff. I was using Xilinx ISE and vhdl to build some components and no matter what the size of component I keep getting "number of bonded iob" exceeded. Then after some observation I finally realized that its the size of bits of the ports of the top level component :P. May I know where I can find layman information on fpga online that explains what are "slices, slice flip-flops, LUT, IOB" and all these? Thanks in advance!Article: 92549
> This problem was reported by the Altera applications group on Monday this week and we will have a fix ready. This global patch > which is undergoing testing will be made available by Friday noon and a link will also be posted here. This problem is seen if you > are compiling a design which has encrypted IP. This affects Nios II designs and four of the communications cores. In the meantime > delete the db directory. This problem only affects Quartus II 5.1. Earlier versions of Quartus are not afected. > > We apologize for any inconvenience this may have caused. Hi Subroto, thanks for the reply. I've added a 'rm -r db' in my Makefile ;-) However, my design does not used any encrypted IP, just plain VHDL files. Martin
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