Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello Andre, Cyclone has clock enable on the I/O registers. You can see it in Fig 2-32 of the data sheet, as well as references to it in figure 2-30 & 2-31, and the description is between figures 2-31 & 2-32. http://www.altera.com/literature/hb/cyc/cyc_c51002.pdf Hope this helps, Subroto Datta Altera Corp.Article: 88076
hi...........
in sparton-2 ......for disply(VGA) controller ...i wanna
use bram...........can??????how?????????
Article: 88077
hi...
i m using spartan-2 ......... and have designed a very simple
vga controller on it ...... now i wanna interface an external ram
with it .......... i m available only a sram of 32 kbit * 8 = 256 kb
memory which is not dual port........
i wanna store 640*480 pixels data on it ... as i need
only 8 colors ...so 3 bits for each pixel ...
is it possilble to reduce memory to make according to
desired requiremeents ........ and to use it although it is not dual
port ...
Article: 88078
Hi...
i wanna use sram instead of Vram in my project ... according to
my knowledge vram is same as sram but its dual port...........as for
display its needed to read and write at same time fastly ...so uses
dual port sram...... but
problem is ... i m available only sram which is not
dual port.............is it possible to use it for display?????????
and how???????????
Article: 88079Hello, I have a top level module for a XCV1000. It has a following specified UCF for the pin and netname mappings. I have instantiated to fo the DLLs and two user modules. The DLLs are the same as in XAPP132 for a 4X clock signal generation. When I generate the bit file and look at the design with FPGA Editor, I don't see any signals or CLBs for one of the two user defined modules. There are some warnings about clock signals and I am using "clock_signal" synthesis attribute to tell XST which are the clocks, basically restricting the clocks and reducing the GCLK usage. When I comment out one of the modules that is instanitated all the time and re-synthesize, I see module instantiation. I have put the files online that I think may be helpful. These files can be found at: http://www.stanford.edu/~johnd/Xilinx/ The top level module is CP2_FPGA and I instantiate two user modules within CP2_FPGA: R3000Init1 Test00a The R3000Init1 always shows up and Test00a doesn't. If I comment out R3000Init1, then Test00a shows up in FPGA editor. I have attached the log files when I synthesize with both modules: R3KandTest00.txt and with just the Test00a: JustTest00.txt. The CP2_FPGA.ncd is the file for FPGA Editor for the first case (both modules) and CP2_FPGA_last_par.ncd is the FPGA Editor file for the latter case, when R3000Init1 is commented out. I can include other files, but it is strange that the instantiated module is not in the FPGA Editor with the related CLB's depending on what other modules exist. I would like a highly modular design for easy of debugging and code management. Any idea's why the module doesn't appear in the FPGA? Thanks, John D. DavisArticle: 88080
fahadislam2002 wrote: > i m using spartan-2 ......... and have designed a very simple > vga controller on it ...... now i wanna interface an external ram > with it .......... i m available only a sram of 32 kbit * 8 = 256 kb > memory which is not dual port........ > i wanna store 640*480 pixels data on it ... as i need > only 8 colors ...so 3 bits for each pixel ... > is it possilble to reduce memory to make according to > desired requiremeents ........ and to use it although it is not dual > port ... You have two choices: 1. Timeslice access between whatever is writing to your video memory, and the vga controller. You'll need some pretty fast SRAM to do this - I suspect your dot-clock is around 30MHz (33ns)? So you'll need SRAM twice as fast as this. 2. Use some sort if FIFO and write to the SRAM only during the blanking intervals on the vga controller. This will of course limit your bandwidth writing to the video memory. As for memory size, my calculations give 115.2KB required for the display, though it's horribly aligned. Storing 2 pixels/byte requires 153.6KB. Not sure where you got 256KB from? Regards, MarkArticle: 88081
Mark McDougall wrote: >> it .......... i m available only a sram of 32 kbit * 8 = 256 kb >> memory which is not dual port........ i wanna store 640*480 pixels >> data on it ... as i need only 8 colors ...so 3 bits for each pixel >> ... is it possilble to reduce memory to make >> according to desired requiremeents ........ and to use it although >> it is not dual port ... > As for memory size, my calculations give 115.2KB required for the > display, though it's horribly aligned. Storing 2 pixels/byte requires > 153.6KB. Not sure where you got 256KB from? Oh, I think you're saying you only have 256k *bits*!?! You'll have to compress the image then. Depending on the complexity of the image, you may get away with RLE - it's pretty simple to decode on-the-fly. Otherwise, well, I'm glad it's you doing it and not me! ;) Regards, MarkArticle: 88082
Gabor wrote: > praveen.kantharajapura@gmail.com wrote: > > Hi, > > I want to design a sequence detector circuit, there are two approaches > > . > > > > The first approach is the traditional state m/c approach > > > > The second is shift register approach > > for ex: for detecting sequence "10101011" i put a simple 8 bit shift > > register and look for the pattern "10101011" .I check the shft register > > value in each cycle whenever the shift register value is "10101011" the > > output is set to "1". > > > > Which method is better the traditional state m/c approach or the shift > > register approach for sequence detection. > > > > Regards, > > Praveen > > You'll need to define "better" in this case. If you need to run > faster, > the state machine may do better because it only handles one bit at a > time. I am running at 150 MHZ is it really feasible to implement in shift registers. I have to look for 3 bytes( 24 bits). > If you need to change the pattern you're detecting, the shift register > and comparator will make life much easier. Also the shift register > approach > gets slower and bigger as the size of your pattern increases. Either > approach can be optimised for a fixed pattern (the comparator turns > into > an AND gate for the fixed case). The state machine can be further > optimised if the pattern is "regular" (symmetric or repeating). I > guess > the answer is "it depends..."Article: 88083
Does anyone possess an example of a core incorporated to the PLB of Virtex2Pro especially if the design is using FIFOs. I am trying to incorporate my DES core to the PLB bus of the Virtex2Pro for a Single PPC design. Thanks, NoelArticle: 88084
"fahadislam2002" <fahadislam2002@hotmail-dot-com.no-spam.invalid> schrieb im Newsbeitrag news:-tqdnXj1L7ewa2rfRVn_vQ@giganews.com... > hi........... > in sparton-2 ......for disply(VGA) controller ...i wanna > use bram...........can??????how????????? > there is no sparton-2 to my knowledge. in spartan-2 you can use BRAM for any purpose, including VGA. AnttiArticle: 88085
fahadislam, it is about time you grew up and stopped using these insane punctutions. It would also help if you learned how to spell. Perhaps you might even learn to think, if that is not asking for too much.. This is not a childrens' playground. If you want to mix with adults, behave like an adult. Peter AlfkeArticle: 88086
Hi Subroto, thank you for the link. Does that mean that the OE Register holds its value if clock enable is inactive ? If so, is the clock enable "generated" automatically by Quartus when using the VHDL description above? Or do I have to instantiate an output register which includes clock enable as input port? Rgds Andr=E9Article: 88087
HI, > I am running at 150 MHZ is it really feasible to implement in shift > registers. > I have to look for 3 bytes( 24 bits). In some fpgas it will be hard getting 5 levels (log2(24) as worstcase compare tree) of logic at 150 Mhz without pipelining. But I see no general problem.Article: 88088
Maybe you should think about another FPGA (e.g. without bitstream). Otherwise I would generate the key instead of hardwireing it. It depends on your apllication how save you need the key and how likely it is that an attacker has access to your bitstream. bye ThomasArticle: 88089
Could it even make sense to describe the clock enable on my own and NOT to let the fitter recognize it automatically ? Could that have some performance advantages ? Rgds Andr=E9Article: 88090
On 7 Aug 2005 17:55:03 -0700, "Tobias Weihmann" <listen@fomalhaut.de> wrote: >Hello. > >I'm new to Spartan-3, before I only worked on the legacy XC6216 FPGA. I >am trying to port a university project over to a modern FPGA platform. > >I assume that the full details of the Spartan-3 bitstream are not >published beyond what is described in XApp452 (XC6216 bitstream was >fully published). > >Also I assume that it is possible to damage the FPGA using invalid >bitstreams (as opposed to the XC6216). > >I want to generate a placed & routed design using my own custom >algorithms and then upload it to the Spartan-3, without resorting to >PAR tools and such. > >At what point would I have to enter the workflow? Convert my design to >NCD files? (Most likely, the NCD format is closed as well?) > >Thank you, Tobias While the NCD data base is closed, there is a program that can dump it to ascii, and convert from ascii back to NCD. Look for XDL.exe start with: xdl -h From ascii you go through bitgen to get to a bitstream. Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 88091
Hi all, I am implementing some logic in FPGA(Transmit/Reveive). On the receive data first i look for a 8- bit pattern to detect the START pattern.Now my question is in the data also i may get the same START pattern how to distinguish between the START /STOP pattern and data. Any comments are appreciated. Regards, PravArticle: 88092
If you don't specify IO standards, drive etc. in the UCF for a Spartan3, what default settings are used ?Article: 88093
<praveen.kantharajapura@gmail.com> wrote in message news:1123580714.592316.233920@g47g2000cwa.googlegroups.com... > Hi all, > > I am implementing some logic in FPGA(Transmit/Receive). > > On the receive data first I look for a 8- bit pattern to detect the > START pattern.Now my question is in the data also I may get the same > START pattern how to distinguish between the START /STOP pattern and > data. Based on the brief text above, the FPGA has no way to tell a start flag character from the same byte appearing as data, so unless you give it one it cannot do this. In practice, people have invented ways of sending 8-bit data like that. The HDLC/ADLC protocol uses the bit pattern 01111110 (0x7E) to mark the start of packets. To prevent those 6 consecutive set bits appearing elsewhere, the transmitter stuffs in a zero after 5 consecutive set bits. Receivers look for 5 consecutive set bits. If the next bit is set, it is the start of a frame. If not, it is a stuffed-bit which is discarded. The Zilog SCC is a good example of a serial chip that supports HDLC. Don't re-invent the wheel! Google HDLC and 'bit stuffing'Article: 88094
<praveen.kantharajapura@gmail.com> wrote in message news:1123559226.504192.76120@z14g2000cwz.googlegroups.com... > > > I am running at 150 MHZ is it really feasible to implement in shift > registers. > I have to look for 3 bytes( 24 bits). > Hi Praveen, If so, in FPGAs you can often use the carry chain for this kind of thing. In UG002 ( http://www.xilinx.com/bvdocs/userguides/ug002.pdf ) go to the section "Implementing Sum of Products (SOP) Logic". 150MHz is a piece of cake, for a fixed pattern circuit you get 4 bits per LUT, 24 bits is only 6 LUTs and only 3 carry delays (the carry logic does two bits at a time). The biggest delays are getting on and off the chain. If you're looking for a programmable pattern, the same idea works, but you only get two bits per LUT. Two from your shift register, two from the programmable pattern. The LUT output is on when they match. Almost as fast as above, because the main delays are getting on and off the chain. HTH, Syms.Article: 88095
Mike, Dunno, but it's easy to find out. Build a noddy design that's a wire from an input to an output. No UCF. Run P&R. Use FPGA editor to look at the IOBs' properties. This method has the advantage of showing you what the software ACTUALLY does, rather than what it SHOULD do! ;-) Cheers, Syms. "Mike Harrison" <mike@whitewing.co.uk> wrote in message news:f61hf1hnbgibg9rmb1cm9effv54kdg67q3@4ax.com... > If you don't specify IO standards, drive etc. in the UCF for a Spartan3, > what default settings are > used ?Article: 88096
praveen.kantharajapura@gmail.com schrieb: > Hi all, > > I am implementing some logic in FPGA(Transmit/Reveive). > > On the receive data first i look for a 8- bit pattern to detect the > START pattern.Now my question is in the data also i may get the same > START pattern how to distinguish between the START /STOP pattern and > data. > > Any comments are appreciated. > > Regards, > Prav > Hi Praveen, do you transmit fully binary data? otherwise e.g. for ascii transmission there is the X-On X-Off protocol. Or how about formatting your data? If you define a blocksize N then after a start symbol follows (at least) one whole block and then comes the stop symbol. The next block(s) need a start symbol again and so on , and so on... (A sophisticated example for a block protocoll is TCP/IP) Surely there are many solutions to your problem. Regards EilertArticle: 88097
praveen.kantharajapura@gmail.com wrote: > On the receive data first i look for a 8- bit pattern to detect the > START pattern.Now my question is in the data also i may get the same > START pattern how to distinguish between the START /STOP pattern and > data. You could define special characters for synchronisation (start/stop/etc), and use escaping to encode these characters with other characters. For an example, take a look at the SLIP protocol RFC (1055) http://www.faqs.org/rfcs/rfc1055.html A snippet from this RFC explains this better then I do : The SLIP protocol defines two special characters: END and ESC. END is octal 300 (decimal 192) and ESC is octal 333 (decimal 219) not to be confused with the ASCII ESCape character; for the purposes of this discussion, ESC will indicate the SLIP ESC character. To send a packet, a SLIP host simply starts sending the data in the packet. If a data byte is the same code as END character, a two byte sequence of ESC and octal 334 (decimal 220) is sent instead. If it the same as an ESC character, an two byte sequence of ESC and octal 335 (decimal 221) is sent instead. When the last byte in the packet has been sent, an END character is then transmitted. As said before, don't re-invent the wheel -- :wq ^X^Cy^K^X^C^C^CArticle: 88098
hi there, i am trying to generate a partial bitstream for a module using a multipier. the code is quite simple, just a counter with some multiplication stuff, nothing special and about 5 lines of code. par says: Phase 8:2 unrouted UNROUTABLE DESIGN is there anything special I have to consider when using the virtex2 6000 multipliers in partial reconfig? i am really going nuts because of these xilinx tools :/ thanks anyway. c. lauerArticle: 88099
Hello, I am trying to run the embedded TEMAC in the Virtex4 under Linux. A design with the EMAC IP Core from the EDK is running with the Montavista Preview Kit. Now I am trying to change the adapter.c file from the Previewkit to the Xilinx TEMAC source files. Has anyone experiences with one of these parts? Thanks
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z