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Technically Taiwan is not part of China, only the CP of mainland China & KMT of Taiwan insists this, the people of Taiwan don't believe it and even fear it. Their laws are already pretty close to US if not a direct copies. Umm. Even the street signs are either UK or US copies umm, I'm always amused when I see those UK signs to describe the smallest irrelevant street features. Alot of what makes Taiwan modern though comes from the Japanese colonial days. Still I would take the usual protections, at least you are free to go and check and resolve it legally. I doubt you could do that in PRC. johnjakson at usa dot comArticle: 85051
"Rene Tschaggelar" <none@none.net> schrieb im Newsbeitrag news:42a014b0$0$1161$5402220f@news.sunrise.ch... > > Hi Falk > > > > I did not get your idea .. > > > > Could you please put ur idea in a figure please .. > > > > to interface VCO to DDS shall we need a DAC also ? > > I gleam that the idea could be to use a PLL to remove > the ugly stuff from a DDS. In my experience, once you > have the ugly stuff (noise, glitches, spikes) on your Haaa, not sooo fast, my friends ;-) First, the DDS output will have NO glitches and spikes. So 2 out of 3 are out. Noise is another story. Yeah, digital and analog dont mix well, but ist not impossible. My idea is. Quadruple the 35.whatever MHz clock using a DCM. Use this clock to drive a simple DDS. No need for a sin rom, just use the MSB as your clock. Generate a clock that is 1/10 of of you desired (fine tuned) 35.whatever clock. With the fixed 35.whatever quadrupled, this gives you a systematic jitter of 1/40 period. Hmm, not too bad. Now use a (cheap) analog PLL with a (cheap) VCO to multiply the 1/10 DDS output by ten. I gues the good ole 4046 isnt fast enough for that, I remeber 30 MHz max. for the VCO. Use a loop filter with a low corner frequency. Somthing in the range of 1/10..1/1000 of the input frequency (which translates in 1/100 ... 1/10,000 of the output frequency) the better the VCO the lower you can go. Imagine, the VCO has to run stable for 100..10,000 cycles before the loop filter will respond to phase drifts. Another approach would be to use the DDS (running at x4 clock) to directly generate the tunable 35.whatever clock. By using just the MSB again, we end up with a clock with 1/4 period of systematic jitter. Uhhhh. But things can get cleand up. Use a plain Xtal for 35.whatever frequency to build a Xtal filter. This should get rid of all the bad jitter. This way you need just a Xtal, which is less expensive than a full DDS IC (i guess). But after all, why do you need a 1Hz tuning in the xDSL modem? Arn't they supposed to tolerate something like +/- 50 ppm, which is a standard precicion of almost every Xtal? Just my 2 cents. Regards FalkArticle: 85052
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:%W_ne.14$Np1.372@news-west.eli.net... > The ugly stuff is hard to remove if it's low frequency ugly stuff. If the > jitter frequencies are above the PLL loop frequency, the ugly stuff will go > away. The problem is in trying to extract the fundamental frequency +/- a > few Hertz from an oscillator with the same frequency. In this situation > there *will* be ugly stuff at a few Hertz that can't be filtered by the PLL. You are right, but the more important question is. Will these narrow sidebands make trouble in the application? I doubt is. > Using a completely unrelated (higher frequency) clock could produce a DDS > clock at the desired fundamental frequency +/- a few Hertz with almost all > the ugly stuff high in frequency if the unrelated clock is chosen well. A > 100 MHz clock will have jitter frequencies at 32kHz and higher which would > be cleaned up rather well by many zero delay buffers. The Hertz-offset ugly > stuff would be about 3 ps peak-to-peak in this arangement. Hardly a issue at all. That aint a rocket science project. I guess ,-) Regards FalkArticle: 85053
"Mac" <foo@bar.net> schrieb im Newsbeitrag news:pan.2005.06.03.01.33.56.516645@bar.net... > The clocks which go from the host board to the PCI slots are supposed to > be matched in length and under some maximum, IIRC. They can actually be > pretty long (12" or more) and still work at 33 MHz, but they are supposed > to be matched in length. AFAIR the trace length on the PCI card (NOT the motherboard/backplane) is supposed to be 1 inch +/- 0.005. Including the tolerances of the backplane, skew is assued to be less than 2ns. Regards FalkArticle: 85054
<learnfpga@gmail.com> schrieb im Newsbeitrag news:1117815955.528902.306240@g43g2000cwa.googlegroups.com... > Hi There, > I have Orcad Express CIS 7.2 and I want to program Lattice ispLSI1016 > using it. I already have the schematic for it in Orcad Express. Also I > have the programmer for 44 pin isp1016. I was wondering if someone can > guide me as to what steps I need to take after this. thanks Go to www.latticesemi.com Download the ispLever Software. Install it. Get a licence (its free) Create a project. Compile the schematics Download the JEDEC file. Njoy. Regards FalkArticle: 85055
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1117771436.575914.41260@o13g2000cwo.googlegroups.com... > I do not know why you are so slow, you could easily be a thousand times > faster. Why hurry withou a need? By scanning so low you a) consere power b) do a debounce > Since you can only detect a single closure, you could encode the scan > into a 6-bit word. > > I am glad you realized that you cannot detect multiple simultaneous key > closures, without inserting iolation non-linearities (diodes) into the > array. ??? Been there, done that? I worked on this topic not too long ago, you CAN easyly detect multiple pressed keys withOUT having diodes in the matrix. All you need is a "walking one" scan. Regards FalkArticle: 85056
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1117771436.575914.41260@o13g2000cwo.googlegroups.com... BTW. I dont know if this is a problem in my newsserver or your newsagent. I see all yor posts twice (no Iam not drunk, unfortunately ;-) Regards FalkArticle: 85057
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1117777855.397592.150070@g47g2000cwa.googlegroups.com... > At 35 MHz, the period is around 30 ns. > If you change the frequency by 1 Hz, you change the period by 30 ns / > 35 million. > That is less than one femtosecond. (Less than a thousandth of a > picosecond) > Light travels 0.3 micron (about half its own wave length) in 1 > femtosecond. > Just to put things in perspective... Thats right but not quite the point. If two clocks @ 35MHz are off just by 1Hz (wich is just 0.02 ppm) , it takes just 1 second to reach a phase offset of 1 clock cycle. Can be nasty if two devices talk to each other . . . That why the lord invented PLLs ;-) Regards FalkArticle: 85058
Hey Man Thanks for the reply. Just to make sure will this be ispLEVER-Starter Synplify Synthesis Module (May 2005) because as far as I know ispLSI1016 is CPLDArticle: 85059
Has anyone taken a C benchmark suite, like MediaBench, partitioned it by hand into C and Verilog or VHDL (or some moral equivalent of those), run the partitioned programs on one of the FPGAs with a built-in processor and published the results? Thanks, BenjaminArticle: 85060
>Hey Man Thanks for the reply. Just to make sure will this be >ispLEVER-Starter Synplify Synthesis Module (May 2005) because as far as >I know ispLSI1016 is CPLD ispLSI1016 may not be supported by the recent *free* software releases? But you can program the device with the downloadble programming software.Article: 85061
Well I finally got around to trying it out, but didn't notice any real
difference.
The following summary gives an idea of the size of the design I tried
out:
Importer Summary
===============
Part-Package: APA600-BG456
Core Slots: 21504
RAM/FIFO Slots: 56
I/O Slots: 356 (Globals: 4) (PLLs: 2)
Core Cells: 11965 --> Usage: 55.6 percent
RAM/FIFO Cells: 6 --> Usage: 10.7 percent
IOs: 352 --> Usage: 99.4 percent
PLLs: 2 --> Usage: 100.0 percent
Constraints processed:
IO constraints: 351
Path constraints: 0
Placement constraints: 0
Net constraints: 4
I/O Cells: Core cells:
| Instances | Gates | Tiles
Input. IOs: 87 ----------|-----------|--------|-------
Bidir IOs: 80 Logic | 8777 | 20183 | 8777
Output IOs: 185 Storage | 3185 | 25215 | 3188
Global IOs: 0 RAM/FIFO | 6 | 54144 | 48
Internal Global: 0 | | |
----------------------- ----------|-----------|--------|-------
Total IOs: 352 Total | 11968 | 99542 | 12013
The windows machine used for the test was a Pentium 4 2.4GHz with 512MB
RAM running WIN XP SP2.
The Linux machine was an Athlon XP2200+ with 512MB RAM running CentOS 4
(RHEL 4 clone).
In both case the run time for layout was ~50 mins, so it seems the
information I received was clearly wrong.
Article: 85062Which programming software are you refererring to? I am a novice in this field and this is something that I have inherited. So if you can be more specific that will be great. thanksArticle: 85063
<learnfpga@gmail.com> schrieb im Newsbeitrag news:1117822755.284513.199090@z14g2000cwz.googlegroups.com... > Which programming software are you refererring to? I am a novice in > this field and this is something that I have inherited. So if you can > be more specific that will be great. thanks Hmm, Mika is right. The free "ispLever" does not support the rather old 1016 anymore. Contact the support. When I did so, they offered my to give me a location where I can download the old version, which does support the old devices. As for the programming tool, its called ispVM (if I remember correctly). This tool allows you to programm the devices, similar to an EPROM programmer. But thats all. If you dont have a JEDEC file (*.jed) you need to compile/fit your VHDL/Verilog/Schematics using ispLever. Regards FalkArticle: 85064
<learnfpga@gmail.com> schrieb im Newsbeitrag news:1117824498.090005.315720@f14g2000cwb.googlegroups.com... > Can Orcad Express CIS 7.2 be used instead of ispLEVER? I duno.Article: 85065
Can Orcad Express CIS 7.2 be used instead of ispLEVER?Article: 85066
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3gbj51Fbl9vdU1@individual.net... > > "John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag > news:%W_ne.14$Np1.372@news-west.eli.net... > > > The ugly stuff is hard to remove if it's low frequency ugly stuff. If the > > jitter frequencies are above the PLL loop frequency, the ugly stuff will > go > > away. The problem is in trying to extract the fundamental frequency +/- a > > few Hertz from an oscillator with the same frequency. In this situation > > there *will* be ugly stuff at a few Hertz that can't be filtered by the > PLL. > > You are right, but the more important question is. Will these narrow > sidebands make trouble in the application? I doubt is. The trouble is the Hz-level modulation looks like a saw wave. When the saw hits the vertical cliff, the phase slews as fast as the PLL loop filter allows producing a phase hit. I may have oversimplified the situation by suggesting the spurs are close-in; they're also in harmonics much further up because of the saw function in the phase error. > > > Using a completely unrelated (higher frequency) clock could produce a DDS > > clock at the desired fundamental frequency +/- a few Hertz with almost all > > the ugly stuff high in frequency if the unrelated clock is chosen well. A > > 100 MHz clock will have jitter frequencies at 32kHz and higher which would > > be cleaned up rather well by many zero delay buffers. The Hertz-offset > ugly > > stuff would be about 3 ps peak-to-peak in this arangement. > > Hardly a issue at all. That aint a rocket science project. I guess ,-) > > Regards > Falk But it is rocket science if the input and output frequencies are offset by a few Hertz.Article: 85067
"John_H" <johnhandwork@mail.com> wrote in message news:wC1oe.16$Np1.395@news-west.eli.net... > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:3gbjurFbm5d1U1@individual.net... > > > > ??? Been there, done that? > > > > I worked on this topic not too long ago, you CAN easyly detect multiple > > pressed keys withOUT having diodes in the matrix. > > All you need is a "walking one" scan. > > > > Regards > > Falk > > You can easily detect *2* keypresses without diodes. If you press R1C1, > R5C1, and R1C3, you can't tell if R5C3 is pressed or not. A drive to R5 ^^^^ - I had R5C3 here which didn't follow - - - > results in C1 and C3 sensed because the two columns are shorted at row 1. > In high school I had fun turning off my TI calculator by pressing 3 keys > that box in the power button, R5C3 in the example. I was a geek even then.Article: 85068
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3gbiulFbja82U1@individual.net... > Haaa, not sooo fast, my friends ;-) > > First, the DDS output will have NO glitches and spikes. So 2 out of 3 are > out. The DDS MSbit output is a square wave with significant phase jitter - glitches and spikes in the phase domian. > Noise is another story. Yeah, digital and analog dont mix well, but ist not > impossible. > > My idea is. Quadruple the 35.whatever MHz clock using a DCM. Use this clock > to drive a simple DDS. No need for a sin rom, just use the MSB as your > clock. Generate a clock that is 1/10 of of you desired (fine tuned) > 35.whatever clock. With the fixed 35.whatever quadrupled, this gives you a > systematic jitter of 1/40 period. The 1/40 period jitter is based on the 3.5 MHz period. The jitter is still 1/4 the 35 MHz period which will translate directly through the PLL. > Hmm, not too bad. Now use a (cheap) analog > PLL with a (cheap) VCO to multiply the 1/10 DDS output by ten. I gues the > good ole 4046 isnt fast enough for that, I remeber 30 MHz max. for the VCO. > Use a loop filter with a low corner frequency. Somthing in the range of > 1/10..1/1000 of the input frequency (which translates in 1/100 ... 1/10,000 > of the output frequency) the better the VCO the lower you can go. Imagine, > the VCO has to run stable for 100..10,000 cycles before the loop filter will > respond to phase drifts. > > Another approach would be to use the DDS (running at x4 clock) to directly > generate the tunable 35.whatever clock. By using just the MSB again, we end > up with a clock with 1/4 period of systematic jitter. Uhhhh. But things can > get cleand up. Use a plain Xtal for 35.whatever frequency to build a Xtal > filter. This should get rid of all the bad jitter. This way you need just a > Xtal, which is less expensive than a full DDS IC (i guess). > But after all, why do you need a 1Hz tuning in the xDSL modem? Arn't they > supposed to tolerate something like +/- 50 ppm, which is a standard > precicion of almost every Xtal? Excellent point: specs are everything. Why specify an electron microscope if a hand magnifier will do? > Just my 2 cents. > Regards > FalkArticle: 85069
For my latest Nios II DevKit I have received 2 additional Nios II 1.1 Upgrades although the kit already came with this version. I haven't received any copy of the 5.0 version so far. The most annyoing thing is that they guarantee the updates for 1 year but never send any. I had another devkit with the old Nios and never got the Nios II software or at least an evaluation version of it. If they want us to download the new versions then they should simply say so on their web site. From the information on the web site I always get the impression that it's just an evaluation version and not the real thing although with previous versions there was no difference in the end. "Jedi" <me@aol.com> wrote in message news:lFDne.179$YR2.156@read3.inet.fi... > So for how long is NIOS2 5.0 out? > > Just received today my NIOS2 1.1 upgrade... > Unbelievable fast they are (o; > > > /jedi >Article: 85070
hi, i am trying to do power estimation for xilinx fpga and decided use the xilinx xpower.i am not sure about how to fill in the toggle rate, the capacitive load,dc load during power analysis. i did look up the tutorials, but then i couldnt understand it clearly.can anyone explain to me how to go about? thanks dvArticle: 85071
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:3gbjffFbklqdU1@individual.net... > > <learnfpga@gmail.com> schrieb im Newsbeitrag > news:1117815955.528902.306240@g43g2000cwa.googlegroups.com... > > Hi There, > > I have Orcad Express CIS 7.2 and I want to program Lattice ispLSI1016 > > using it. I already have the schematic for it in Orcad Express. Also I > > have the programmer for 44 pin isp1016. I was wondering if someone can > > guide me as to what steps I need to take after this. thanks > > Go to www.latticesemi.com > Download the ispLever Software. > Install it. > Get a licence (its free) > Create a project. > Compile the schematics > Download the JEDEC file. > Njoy. > > Regards > Falk > not as easy - the Lattice support told me once that older devices like ispLSI1016 can be 're-enabled' in the new software, by editing some textual conf file, but I never got the details how to do this :(, and it was for ispLever 4.x something not sure if it is still doable for 5 anttiArticle: 85072
Hi, While taking my first steps with the EDK, I'm running into problems right away. - clean install of ISE 6.3i and EDK 6.3 - start Platform studio - Create a project for the 3L eval board with the wizard - Create bitstream After a few minutes, the build breaks with the following message : FATAL_ERROR:HDLParsers:vhplib.c:466:$Id: vhplib.c,v 1.25 2003/05/22 00:46:02 kumar Exp $:200 - INTERNAL ERROR... while parsing <no file> line 86. Contact your hot line. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com The tricky part is probably "INTERNAL ERROR... while parsing <no file> line 86". No references on google or on Xilinx support about 'vhplib.c', so no idea where to start. Any ideas ? _IcoArticle: 85073
As far as I know, it is still do-able. I suggest on the other hand to contact your local FAE (or distributor). They will certainly help you further. Luc On Fri, 3 Jun 2005 21:16:52 +0200, "Antti Lukats" <antti@openchip.org> wrote: >"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag >news:3gbjffFbklqdU1@individual.net... >> >> <learnfpga@gmail.com> schrieb im Newsbeitrag >> news:1117815955.528902.306240@g43g2000cwa.googlegroups.com... >> > Hi There, >> > I have Orcad Express CIS 7.2 and I want to program Lattice ispLSI1016 >> > using it. I already have the schematic for it in Orcad Express. Also I >> > have the programmer for 44 pin isp1016. I was wondering if someone can >> > guide me as to what steps I need to take after this. thanks >> >> Go to www.latticesemi.com >> Download the ispLever Software. >> Install it. >> Get a licence (its free) >> Create a project. >> Compile the schematics >> Download the JEDEC file. >> Njoy. >> >> Regards >> Falk >> > >not as easy - the Lattice support told me once that older devices like >ispLSI1016 can be 're-enabled' in the new software, by editing some textual >conf file, but I never got the details how to do this :(, and it was for >ispLever 4.x something not sure if it is still doable for 5 > >antti >Article: 85074
I want to share one BRAM block (RAMB16_S9_Sxx) between microblaze and my user logic. My user logic would use PortA (8 bits), microblaze could use PortB for 32 bit access. Microblaze is always using 4 BRAM block for 32 bit access, but I need only one BRAM block. How can I do this? Zolee
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