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bijoy wrote: > Hi I am using Spartan-3 fpga > > I need to generate 35.328 MHz clock > > I have an external xtal of 35.328 MHz feeding to FPGA. > > From this clock i need to generate 35.328 MHz square wave with fine resolution. > > We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution. > > I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept. > > Is there any-other way out ? > > ( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices. > > So i thought of using FPGA for this purpose as an alternative solution. ) How would an FPGA be able to achieve a clock that was difficlt to achieve otherwise ? So when a 300MHz DDS is too noisy, rebuilding the DDS with an FPGA is not going to help. What is also not going to help is a PLL with a Phase comparator running at 1Hz. The other possible way would be to single side band modulate your carrier. The probelm there ist the suppression of the other sideband and the suppression of the carrier. In the 35MHz range, a suppression of 40dB should be doable. The existing 35MHz clock would be the LO, of which you'd need another channel 90 degrees shifted. Then you's need the difference frequency, in 1Hz steps, possibly from a DDS, and a pair of mixers. This difference frequency is the IF channel, also required in quadrature, eg 90 degrees shifted. I'd stick with a DSS and filter the signal. An AD9854 or such. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 84976
I didn't try it with microblaze. But you should be able to do it. I did it with my power pc on the BRAM as well as the SDRAM. After all its just reading and writing a memory location. So it must work with Microblaze as well :) "Marco" <marcotoschi_no_spam@email.it> schrieb im Newsbeitrag news:d7ku3f$kvu$1@news.ngi.it... > > "Joey" <johnsons@kaiserslautern.de> wrote in message > news:d7kpmg$m53$2@news.uni-kl.de... > > > > You can just make use of pointers and thats easy enough, isn't it? > > > > "Marco" <marcotoschi_no_spam@email.it> schrieb im Newsbeitrag > > news:d7kfc5$fup$1@news.ngi.it... > > > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > > > news:newscache$w5ndhi$t3a$1@lbox.itee.uq.edu.au... > > > > Hi Marco, > > > > > > > > Marco wrote: > > > > > Which C function should I use to perform read or write into block > ram > > > (connected to opb bus with opb bus controller)? > > > > > > > > > > Xio_in8 and Xio_out8 ? > > > > > > > > Not necessary - just read and write it like normal memory. > > > > > > > > Regards, > > > > > > > > John > > > > > > > > > Could you explain, please? > > > > > > Normally, when I write a C program, I create variables... and everything > > is > > > stored in memory, but it is implicit. > > > > > > So, what sohuld I do to read or write into memory? In what way may I > > save, > > > in example a matrix into block ram? > > > > > > Thanks > > > Marco > > > > > > > > > > > > I can use C pointers to point to address space mapped from microblaze? > > > >Article: 84977
Hi Rene We are presently using AD9854 but it is too costly for a USB ADSL2+ modem So i was searching for alternatives. Thats how i reached DDS on FPGA which generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy. bijoyArticle: 84978
Hi I have used Coregnerator FIR filter in my desing. Initially i have used fixed coefficients, which is stored in BRAM area. and the design is working fine Now i want to have the flexiility to change the filter coefficient in the BRAM dynamically, but how do i write to that BRAM used by that particular FIR filter ? (i have one more FIR running in parllalel with fixed coefficients loaded to another BRAM area) Thanks bijoyArticle: 84979
Hi Guys, Is there another standard of PCI for master? i think of this because i have observed that clock trace in the motherboard of personal computer from noth bridge to 3th slot of PCI connector is more than 2.5 inches. We are designing an PCI master in one of our design. Thanks and regards PraveenArticle: 84980
Hi I am having problems trying to add a plb slave device. I edited the user_logic.vhd file of my core and invoked the Create/Import utility. There had been some libraries which I used to create the entity which I had called in this user file. I have a function in this library which XPS cannot access (it appears to be so). I have all the library (vhdl files) also in the same folder where I have my core files. Do I have to add it as a library in the Import utility? Could someone please help me on this? This is the error which I got when I invoked "Generate Netlist" in XPS plb_decoder_0_wrapper (plb_decoder_0) - E:\Test\system.mhs:63 - Running XST synthesis ERROR:Xst:813 - E:/Test/xps_decoder/try02/pcores/plb_decoder_v1_00_a/hdl/vhdl/user_logic.vhd line 53: Body of function MY_FUNCTION not found. ERROR:MDT - HDL synthesis failed! INFO:MDT - Refer to E:\Test\synthesis\plb_decoder_0_wrapper_xst.srp for details ERROR:MDT - platgen failed with errors! make: *** [implementation/plb_decoder_0_wrapper.ngc] Error 2 Regards, JoeyArticle: 84981
Hello Joe, Have a look at USB core of synopsys. Their USB core has AHB interface. You should be more specific about what are you looking for then only i can clarify ur doubt. Regards PraveenArticle: 84982
So for how long is NIOS2 5.0 out? Just received today my NIOS2 1.1 upgrade... Unbelievable fast they are (o; /jediArticle: 84983
I believe you will find the 2.5 inches is the clock trace length allowed on an expansion card not main bus segment. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <praveenkumar1979@rediffmail.com> wrote in message news:1117712445.958682.146120@g43g2000cwa.googlegroups.com... > Hi Guys, > > Is there another standard of PCI for master? i think of this because i > have observed that clock trace > in the motherboard of personal computer from noth bridge to 3th slot of > PCI connector is more than 2.5 inches. > We are designing an PCI master in one of our design. > > Thanks and regards > Praveen >Article: 84984
If you start off with a much higher frequency clock, the MSbit from a DDS that produces a phase output (no need to generate a sine if all you're using is the MSbit) won't be as noisy. In the time domain, the DDS jitter will be up to 1 master clock period, peak-to-peak. The clock can be cleaned up with an external 0 delay buffer as long as all the generated spurs are high in frequency, reducing your jitter to a 25 ps class device. The 0 delay buffer isn't $1. A DDS run by a multiple of 35.328 MHz generating 35.328001 MHz will produce an unfilterable 1 Hz spur. The trick is to find something where the tuning range is all high frequency jitter content. There are plenty of techniques to get extreme precision but they aren't cheap. Consider that the noise of a cheap crystal oscillator will probably wander around the 1 Hz resolution by several Hz depending on temperature, mood, microphonics, and other environmental effects. Your specs may need to be reconsidered. bijoy wrote: > Hi I am using Spartan-3 fpga > > I need to generate 35.328 MHz clock > > I have an external xtal of 35.328 MHz feeding to FPGA. > > From this clock i need to generate 35.328 MHz square wave with fine resolution. > > We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution. > > I tried to generate this by using DDS core provided by core-generator and taking the MSBit of the sine wave samples given by the DDS. But the spurious components generated using this method is too much for my application to accept. > > Is there any-other way out ? > > ( This is for ADSL Modem appliaction. we currently use DDS provided by Analog devices. > > So i thought of using FPGA for this purpose as an alternative solution. ) > > Thanks bijoyArticle: 84985
When having compiler errors always look at the very first error first: > In file included from inbyte.c:2 > > ../../../include/xuartlite_l.h:48:26: xbasic_types.h: No such file or director In this case the compiler simply can't find an include file. Make sure it exists and make sure include path(s) are set for the project wherever they are supposed to be set. Include paths can always be given to a compiler in a command line. /MikhailArticle: 84986
Hi All, I installed EDK7.1i on my computer and built a project. but there are always mistakes. (1): when i download the bitstream to the FPGA board with the iMPACT of ISE 7 it always show a mistake as follows: ERROR:iMPACT: 583-"1":The idcode read from the device does not match the idcode in the bsdl File. (2)however, when i ignore the mistake and then go on to implement the programme "TestApp_Memory" which test the two SDRAMs(this programme is produced with the project automatically), they get the wrong results: sdram1: passed sdram2: failed but when i compile the programmes with EDK6.3i, all of the two sdrams will pass. who knows the reason? please help me! Thank you! linaArticle: 84987
bijoy wrote: > Hi Rene We are presently using AD9854 but it is too costly for a USB ADSL2+ modem > > So i was searching for alternatives. Thats how i reached DDS on FPGA which generates sine wave samples and take the MSbit to generate square wave, that is what found to be noisy. Ok, another lower cost alternative could be running two PLLs. There are these ADF4001 for 8$ @100, they operate between 10 and 200MHz. So by taking one as reference for a second... One would have to play with the numbers. Or two of them plus a CPLD. I remeber an article recently that they were achieving rather low difference frequencies. Yep, the article was about how to generate a second frequency very close to the original for sampling purposes. But without long integeration times in the PLLs. I'll look it up. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 84988
Jim George <send_no_spam_to_jimgeorge@gmail.com> writes: > Jorge wrote: > > Hi, > > > > I am trying to implement the PCI Brige in a Spartan II board (XC2S200). The problem is when I try to program the board I got that error: > > > > ERROR:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. > > > > I read from the manual that I need to associate the ISO PROM with a dummy.mcs file or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM. I don't know how to that to resolved my problem. If someone know how to resolve the problem please help me. > > > > Thank you Jorge > > Jorge, > When Impact asks you to associate a file with the PROM, click the > "BYPASS" button in the file open dialog. This eliminates the need for a > dummy .MCS file for the PROM. I found that when Impact starts up, it > does not scan the chain, you must do this manually by right-clicking an > empty space in the Impact window and choosing "Initialize Chain". Hope > this helped! Also, don't start several instances of the Impact program. Only the first one will recognize the cable. MB [at least for me, with spartan3 starter kit and parallel cable, 6.3] -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 84989
hi -- i got it working fine now --- apparently some driver files were missing --- so i re-installed Xilinx-ise & its working fine now , regards , RehanArticle: 84990
Hi, I've got a question concerning the use of BRAM connected to the Data Cache Unit. Does the processor still use the internal D-Cache Array when BRAM is used? If that were the case, is there any possibility to disable the D-Cache Array, so that the processor is forced to use the connected BRAM? Thx in advance, PitArticle: 84991
Hi Everyone, I am an electrical engineer but I have never had a chance to learn about FPGAs. I think now is a time to make a foray in this world. My problem is I dont know where to start. So I will appreciate if someone can tell me what are the things I will need to start from scratch, like software, hardware etc. Thanks a lotArticle: 84992
"xenos" <shantanu.pathak@gmail.com> wrote in message news:1117730083.658272.266930@f14g2000cwb.googlegroups.com... > Hi Everyone, > I am an electrical engineer but I have never had a chance to learn > about FPGAs. I think now is a time to make a foray in this world. My > problem is I dont know where to start. So I will appreciate if someone > can tell me what are the things I will need to start from scratch, like > software, hardware etc. Thanks a lot You can't go wrong with the $99 Xilinx Spartan 3 kit and free WebPack software. I actually got my kit from Digilent who make them for Xilinx and paid an extra $20 for the larger -400 Spartan 3 chip. LeonArticle: 84993
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:tPDne.35062$GN3.17984@trnddc04... > > I need to generate 35.328 MHz clock > > > > I have an external xtal of 35.328 MHz feeding to FPGA. > > > > From this clock i need to generate 35.328 MHz square wave with fine resolution. > > > > We need a resolution of 1Hz, that means i should be able to change the square wave out put frequency by 1 Hz resolution. Hmm, how about using a cheap VCO based PLL (ala 4046) and a DDS (inside the FPGA) generating lets say 3.5328 MHz. Multiply the 35.328 by four. Run the DDS at this frequency, a 32 bit accu will give a resolution of 0,03 Hz. Use the analog PLL to multiply by ten. This way your frequency resolution is degraded to 0,3 Hz, but this sounds enough for your application. If the loop filter is designed properly the broadband/high frequency jitter is filtered out. Regards FalkArticle: 84994
The PPC caches are built into the processor core. They can be enabled or disabled for any 128MB memory region in real mode (MMU not used) or for any page size in virtual mode (MMU is used). Unless you are running an OS you will most likely run in real mode. I assume that you hook the BRAM to the DSOCM port of the PPC. The DSOCM is not cacheable, never. This is even true if the DSOCM is mapped into a cacheable region. DSOCM has similar access characteristics as cache and thus does not need to be cached. You might want to look at the OCM section in the PowerPC processor block reference guide to learn more about OCM. See http://www.xilinx.com/bvdocs/userguides/ug018.pdf - Peter Pit wrote: > Hi, > > I've got a question concerning the use of BRAM connected to the Data > Cache Unit. Does the processor still use the internal D-Cache Array > when BRAM is used? If that were the case, is there any possibility to > disable the D-Cache Array, so that the processor is forced to use the > connected BRAM? > > Thx in advance, > > Pit >Article: 84995
xenos wrote: > Hi Everyone, > I am an electrical engineer but I have never had a chance to learn > about FPGAs. I think now is a time to make a foray in this world. My > problem is I dont know where to start. So I will appreciate if someone > can tell me what are the things I will need to start from scratch, like > software, hardware etc. Thanks a lot > There are two main flavors of HDL for programming FPGAs, Verilog or VHDL. You could try Verilog first, since it has a lot of free tools available, including free compilers and simulation tools. GPL Cver (a free verilog compiler): http://www.pragmatic-c.com/gpl-cver/ GTKWave (free waveform viewer for GTK): http://www.geda.seul.org/tools/gtkwave/ With the above two free tools you could learn how to program in Verilog. Then you can move on to commercial tools such as Xilinx's ISE and EDK to do real FPGA synthesis. Good luck!Article: 84996
Hey Leon Thanks for the reply. I think I also emailed you directly using my other ID for a private tution on FPGAs. Let me know if you can do that.Article: 84997
You can go through this very good introductory tutorial on PLDs/FPGAs. http://klabs.org/richcontent/Tutorial/fpga/Toronto_tutorial.pdfArticle: 84998
Hi,
I am receiving some data from the uart.I take it and keep it in
memory using a pointer.I use the following condition in my code:
while (!XUartLite_mIsReceiveEmpty(XPAR_RS232_UART_BASEADDR))
{
*uart2ram=XUartLite_RecvByte(XPAR_RS232_UART_BASEADDR);
uart2ram++;
}
then i have to do some processing on the data stored in the memory.I
intend to do that after i receive the complete frame of data from uart.
Now what happens is that the uart takes the first byte puts it in the
memory and comes out of the interrupt handler.then goes back again and
receives the rest of the data.I am not able to figure out y is it
coming out of the handler after taking jsut one byte.shouldnt it take
all the bytes from uart,store it in the ram?
please give some suggestions if you guys can think about any thing that
i am missing.
thanx...
Article: 84999Thanks for the info. But I had a question and pardon my ignorance here. Some one also suggested that I buy Xilinx Spartan 3 kit and free WebPack software. What is the use of that? Is that used to actually program FPGA chip? As far as I understand i can use the tools you suggested to practise simulations and then go towards the hardware to program the chips.
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z