Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Wing Fong Wong wrote: >I know this may seem like a strange question but what is the minimum >bitrate that data can be sent through the RocketIO port? > >Just another question while I'm here, anyone Xilinx people out there >really familiar with the Xilinx ML310 board with the Virtex-II pro fpga? >I just want to know what is the best way to interface 50 odd digital I/O >lines to it. About half of the lines will be input and the other half will >be output. > > > Just using the RocketIO the lowest bitrate is 600Mbps in the Virtex-II Pro. However you can implement an oversampling technique in the logic fabric which allows you go slower, see XAPP572 for more details on the technique we've used for data rates down to 200Mbps. Using the same principles but with greater oversampling 155Mbps is possible with good results. JonathanArticle: 80176
John McCluskey wrote: > On Mon, 28 Feb 2005 08:53:06 -0800, Kevin Brown wrote: > > > Has anyone found the -12 Virtex4 speedfile that are mentioned in the > > latest Xilinx press release? I haven't seen them anywhere on their > > website. > > It's coming out in ISE 7.1, which is shipping this week. Speedprint won't > actually print the values in the speedfile until service pack 1, which > will be out around the middle of March. You noticed that too, eh? I have used the speedprint program from 6.3.3i with the 7.1i speedfile and it seems to work ok (except that rather than a speedup as the press release implies, it seems many items for -10 speedgrade slowed down). I guess the Xilinx marketing department just saw the updated speedfile as a chance to get an extra press release out for Feburary. MarcArticle: 80177
> > it seems that XILINX ISE7.1 is out. Anybody has goy his hands on it? > > Does it now use QT for the GUI? We've had a preview copy for a few days. I'm not sure what QT is, but the GUI looks to be the same as in previous releases. Tuukka Toivonen wrote: > On 2005-03-02, Jim George <jimgeorge_@_gmail.com> wrote: > > I guess the only downside to ISE 7 is that we bought ISE 6.3 just a few > > weeks back :-( > > Is it licensed with the time based license? My impression > is that free upgrades are possible during the one-year license > period. I'll soon try if it is so, as we too > purchased ISE license couple of months back. The bottom of the following page seems to imply you all are correct, although I'll warn you, it's huge (now 3 CD's). http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp MarcArticle: 80178
On 2005-03-02, Marc Randolph <mrand@my-deja.com> wrote: >> Is it licensed with the time based license? My impression >> is that free upgrades are possible during the one-year license >> period. I'll soon try if it is so, as we too >> purchased ISE license couple of months back. > The bottom of the following page seems to imply you all are correct, Well, doesn't work for me. It just says "Our system records indicate you are not entitled to access the Xilinx CD Download at this time." I think the "free upgrades" include only service packs, at least with out license.Article: 80179
http://www.latticesemi.com/products/fpga/xp/index.cfm Lattice XP is announced, pretty much at same time as S3E :) AnttiArticle: 80180
Hi all, I am currently implementing a module which has large number of registers(the datapath is heavily pipelined and lotsa registers). To reduce the area of the design , I have replaced many of the internal registers ,with FFs without a RESET pin. So now all the internal register dont get cleared (reset) while applying an external reset. they just keep on shifting unknown value, until the actual data fills in the pipeline. this is perfectly acceptable for me except for the initial X's I see in waveform, till the actual data reaches to the point. I save around 10-15% area by this way. (in a total size of ~90K). My module is part of a ~1.5Mgates asic. I want to ask you people , whether this method of reducing area will cause any problems(in the design flow) considering the total system. please giveme ur valuable suggestions. thanks a lot Deepu JohnArticle: 80181
"Richard Thompson" <nospam@nospam.com> wrote in message news:vr4b215g9qna9mh4dmn7gok3mgjk3rbss7@4ax.com... > On Wed, 2 Mar 2005 09:56:59 +0000 (UTC), Uwe Bonnes > <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > >>QT is a toolkit available for many systems. >>Otherwise you can also use the Windows Toolkit and use Wine as a >>compatiblity layer, like Nike Engelhard does with Linear Technologu >>switchercad. > > I'm trying to choose between gtk and QT - QT does seem to be more > portable. Your 7.1 posting makes me think that ISE 6.3 isn't using QT, > though - any idea what it does use? If you want to see what Qt looks like, the Pulsonix PCB software I use uses it, and Rowley use it for all their software: http://www.pulsonix.com http://www.rowley.co.uk LeonArticle: 80182
I'm using an Altera APEX20KE with 200k gates on a bought FPGA board. The Clocks 1 and 2 of the FPGA are used by the board, the Clocks 3 and 4 are free. I testet the i2c-core from opencores.org working with the onboard clock on Clock-Pin 2 and it works fine. If I connect (just connect not use in the FPGA, I'm still using the onboard clock from Clock-Pin 2) an own clock to the two free Clock-Pins, the i2c-core doesn't work anymore !!! :-( If I use my own clock on Clock-Pin 3 or 4 as clock-input for the i2c-core, it doesn't work too. I can't understand this behaviour Please Help ManfredArticle: 80183
TheMightyShaman wrote: > > No problem. I had to think a little on how to solve it. t's not a normal > system. > > > > > Yeah, in fact it seems that the microblaze architecture and the available ips aren't really well suited for this type of multiprocessing (i.e. only with pools of shared memories). Much better would be to take advantage of the local memories (maybe using a shared memory too along with the FSL connections). > I would say that most system aren't ready for this since it requires special startup code. > I wished I had time to try it out. > > > > > It seems not so easy to manage: I think that after the initialization sequence there would be anyway problems to manage the same code for both the processors... In fact, I think that it would be rather easy to "jump" to the different code for the processor rather than "branching" on the code depending on the CPU constant signal (identification). What do you think? Having the same program for boths requires a godd startup code to setup the stack and heap pointers correctly for each processor. Having two seperate programs requires a merge of the two elf files into one elf files and also different reset handling (starting to execute a different addresses) > > My view of multiprocessing is more >of distributed processing where each > processor has it's own memory and >the communication between are done > >with message passing using FSL. Very much like to old transputer >concept. > > > > > Yep, it seems one of the model destined to become dominant in the next years (thinking about CELL Architecture)... Yes. Göran BilskiArticle: 80184
Thanks. /MikhailArticle: 80185
Sander Vesik <sander@haldjas.folklore.ee> writes: > Michel Billaud <billaud@labri.u-bordeaux.fr> wrote: > > Jeremy Stringer <jeremy@_NOSPAM_endace.com> writes: > > > > > One thing I guess you could consider is that the GPL can make things > > > difficult for companies that want to integrate your IP block into a > > > commercial product, because of the requirement to redistribute source > > > code. > > > > Well, not a big problem. Such companies are free to contact the author > > for a different licensing of the same source if they have different > > needs. > > Only true if the gpl licenced ip comes to them unmodified. because the modified (improved, hopefully) version of your IP is not _your_ IP anymore. It belongs to all contributors. But what are the other choices ? You can't reasonably suggest other people to improve your work and claim all rights over what they did. That means a "use as is but no right to modify" licensing. So, no improvement to expect. MB -- Michel BILLAUD billaud@labri.fr LABRI-Université Bordeaux I tel 05 4000 6922 / 05 5684 5792 351, cours de la Libération http://www.labri.fr/~billaud 33405 Talence (FRANCE)Article: 80186
MM, A well designed link has 0 errors. Yes, no errors. No reason why you can not model this, and prove in simulation (hspice, nspice) that the link has more than enough margin to be error free. I caused quite a stir when everyone wanted to publish an error rate of 1E-12 (basically one of the common specifications for XAUI, etc.) I said that since we have no errors in a properly designed link, the BER should be identically 0. That is what we published. My opinion: if there are errors, the link was not designed properly, and it is broken (or the transceivers are junk). The midplane through connectors need to be modeled and verified they do not mess up the balance, impedance, etc. but otherwise this arrangement should work error free at any rate supported by our devices (up to 10 Gbs). With no long paths, you have the best situation: no loss to speak of. Austin MM wrote: > On a different topic, what kind of error rate can I expect at 2.24 GB/s? Two > FPGAs I am connecting with this link are on 2 separate PCBs (so called front > and rear Compact PCI cards). The cards are connected with a 2mm Hard Metric > "pass-through" connector. In other words there is a backplane or rather > midplane between the cards, but there are no tracks, the signals pass > directly through the vertical male connector pins sticking out on both sides > of the plane, while each of the cards has a right angle female connector. > > My problem is that I can't really have any errors at all... If that is not > achieavable with RocketIO at the data rate I am interested in, then I guess > I should look at other options. I noticed that there is a slower core in the > Coregen, called High-Speed Data Serialization and Deserialization. I guess I > could use 4 of them, one per each of the bytes in my packet and run them at > 560 MHz. Would this be more reliable? > > > > Thanks, > /Mikhail > >Article: 80187
Jim, Contact your FAE/hotline for upgrade. A 'few weeks' is not a good reason to not allow you to use the latest and best release. Austin Jim George wrote: > Uwe Bonnes wrote: > >> Hallo, >> >> it seems that XILINX ISE7.1 is out. Anybody has goy his hands on it? >> Does it now use QT for the GUI? Anybody using the Linux version? Is the >> WindU compatiblity layer gone? Any other comments? >> >> And when to expect Webpack 7.1? >> > > Xilinx.com says Webpack 7.1 should be out by March 2005. Any time > now... :-) > I'm excited to see that ISE will now include a simulator. I somehow > found ModelSim's interface rather clunky (I also dont make use of most > of the features it offers, like Tcl scripting), and I'd like to see how > ISE Simulator fares. Also, MXE's artificial speed limit makes > simulations more painful. > I guess the only downside to ISE 7 is that we bought ISE 6.3 just a > few weeks back :-( > -JimArticle: 80188
Well, Thanks for the advice, but the problem is that I can't figure out why the block may be unconnected. I checked my code, simulation. So the question is how do I make sure whether this warning is purposeful or not. Any advice is appreciated Thanks MORPHEUSArticle: 80189
I need a vhdl code for a pll.....or any of its components......like a freq divider...VCO.....loop filter and phase detector...thanks Is there anyway that the pll could be implemented onto a FPGA chip.Article: 80190
"Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com... > >After all, what is a RS-FF good for nowadays?? > > The same things that it has always been good for. For a cost of 2 > gates, it gives you a memory. It doesn't need a clock. It remembers an > event until you have time to deal with it. It's ideal for handshaking, > and for communicating between different clock domains. Can you name > any other digital circuit which is so versatile, at such a small cost? > Even if you ignore the 'cost', as you might do in an FPGA > implementation? Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always free. So why asking for trouble and doing stone age handshakes when there are proven solutions using standard methods (here, D-FlipFlops)? I wouldnt waste a nanosecond thinking of RS-FlipFlops made of gates. Regards FalkArticle: 80191
Austin Lesea wrote: > Jim, > > Contact your FAE/hotline for upgrade. A 'few weeks' is not a good > reason to not allow you to use the latest and best release. > > Austin > > Jim George wrote: <snip> >> I guess the only downside to ISE 7 is that we bought ISE 6.3 just >> a few weeks back :-( >> -Jim Hi Austin, We purchased ISE 6.3 from Xilinx.com through the Xilinx University Program, there was no FAE involved. Is there someone else I can contact? Thank you. -JimArticle: 80192
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> schrieb im Newsbeitrag news:d0305q$kc55@xco-news.xilinx.com... > Sudhir.Singh@email.com wrote: > > Hi Group, > > I am implementing a multichannel IIR filter on Virtex II fpga and the > > filter memory is implemented using the BlockRAM. Is there a way to > > reset all memory contents to 0, without having to sequentially write > > 0's into the RAM. > > > > Thanks in advance. > > Sudhir > > > No. But you might be able to use a trick. The virtex-II BRAM has Read-before-Write mode, which means at the very same clock cycle you can read a memory location and write it. So maybe you can do a clever readout of your memory (last read for filter operation) and in the same moment clear it (write all zeros) Regards FalkArticle: 80193
genlock wrote: > I need a vhdl code for a pll.....or any of its components......like a > freq divider...VCO.....loop filter and phase detector...thanks > > Is there anyway that the pll could be implemented onto a FPGA chip. > This question has been asked before (search the archives at fpga-faq.com) Anyway, the answer depends on the kind of PLL you're looking for. RF PLL? No. PLL to get a clock for on-chip or off-chip use? Many FPGAs include onboard PLLs (Xilinx offers what they call a DLL, makes use of a string of inverters with a mux to set the delay). These are pre-built sections you can use. If you need this for low-frequency applications (where all the analog signals are sampled, for example a video signal), you can use Coregen to generate all the required portions (VCO -> NCO, loop filter -> FIR core, phase detector -> multiplier). -JimArticle: 80194
Jim George wrote: > Austin Lesea wrote: > >> Jim, >> >> Contact your FAE/hotline for upgrade. A 'few weeks' is not a good >> reason to not allow you to use the latest and best release. >> >> Austin >> >> Jim George wrote: > > <snip> > >>> I guess the only downside to ISE 7 is that we bought ISE 6.3 just >>> a few weeks back :-( >>> -Jim > > Hi Austin, > We purchased ISE 6.3 from Xilinx.com through the Xilinx University > Program, there was no FAE involved. Is there someone else I can contact? > Thank you. > -Jim uh.. same here ;o) lukaszArticle: 80195
"Austin Lesea" <austin@xilinx.com> wrote in message news:d04mpa$1as5@cliff.xsj.xilinx.com... > Jim, > > Contact your FAE/hotline for upgrade. A 'few weeks' is not a good > reason to not allow you to use the latest and best release. > > Austin > Go for it all you early adopters of the 'latest and best'! And let me know when you've reported enough bugs to fill a service pack 2 release. ;-) In the depths of cynicism, Syms.Article: 80196
"genlock" <genlocks@gmail.com> wrote in message news:1109779833.145315.64410@o13g2000cwo.googlegroups.com... >I need a vhdl code for a pll.....or any of its components......like a > freq divider...VCO.....loop filter and phase detector...thanks > > Is there anyway that the pll could be implemented onto a FPGA chip. Xilinx has a phase detector in a app. note. The dividers should be quite easy to implement. The VCO and loop filter will have to be outside the FPGA. LeonArticle: 80197
>A well designed link has 0 errors. > >Yes, no errors. > >No reason why you can not model this, and prove in simulation (hspice, >nspice) that the link has more than enough margin to be error free. Is there any simple way to verify that a design actually does get such a low error rate? The fiber guys have a neat trick. They insert enough attenuation so they get enough errors to measure, then back calculate the expected error rate without the attenuation. Theory and practice agree well. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 80198
Still no comments on the newsgroup. Those of you who want to (re)visit Howard Johnson's presentation can do this by clicking on http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf Peter Alfke, Xilinx ApplicationsArticle: 80199
Peter, I suppose they are still digesting Howards presentation.... Bottom line, the new SparseChevron(tm) package for V4 has substantial benefits which enable the high speed designs to work. It doesn't help to have better dI/dt if all it does is create SI problems. Perhaps we design our IOs to meet requirements, such that they can actually be used? (Answer: yes we do. It is part of the requirements not to 'blow the lid off' with dI/dt that would be of no benefit to a customer). The key is what is going to happen when all the IOs (and CLBs) in your application do what you want them to do: will the noise trash the IO? will the noise cause so much jitter during the "boing" (I love HJ's sound effects...) that the timing margins are violated, and errors result? Errors caused by system jitter (which in turn is caused by ground & supply bounce, which in turn is caused by SSOs and logic toggling) is the number one SI problem in high speed designs today (and not exclusive to FPGAs at all). Austin Peter Alfke wrote: > Still no comments on the newsgroup. > Those of you who want to (re)visit Howard Johnson's presentation can do > this by clicking on > > http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf > > Peter Alfke, Xilinx Applications >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z