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Hi, Thanks for the response, but I now have problem with using the SVF file. I used the svf2xsvf and play xsvf utilities provided by APP058. Does anyone know a valid way for using these utilities? If I have my device programmed in IMPACT and then used this utility, I can see TCLK, TMS, and TDI, I don't see TDO for some reason. If I used this utility without having my FPGA programed in IMPACT. I don't see any TAP pins at all. Has anyone successfully used these tools???? Thanks, AnnArticle: 80126
Hi, I am using the Xilinx MGT as PCI-Express specification (Endpoint). As specified in the MGT user manual, we use the Epson's crytstal as the reference clock (125MHz) needs by MGT. But when the add-in card plugs to mother-board, the MGT seems can not lock to the signals from PC. The RXLOSSOFSYNC jumps back and forth between accquired (2'b00) and non-sync (non-zero) state. Can anybody advise me how to debug this. Any comments is appreciate. Thanks. JasonArticle: 80127
Reconfiguring the part woud do it, but is probably unrealistic. Remember, no RAM affords itself the luxury of a general reset line, connected to every cell. So it would add a transitor to every cell. (25 to 50% added overhead?) Nobody would be willing to pay for it... Peter AlfkeArticle: 80128
Hi, It likely doesn't lock onto the data stream due to the MGT CDR range and the tolerances of the clocks in the system. The 125 MHz oscillator you have is probably +/- 100 ppm. It is likely that the motherboard is providing a 100 MHz reference clock +/- 300 ppm, possibly spread spectrum. It is this same refclk that is used by the root complex. This is allowed by the PCI Express specification. The end result is you could get a 400 ppm difference, which is out of range of the V2Pro / V2Pro-X MGT CDR to reliably lock. This is related to a similar topic that Antti Lukats corrected me on some months ago regarding SATA... However, if you could use what is called the "common clock configuration" you can reliably lock. To do this you leave off the 125 MHz oscillator and use a clock conversion chip to convert the 100 MHz reference clock from the connector to 125 MHz for the MGT. Hope that helps, Eric Jason wrote: > > Hi, > I am using the Xilinx MGT as PCI-Express specification (Endpoint). > As specified in the MGT user manual, we use the Epson's crytstal as > the reference clock (125MHz) needs by MGT. But when the add-in card > plugs to mother-board, the MGT seems can not lock to the signals from > PC. The RXLOSSOFSYNC jumps back and forth between accquired (2'b00) > and non-sync (non-zero) state. Can anybody advise me how to debug > this. Any comments is appreciate. Thanks. > > JasonArticle: 80129
Hello, I have also posted this message on the niosforums site. Hopefully someone here will have an insight to my problem. I am developing on a system that is very similar to the Nios II evaluation kit. I am trying to transfer data to and from the LAN91C111 Ethernet MAC but have noticed some problems. The MAC is connected to the Nios II in exactly the same way as on the demo board. It appears as though the Altera model for the interface to the LAN91C111 is incorrect. The data sheet for this device shows the timing when the LAN91C111 is used in asynchronous mode, and although the nRD & nWR signals meet the timing shown in the data sheet, the minimum cycle time appears to be violated. In the SMSC LAN91C111 FAQ and Application Note 9.6, it clearly states that the minimum cycle time should be either 80ns or 100nS depending on whether the interface is operating as half or full duplex. When I try to use the DMA to read from the LAN91C111, it see a cycle time of 40nS (when clocking the Nios II with 50MHz). The timing for the LAN91C111 is not directly accessible from the SOPC builder, but looking at the class.ptf file for the LAN91C111, it shows the following: Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; in the SYSTEM_BUILDER_INFO section. If I am interpreting this correctly, this will result in the 40nS cycle time for Read and Write operations which is in conflict with the SMSC FAQ and the App Note. I have measured this using an oscilloscope. Now, this wouldn't be a huge problem for me, if I was able to change it, but it doesn't seem to be vary if I change the class.ptf file so that each of the above times are, say, 40nS. This is really the second part of my question. Should it be possible to change the timing as defined in the class.ptf file? I have tried changing it outside of the SOPC builder but it compiles the same regardless. Perhaps there is a trick here? If anyone has had any luck with using DMA transfer to and from the LAN91C111, it would appreciate any tips you might have. Many thanks, sja.Article: 80130
I think Howard Johnson gave a super presentation, definitely "technical". We had 800 listeners, and we got lots of questions. From my point of view, it was a smashing success. The newsgroup is still very quiet, maybe that is better than the biting and bitching after the prior seminars ... Coincidentally (?) Altera had a press release about Signal Integrity on the same day. Their David Greenfield (of comp.arch.fpga fame...) claims that "benchmarks demonstrate another significant advantage...", but their press release tells us that Altera's benchmark claims come from simulations based on IBIS models. On our board, we measured and compared the real hardware, for both families, under identical condition. I prefer an 8 GHz Tektronix scope picture over an IBIS-based simulation any time of the day. More work, more expensive, but definitely more believable and more encompassing. Peter Alfke, from home.Article: 80131
Petter Gustad <newsmailcomp6@gustad.com> wrote: > "Michael Polovykh" <kefir@rissa.ru> writes: > > > So you have a fridge. Put Cyclone into it during PLL work for 30minutes :) > > And tell us about this experiment - we are interested in it too :) > > I dubt his fridge will go as low as -20 ?C. Considering he is from .ru and its winter, he just needs to leave it outside overnight. > > Petter -- Sander +++ Out of cheese error +++Article: 80132
I know this may seem like a strange question but what is the minimum bitrate that data can be sent through the RocketIO port? Just another question while I'm here, anyone Xilinx people out there really familiar with the Xilinx ML310 board with the Virtex-II pro fpga? I just want to know what is the best way to interface 50 odd digital I/O lines to it. About half of the lines will be input and the other half will be output. -- Wing Wong. Webpage: http://wing.ucc.asn.auArticle: 80133
blackduck <rg66@le.ac.uk> wrote: > Hello friends > > I am implementing a design which has about 250 32-bits unsigned numbers > which have to be added to give the final outcome, since it is a very > large number of elelments I think implementing this operation on FPGA > would be very slow (250 cascade adders), I am thinking in using > Carry-Save adders scheme to avoid the long propagation times due to the > carry, but I am not sure now if it would really help. I need to carry > out this additions in the shortest possible time, Carry-Save arithmetic > would be helpful? is there any other scheme I can use to speed up the > addition? (at some point I will need to increase the number of > quantities to be added far above 250). You may be limited by how many adders fit in the fpga. If you can fit 250 adders in it (125 ; 62 ; 32 ; 16 ; 8 ; 4 ; 2 ; 1 in stages) and route it all, then you can get the answer in 8 propagation delays of a 32bit add (or 8 cascades). If you need faster you probably need to use merged 4-input adders and similar. > > Many Thanks > -- Sander +++ Out of cheese error +++Article: 80134
blackduck <rg66@le.ac.uk> wrote: > Many thanks for your response, > > Actually the problem is as you said, 250 filters are giving me at time > n 250 different values, then i need to get the addition of those 250 > values at time n+1, and this new value conforms an input for a > comparator. Each data is a 32 bits unsigned integer, which is generated > by a lowpass filter at 300MHz, is in fact the impulse response of such > a filter. > 300Mhz * 250 * 4B = 300 GB/s. I *SERIOUSLY* doubt that you can get that high bandwidth into a single fpga. It sounds like that you should be looking at a number of FPGA-s, say 8 to do the first stage additions and feed the results to the ninth that then adds their results (the first level fpgas need not necessarily send just one numebr each to the final one, depending on how you have on-chip vs io pin resources). -- Sander +++ Out of cheese error +++Article: 80135
KCL <kclo4_NO_SPAM_@free.fr> wrote:
> well you make a additionner that add 2 number
> you put 125 additionner in parrallel to add your 250 number
> next level you use 63 additionner to add the 125 result of the first level
> and you do that till you have only 1 result
> so in final you will have 125 + 63+ 32+16+8+4+2+1=251 adders
^^
62. you by-pass one of the results from the 125 adders to the 32 adders
directly. If you have 63 adders at that stage, one of them will do a
pointless "add to zero" operation.
--
Sander
+++ Out of cheese error +++
Article: 80136Since you are at a university you can get a copy of Synplify Pro through our university program which should fix your problem. cecilia annovi wrote: > I've found it anyway...thank you! but with the Quartus II I've many problems > to use this package... > > Cecilia Annovi > > > "Martin Schoeberl" <martin.schoeberl@chello.at> ha scritto nel messaggio > news:xJ1Vd.72929$2e4.70358@news.chello.at... > >>>www.perso.ens-lyon.fr/jeremie.detrey/FPLibrary/ >>> >>>i tried the routines in xilnx ise + modelsim...it worked fine. >> >>The link seems to be broken. >> >>Martin >> > > >Article: 80137
MM wrote: > On a different topic, what kind of error rate can I expect at 2.24 GB/s? Two > FPGAs I am connecting with this link are on 2 separate PCBs (so called front > and rear Compact PCI cards). The cards are connected with a 2mm Hard Metric > "pass-through" connector. In other words there is a backplane or rather > midplane between the cards, but there are no tracks, the signals pass > directly through the vertical male connector pins sticking out on both sides > of the plane, while each of the cards has a right angle female connector. > > My problem is that I can't really have any errors at all... If that is not > achieavable with RocketIO at the data rate I am interested in, then I guess > I should look at other options. I noticed that there is a slower core in the > Coregen, called High-Speed Data Serialization and Deserialization. I guess I > could use 4 of them, one per each of the bytes in my packet and run them at > 560 MHz. Would this be more reliable? Howdy Mikhail, Unless you have something weird going on in your system, you should be able to achieve "error-free" links (better than 1E-12, let's say). Weird being something like noise on your MGT power or ground, or reference clock quality problems. With RocketIO, you trade fewer pins for a little more design complexity (due to the higher speeds). Thousands of people doing it (error free) though, so it works. Have fun, MarcArticle: 80138
regarding the first warning, it just means that you have a bit by name "seriesiii_chan1_reg_2" which is not changing and having a constant value of either '0' or '1'. the second warning says that you have one module(or port) not connected in its instantiating module. this you have to look into if it was purposeful or not.Article: 80139
Hmmm, first think I found using google: http://groups.google.ca/groups?selm=3A720DD4.F2E0032C%40xilinx.com&output=gplain Doh! Sudhir.Singh@email.com wrote in message news:<1109720819.438250.230050@g14g2000cwa.googlegroups.com>... > Hi Group, > I am implementing a multichannel IIR filter on Virtex II fpga and the > filter memory is implemented using the BlockRAM. Is there a way to > reset all memory contents to 0, without having to sequentially write > 0's into the RAM. > > Thanks in advance. > SudhirArticle: 80140
On Wed, 09 Feb 2005 06:20:28 -0800, andyesquire wrote: > Hi, > > I'm working on a design that will require external memory, and I'm > trying to find some learning resources for Xilinx DDR SDRAM memory > controllers. I don't have much VHDL/FPGA design experience and all the > resources I can find assume that you implicitly know how to use a > memory controller. > > The Xilinx models from their web site just unzip to a whole bunch of > vhdl files and their documentation is not user oriented - it's an > explanation of how their controller is implemented (I don't care!). > > The memory controller performance/specification isn't important to me > right now, but without being able to simulate a controller I can't > proceed further with my circuit design. I'm using ISE and ModelSim. > > Do I need to go down the Denali route and purchase a memory model then > lean on their technical support? Or should I just give up and get a > consultant to help? I agree 100% about those memory controller app notes - while it's important to know how they work internally, they really fall down on how to hook them up internally, and to a lesser extent externally. (my particular experience was the DDR app note for spartan3). We finally ended up giving up on the thing and reused a slower design we had done for v2. Most of the notes seem somewhat evolutionary from some old reference design where they keep replacing the tricky bits, so if you dig back far enough to one of the really old notes (maybe it was for virtex?) they have some info about what to do with the pieces they give you, but it's really painful.Article: 80141
"Benjamin Menküc" <benjamin@menkuec.de> wrote in message news:<d000me$iu2$05$1@news.t-online.com>... > If I was a fpga manufacturer I would put 1 or 2 people in this newsgroup > just for answering questions. That would be the most effective publicity > possible, I guess. > > regards, > Benjamin > > PS: Hello Peter :) You gotta clarify "people". Engineers, techies sure. Anyone that can back up what they say will be appreciated and more than welcome. Marketing droids or wannabes, there's enough of that going on here already. :) In particular comes to mind the A droid that keeps bragging about their supposed 39% but can't back it up.Article: 80142
Hi Ranbir! So, are you looking for Americans to move to India? It's so great that India is finally going to take care of all the engineers here who lost their jobs due to outsourcing. Will I be able to afford a Qualcomm-chipset based phone with the pay I get? Thanks in advance! reachranbir@gmail.com wrote in message news:<1109664726.181045.112170@z14g2000cwz.googlegroups.com>... > Hi, > I am Ranbir from eQURA Consulting. > Guys, my client, which is a San Diego based wireless telecom giant. > They were the original inventors of CDMA technology. > > They have recently set up a next gen design centre here in Bangalore, > India. > We are looking at various profiles, starting from frontend, backend to > verification managers. > > If interested do contact me on +91 09845365740 > ranbir@equra.comArticle: 80143
Hello again. AL wrote: > Hi, Thanks for the response, but I now have problem with using the SVF file. I used the svf2xsvf and play xsvf utilities provided by APP058. Does anyone know a valid way for using these utilities? Also check out XAPP503. > If I have my device programmed in IMPACT and then used this utility, I can see TCLK, TMS, and TDI, I don't see TDO for some reason. If I used this utility without having my FPGA programed in IMPACT. I don't see any TAP pins at all. Has anyone successfully used these tools???? Thanks, Ann IIRC, these tools are meant to configure and/or program devices with an application like iMPACT. It seems to me that you are trying to use iMPACT as a generic tool to introduce/extract information from your device using JTAG. I don't know if this is actually possible. I know that you can check the TDO values returned with a value and mask, but I don't remember seeing commands that dump arbitrary TDO values in a comfortable format for post-processing. You will need a better tool to do that. I use my own Java tools to read and write the BSC registers of my designs through parallel or USB interfaces. They are not plug-n-play but if you are interested I can make part of them available for download. Cheers. -- /"Malgr=E9 les murs qui ensevelissent PabloBleyerKocik / LA CROIX DU SUD pbleyer / Est le seul avion qui subsiste" @embedded.cl / -- A=E9roplane, Vicente HuidobroArticle: 80144
I'm confused by the numeric API functions for microblaze.
Dizzy!Dizzy!
Is there any docs that talk about these functions in detail,the docs
Xilinx provide seems too brief.
Or at least you can help me about this:
What is the channel in gpio functions and where does it defined?I
cannot find it in Xilinx docs.
Article: 80145"Chinix" <qinxi@mail.csdn.net> schrieb im Newsbeitrag news:1109745595.068645.314800@g14g2000cwa.googlegroups.com... > I'm confused by the numeric API functions for microblaze. > Dizzy!Dizzy! > Is there any docs that talk about these functions in detail,the docs > Xilinx provide seems too brief. > > Or at least you can help me about this: > What is the channel in gpio functions and where does it defined?I > cannot find it in Xilinx docs. > channel is "new" in GPIO ver 3.1 it is either 1 or 2 depending if you want first or second port of an dual GPIO AnttiArticle: 80146
Hallo at all I have created my IPCore which is connected on PLB Bus. Now I created a Simulationfile and want to launch it. The ModelSim starts and agter a little bit compiling launch a Error: # ** Error: (vcom-11) Could not find proc_common_v1_00_b.proc_common_pkg. # ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_b/hdl/vhdl/ipif_pkg.vhd(303): Cannot find expanded name: proc_common_v1_00_b.proc_common_pkg. # ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_b/hdl/vhdl/ipif_pkg.vhd(303): Unknown field 'proc_common_pkg'. # ** Error: C:/EDK/hw/XilinxProcessorIPLib/pcores/ipif_common_v1_00_b/hdl/vhdl/ipif_pkg.vhd(304): VHDL Compiler exiting # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed. Can it be that the IPIF_pkg of ipif_common_v1_00_b is bad? thks cauArticle: 80147
The SP-3E datasheet only talks about external programming hardware regarding the SPI configuration Flash. Is there a bootstrap programming method planned for these Flash memories (eg. using the JTAG interface with the usual ISE configuration tools)? Regards. -- PabloBleyerKocik /"I've finally learned what `upward compatible' pbleyer / means. It means we get to keep all our old @embedded.cl / mistakes." -- Dennie van TasselArticle: 80148
"Pablo Bleyer Kocik" <pablobleyer@hotmail.com> schrieb im Newsbeitrag news:1109751233.384425.271710@l41g2000cwc.googlegroups.com... > > The SP-3E datasheet only talks about external programming hardware > regarding the SPI configuration Flash. Is there a bootstrap programming > method planned for these Flash memories (eg. using the JTAG interface > with the usual ISE configuration tools)? > > Regards. you mean similar feature to Altera JIC? Isn't it too early for those questions? :) AnttiArticle: 80149
Very interested for my new embedded product. Some questions: for when the first samples? for when on the production market? are the s3 and s3e FPGA pin compatible? Thanks Laurent www.amontec.com
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z