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As I am looking for a job and also thinking about moving to Asia, I'm interested by your own experience. Which country are you from?? Do you think it is easy for european (french exactely) to move to India (because it seems to be here there is the most part of R&D center in EDA)? Even more for young graduate because over there all companies wanted 2 year experienced engineers not less not more. And jobs in france look more and more making specifications & documentations than doing hardware developpement. Regards, Alexis <akuchlous@gmail.com> a écrit dans le message de news: 1109058331.199826.275910@z14g2000cwz.googlegroups.com... > Hi > > I work for a EDA company, working on FPGA synthesis tool. > > Two fpga tool lead in market. > One is our company( to keep company name out), and other is from > synplicity. > > An under-grad approached me for help in getting his design into an > FPGA, and verify it. > > So I thought it would be a good exercise for me to do some pure design > stuff and verify it. > > As for work, I am satisfied out here, for I get to do the best stuff in > EDA, and given the opportunity and salary out here, it was a wise > decision to move back to India. > > -Ankur > > mail me at gmail.com@akuchlous, if u have any more questions. > (reverse the email id). >Article: 79626
"SD" <sourabh.dhir@gmail.com> wrote in message news:1109061888.331205.165020@z14g2000cwz.googlegroups.com... > Hi all, I have a signal algorithm implementation design on FPGA. I > simulated the design in Modelsim and now I want to export the output > values and compare with those of the Matlab. Can somebody suggest me > how to do that? > > I read the input values of my testbench from the same input file which > I use for Matlab input. > > I tried using VIEW --> LIST and then dragging the signals I want to the > LIST window but that doesnt seem to be solving the problem. It creates > duplicate input values too whenever the "DELTA" value is high. I dont > understand whats DELTA in the LIST window? Delta is how as event based simulator schedules evaluation of the logic. If one opens a list window, tools, window preferences, triggers in Modelsim, there are options for deltas and triggering the list window. I have not used these for several years, and you might have to play around with the settings and or read the manual. When I used Matlab several years back, the testbench used file IO to write out data that needed to be compared against the Matlab data. Unfortuanately, due to a NDA, I cannot share more with you. Good luck - Newman > > I would appreciate if somebody could comment on this??? > > Thanks in advance. > > SD >Article: 79627
i think asics.ws have a phy IPCORE for usb 1.1 Jonathan <stud_lang_jap@yahoo.com> a écrit dans le message de news: 1109073272.206001.282600@o13g2000cwo.googlegroups.com... > Hello Guys, > I am interfacing the synopsys USB 1.1 core with the PHY. But the > problem is the USB core side transreciever signal doesnot match the PHY > signal. As any one interface USB core to PHY?. If so can you please > provide more information about it. > Is USB 1.1 also having UTMI interface to PHY? I searched the internet > but could not get the information. > > Thanks and regards > Williams >Article: 79628
any news Sylvain ? have you play with wb_gpio ipcore ? regards Jonathan "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le message de news: 420fb7ae$0$22479$ba620e4c@news.skynet.be... > Hello, > > I'm trying since yesterday to interconnect the opencore mac to a > microblaze design. > After several problems solved, I'm stuck. > > The "Generate netlist now works fine" but When I try to "Generate > bitstream", > I have three errors from NgdBuild : > > > ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' > could > not be resolved. A Pin name mispelling can cause this, a missing edif or > ngc > file, or the mispelling of a type name. Symbol 'wb2opb' is not supported > in target > 'spartan 3'. > ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 'opb2wb' > could > not be resolved. A Pin name mispelling can cause this, a missing edif or > ngc > file, or the mispelling of a type name. Symbol 'opb2wb' is not supported > in target > 'spartan 3'. > ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' > with > type 'eth_top' could not be resolved. A Pin name mispelling can cause > this, a > missing edif or ngc file, or the mispelling of a type name. Symbol > 'eth_top' is > not supported in target 'spartan 3'. > > > For the wb_ethermac core, I've created a file that includes the eth_top of > the > ethernet mac core on opencore and present the interface to the outside > world. > I've done this as a ISE project then I synthetized it to have a .ngc file > (because > I have both VHDL & Verilog there) then I created an IP from this netfile > and my vhdl top file. > > Any one has a clue on what to do ? Has anyone make this work ? (I'm using > ISE/EDK 6.3) > > > Thanks, > > SylvainArticle: 79629
Hello @ FPGA people, I have been reading some threads on TRISTATE STUFF on this forum and yet I am not sure about the following question: Is it possible to use a tristate VHDL description in a hierarchical design that is in a sub module or do I have to use it only on the top level description WHEN using QuartusII version 4.2 ? Thank you for your opinion. RgdsArticle: 79630
"Antti Lukats" <antti@openchip.org> writes: > finally I can announce it: > > http://www.eubus.net/hydraXC > > Reconfigurable "dream" - small and fully reconfigurable computing module. Looks very nice, I think I will buy one. I was considering to buy a Xess XSA-3S1000 and modify it to be configurable over USB and have a LVDS port instead of VGA, but your board has already everything! (And much more.) I would like to know more about it, especially about the LCD-TFT and touch-panel connector and the system management thingy. Can you connect it directly to a TFT panel that I happen to have lying around? Can you configure the FPGA directly from USB without having to write the bitstream to the flash? That sort of questions. Essentially, I would really like to look at the schematics of the HydraCX. Is that possible?Article: 79631
Ali Dixon wrote: > I'm trying to build a simple core in which decode and register file access occurs in the same cycle on a virtex II pro board. > > Decode completes in the half clock cycle after the positive edge. Any ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge? Ali, I suppose you want to use the dual=ported BlockRAM in Virtex-II. Those two ports are completely independent as far as addressing and control is concerned. They only share the data. So you can use one port to write on one clock edge, and use the other port to read out on the other (or the same) clock edge (or even use a completely different clock). The issue will be speed. You obviously should not try to read something that is not yet reliably stored in the data latches. So do a timing analysis. Our dual-ported BlockRAMs are really easy to understand, as long as you realize that the incoming Address, Data, and WE control are all registered. So nothing happens without a clock edge, even in read mode. That's desirable in many cases, not desirable in others, but it is "non-negotiable". Also, we throw in a read data output even when you write, and you can choose to read the old or the new data, or even to maintain the previous data on that output port. Now, if you want to use the LUTs as dual-ported RAM, then the structure is different, and you can read without using a clock edge. Peter Alfke, Xilinx ApplicationsArticle: 79632
"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message news:87oeedx1b7.fsf@filestore.home.gustad.com... > "Michael Polovykh" <kefir@rissa.ru> writes: > >> "Petter Gustad" <newsmailcomp6@gustad.com> wrote in message >> news:87zmxy871e.fsf@filestore.home.gustad.com... >>> "Michael Polovykh" <kefir@rissa.ru> writes: >>> >>>> So you have a fridge. Put Cyclone into it during PLL work for 30minutes >>>> :) >>>> And tell us about this experiment - we are interested in it too :) >>> >>> I dubt his fridge will go as low as -20 °C. >> My fridge can go down to -32°C. > > Impressive, my freezer wont even go that low. My fridge goes down to > +2 °C. If I want -32 °C I will have to put it outside - on an extreme > cold winter night... hmm, :) and where do you store meat? i do it in refrigerating chamber of my fridge. ;) > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 79633
How does one go about accessing the external RAM on the Spartan 3 starter board? Is there any VHDL code available anywhere for doing this? Also, how would one load up this RAM with data from the PC? PhilArticle: 79634
For register file reads, why not access the BlockRAM with the lower address bits anyway and only "use" the result if the BlockRAM was selected? This assumes the register file is a contiguous chunk of memory and the read port wouldn't be needed for something else that cycle. "Ali Dixon" <ali@cs.bris.ac.uk> wrote in message news:ee8c0f8.-1@webx.sUN8CHnE... > I'm trying to build a simple core in which decode and register file access occurs in the same cycle on a virtex II pro board. > > Decode completes in the half clock cycle after the positive edge. Any ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge? > > Thanks in advanceArticle: 79635
> > This exists because some IP is very tightly bound to its IO pin type, > > such as PCI or DDR SDRAM. We requested this feature from Xilinx a few > > years ago specifically so that we could use the PCI logicore netlist > > inside of a wrapper in EDK, without hand editing the top level VHDL. > > YES and NO. > EDK can work as described, YES. > but the IO buffers are NOT inside the PCI logicore netlist! > PCI IO buffers for Xilinx OPB PCI core are instantiated in the VHDL code > as can be seen above and NOT inside the PCI logicore netlist! > and as of DDR SDRAM core there the _I _O _T is used as normal I think you have missed the point. I make absolutely no mention of EDK IP. First with respect to the PCI logicore, which if purchased from Xilinx is provided with an EDF netlist, and a VHDL netlist (or as some would say "structural VHDL") that instantiates this core netlist, the IO pins, and a user configurable module. To use this entire package, without editing any of the IP core from the vendor, which is delivered as both VHDL and a netlist, one must do as I described. This still requires some editing of the contraints that are provided by the vendor, but only for location in the hierarchy. Secondly, DDR SDRAM was cited as an example because separating out the tristate buffer from the DDR register is counter to the architecture of the FPGA. The IO cell in virtex2 contatains a tristate buffer and a DDR register, each of which only exist in this type of cell. Breaking off the tristate buffer from the DDR register does not provide for any sort of meaningful improvement in the hierarchy. Rather, it confuses the issue. Arguments for breaking the hierarchy at this point that have been presented in this newsgroup are: using chipscope at the top level of a hierarchy; or the creation of a vendor agnostic design. Given that the signal between the DDR register and the OBUF, or the IBUF and the other DDR register are not observable, as the wires simply do not exist in the architecture, obviates the first argument. The fact that the DDR register and the IO buffer are both vendor specific, and vendor unique, obviates the second argument. As the FPGAs get more encompassing IO structures, as with V4, it makes more and more sense to bind the IO structures which will include shift register, differential pins, etc, into the cores themselves. One is kidding himself if he believes he can do a high performance and cost effective design without expressly instantiating specific architectural elements. The IO structures are no exception. This is not to say what Xilinx did with the EDK and separating out tristates did not make sense. It did, when specific IO pin types and IO structures did not need to be called out from the underlying core. For example, many people new to FPGAs and the coreconnect bus architecture have started by using the GPIO module to interface to their own IP inside the chip. This is a good example of where one may want to use the same IP for on chip or off chip interconnect, and as such, not binding the IO pins to the core results in one rather than two cores being created. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 79636
"Tom" <tagerbaek@epo.org> wrote in message news:ee8bfea.-1@webx.sUN8CHnE... > A HW-designer's lament: I'm new to FPGA's, but not to HW design in general. Xilinx/Altera et al all characterize their FPGA's in terms of (very nice) HW features. Great, you buy an ev-kit, fire up the SW, only to discover that the SW, i.e, HDL, hides the HW from you. A design that could have been hand-wired in a matter of hours (using imaginary discrete chips having the function-blocks of the FPGA) now turns into an aggravated struggle against the SW (others have described it as pushing a rope, or searching for an incantation which will magically make the synthesis tool behave). Isn't there some way to do direct design instead of the tedious imposing of constraints upon an excruciatingly stupid piece of SW? Thoughts? Cheers, Tom One more thing: You can use the Xilinx/Altera primitives to instantiate your logic exactly. I end up having to include MUXCY or MUXF5 primitives manually often enough to meet my speeds even with an advanced 3rd party synthesizer. Arrays of instances and generate statements allow me to do wider operations easier without sacrificing too much in the way of readability. There are spots I've even resorted to manually instantiating LUTs to have something I can always RLOC to keep my critical timing close. Often, however, just knowing the silicon will allow you to code in a form that the synthesizer has a better chance of doing the right thing from the start. I find myself coding in Verilog to get the full data flow in a concise form then checking the timing and iteratively constraining or infusing primitives to get my timing. If you need 2.5 or fewer logic levels to run at 250 MHz, it's easier to code with Verilog to get the paths that automatically fall to 1 or 2 levels of logic and spend time getting the other paths chopped down through redesign, pipelining, or primitives. Schematics wre fun until I had to start sitting through 180 page design reviews. I am soooo glad I have Verilog.Article: 79637
All, Igor has his case now submitted, and it was escalated due to its nature (basically saying "lines down" makes that happen). As of 8:30 AM PST 2/22/2005 here in San Jose we have folks on it. Thanks to all who posted. For those interested, I will probably post the results here (if Igor agrees) as there seems to be some interest in lot related failures. Generally speaking, lot related failures are almost always design related: either the lot silicon is a little faster, or a little slower (but within spec's) than the previous lot, and an unconstrained timing path doesn't work. Sometimes IOs are a little stronger, or a little weaker, and that too is within spec but makes a difference in a design. The fabric speed was the case of the customer who designed their own FIFO (and didn't understand schrnoization circuits), and "lot" related problems. In this case, we have just started, so Igor will learn failry quickly what the differences are between the lots, and we will help resolve what the cause of the problem is, and provide solutions. Thanks again to all who have interest in this sort of posting, as it gives us a chance to educate folks on the services we offer (the hotline), the escalation procedures for hot cases (lines down), and the nature of this particular kind of problem, and the types of likely resolutions we often find. In no way am I implying that Igor has a funny path in his design: I am only suggesting that this is often our experience. Rarely (VERY RARELY) we have lot quality problems, test escapes, etc. that all manufacturers occasionally have when something doesn't go right in the test group. Of course, each time that happens, it is cause for reviews of quality and proceedures so we never make that mistake again! So to all of you who think you might have a lot quality problem, again, that is so rare that I only mention it here to be accurate and honest. Often mentioning something in the news group is like describing a new rare illness to a hypochondriac, suddenly everyone thinks they are sick with the new rare disease! (In which case it isn't rare anymore....) AustinArticle: 79638
Ali, two ports of DPRAM block memory are completely independent, so the only thing you have to worry about is meeting the timing, in case the ports operate at a different clock edges. Regards, Vladislav "Ali Dixon" <ali@cs.bris.ac.uk> wrote in message news:ee8c0f8.-1@webx.sUN8CHnE... > I'm trying to build a simple core in which decode and register file access occurs in the same cycle on a virtex II pro board. > > Decode completes in the half clock cycle after the positive edge. Any ideas about how to make a dual ported RAM which operates in the half cycle after the negative edge? > > Thanks in advanceArticle: 79639
It seems that the SD/MMC cards get popular for FPGA designs today. These cards are real consumer products and are in effect cheaper than bare NAND chips (for low/medium volume). I would like to summarize the facts I've found in c.a.f [1] and on various web sites. SD Cards are now considered for configuration of an FPGA. One of the first projects, done by Antti, uses MMC and load the configuration stream with a small CPLD (21 cells) [2]. Another FPGA loader was done by Arnim Laeuger for a SD card and takes about 50 cells in an EPM3064 [3]. Ad Anuff has used an Atmel ATTiny12 for this task [4]. The design (asm program, eagle library, schmatic) is available at [5]. However, what's the big win when configuring the FPGA from the SD Card? Cost saving? You need an additional part (CPLD w 64 cells) or an ATTiny12. Both are around $2. That's the same price as for a serial Flash. Flexibility? You need a SD slot on your PC to write the configuration file onto the card. I think SD Cards are a very fine addition for an FPGA with a soft-core processor to be used as file system. Than it's better to connect the card direct with the 4-bit interface to the FPAG. If you use it also for configuration all above approaches use the SD Card in SPI mode. That maens 1/4 of the available bandwith. And AFAIK you cannot swith to the SD bus mode without powering off the card. And for a file system it can make a difference if your transfer rate is 12MB/s or only 3MB/s [6]. Martin [1] http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/80f39633c74b22e2 http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/7669de518b0c9bab http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/fbd9392981fc2855 [2] http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview [3] http://www.opencores.org/projects.cgi/web/spi_boot/overview [4] http://groups.yahoo.com/group/java-processor/message/110 [5] http://groups.yahoo.com/group/java-processor/files/sd_card_fpga_interface/ [6] http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdfArticle: 79640
Hello everybody, i'm building up a system where i need to use a
Microblaze uP with a RTOS, and my option was the XilKernel that comes
with Xilinx EDK.
I'm using a Spartan3 starter board to test my system.
After reading the Xilinx documentation on XilKernel, and also after
looking to some implementation examples i started to come my embbed
program.
I'm building a simple test program with an Uart ISR to recieve some
messages, validate them in one task and send them back in another
task.
I've made all the Xilkernel configurations (just like in the working
examples i've been looking to), OS defenition, OS configuration,
Complier configuration (-lxilkernel), and i also included the xmk.h
header file.
But i allways get the same compile error:
TELEC/Master.C: In function `int
main()':
TELEC/Master.C:72: implicit declaration of function `int
xilkernel_main(...)'
make: *** [telec/executable.elf] Error
1
this is when in the main routine i call the xilkernel_main() function,
and my main task is just like it follows:
[code:1:9b095c3f06]
int main(){
xilkernel_main();
return 0;
}[/code:1:9b095c3f06]
Hope someone can give me some hints.
Thanks in advance
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Article: 79641> Is it possible to use a tristate VHDL description in a hierarchical design > that is in a sub module or do I have to use it only on the top level > description You can use it in any module. Just declare your signals inout. You can even use tri-state busses internal to avoid coding the MUXs. The synthesizers are smart enough to substitute the tri-state busses by MUXs. I've used this to define in one module which IO components are integrated for the processor only by component declarations. > > WHEN using QuartusII version 4.2 ? Yes Quartus does fine. It has (or had) only a problem when you assigne the 'Z' value inside a clocked process. Better do it outside of a process with a concurrent statement. MartinArticle: 79642
Andrés wrote: > I have been reading some threads on TRISTATE STUFF on this forum and yet > I am not sure about the following question: > Is it possible to use a tristate VHDL description in a hierarchical > design that is in a sub module or do I have to use it only on the top > level description > WHEN using QuartusII version 4.2 ? It is at least possible to do in verilog with QII. What I haven't figured out how to do is connect two inout lines together without a module in between. I can rename an ordinary signal with an assign, but not an inout line. The verilog tran gate won't synthesize. -- glenArticle: 79643
John_H wrote: > Gaussian jitter is a statistical number. If the peak-to-peak is specified > at 6-sigma (which it often is) the probability is 0.00034% that either > jitter value is at its peak. The probability that *both* values are at > their peaks is below 0.000000000012% Hmm. That's every five minutes for a 400MHz clock? So if I use this for my timing budget the chip might fail every five minutes? Kolja SulimmaArticle: 79644
AL wrote: > When I put a constant number into the register and read it > back, it works, but when I have that number changed depending > on an if else statement, it doesn't work anymore. > For example, in the following code: > always @(posedge CLK_IN) begin if(RESET) begin > num = 20+1; > end > else begin > num = 1+1; > end > It would give me 00010011 or 21 even though the > RESET signal has changed. This is a synchronous reset, which says to set num to 21 if RESET is high on a rising edge of CLK_IN. If RESET is low on a rising edge it sets num to 2. In logic terms, RESET is the enable for a FF, and CLK_IN is the clock. (Also, RESET is usually used to describe setting to zero.) -- glenArticle: 79645
tom wrote: > BTW the fpga editor looks promising - even I can understand it at some level. May I suggest that you do not use the FPGA editor to build your whole design. Create some building blocks (datapath components) and hook them up via HDL and place them with the floorplanner. In this case you usually can trust the tools to map any external control logic with less then four inputs into a single LUT and automated placement of a few LUTs between hand placed macros shouldn't be too bad either. Kolja SulimmaArticle: 79646
Martin Schoeberl wrote: > It seems that the SD/MMC cards get popular for FPGA designs > today. These cards are real consumer products and are in effect > cheaper than bare NAND chips (for low/medium volume). > I would like to summarize the facts I've found in c.a.f [1] and on > various web sites. > > SD Cards are now considered for configuration of an FPGA. > One of the first projects, done by Antti, uses MMC and load > the configuration stream with a small CPLD (21 cells) [2]. > Another FPGA loader was done by Arnim Laeuger for a SD > card and takes about 50 cells in an EPM3064 [3]. > Ad Anuff has used an Atmel ATTiny12 for this task [4]. The > design (asm program, eagle library, schmatic) is available at [5]. > > However, what's the big win when configuring the FPGA from > the SD Card? > Cost saving? You need an additional part (CPLD w 64 cells) or > an ATTiny12. Both are around $2. That's the same price as for > a serial Flash. > Flexibility? You need a SD slot on your PC to write the configuration > file onto the card. > > I think SD Cards are a very fine addition for an FPGA with a soft-core > processor to be used as file system. Than it's better to connect the > card direct with the 4-bit interface to the FPAG. > If you use it also for configuration all above approaches use the > SD Card in SPI mode. That maens 1/4 of the available bandwith. > And AFAIK you cannot swith to the SD bus mode without powering > off the card. And for a file system it can make a difference if your > transfer rate is 12MB/s or only 3MB/s [6]. So perhaps the PLD, or 8-14 pin uC, could perform this power removal ? Next generation FPGAs could include native boot in 4 bit mode option ? Is there a random access cost-hit in the 4 bit mode ? -jgArticle: 79647
Stephen Williams wrote: > > Unfortunately, our engineer did exactly that: a DCM (used to be a > chain of DCMs) multiplies a PCI 33MHz clock up to 100MHz and sends > it off the chip. The return 100MHz clock is connected to another > DCM which is used as an internal 100MHz clock phased with the SDRAMS. > Another thing to watch out for in certain cascaded and external DCM constructs, where absolute delay from input_dcm_1 to output_dcm_2 is important, is the intentionally early ( ~1.5ns in V2 ) DCM output clock arrival time when using the default SYSTEM_SYNCHRONOUS mode of the DCM. DCM in->out delays were modeled oddly in older versions of the SW, but I haven't checked how 6.3 handles it- see the Answer Records listed at the bottom of this old post: http://groups-beta.google.com/group/comp.arch.fpga/msg/7f691bfe47996336 BrianArticle: 79648
Hi 1) how could I have the worst delay path in xilinx ise in a design? Because if i put a timing constraint it give me the worst paths if the constraints is not reach but if the constraint have been met we haven't the worth path. 2) When can we say that we have reached the max frequency possible for the design? In my mind it 's for when we made an IP with no timing constraint when can we say that we are fast enought?? Relative to time due to logic and route , when we have more time due to route than logic or something else?? 3) Is it possible to put a part of the a design out of timing analyze? because a part of my design is only here for simulation (it generates stimuli when onboard) and the worst delay path is due to this part. Or should I analyze each part of my design separately without the test part?? Thanks for your answers Regards AlexisArticle: 79649
Kolja, Exactly. Often folks do not realize that 12, or even 14 sigma is required if you wish to be 'error free'. The great news is that the difference between real jitter in physical systems, and a theoretical gaussian distribution is that in the real world, we do not have infinite energy. Real world systems begin to have real physical limits that prevent you from having to worry about 14 sigma cases. But, you should worry out to 12 sigma (or be able to tolerate occasional errors). Often you hear people say that "jitter is unbounded" which is not exactly true. What is true is that the longer you measure, the more jitter you get - up to a point (the peak to peak grows increasingly slowly as the number of samples increases, so at some point, it isn't worth the time to wait, as you will only get 10 more ps p-p by waiting another day!). "Tail fitting" fits the tails of a gaussian curve (right and left) to the measured histogram, which is useful for not waiting around forever, and getting your 12 to 14 sigma results. Or you can add another 10% after 2 million samples, and be very very close to the "right" answer (and a little conservative). We only measure jitter in this way (tail fitting), because all other methods have the problem that you detailed in your posting: don't you have to sample (wait) longer to know the 'truth'? The other point is that in digital systems, it is not the positive excursion (the lowest or longest period) that gets you in trouble, it is the shortes (or fastest). Take the peak to peak jitter, divide it by two, and take that away from the clock period to find your worst case min clock period. That is the constraint you need to have slack for, not the clock period itself. http://tinyurl.com/3jfq6 Austin Kolja Sulimma wrote: > John_H wrote: > >> Gaussian jitter is a statistical number. If the peak-to-peak is >> specified >> at 6-sigma (which it often is) the probability is 0.00034% that either >> jitter value is at its peak. The probability that *both* values are at >> their peaks is below 0.000000000012% > > Hmm. That's every five minutes for a 400MHz clock? > So if I use this for my timing budget the chip might fail every five > minutes? > > Kolja Sulimma
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