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Hello Antti. Thanks for your reply. Antti Lukats wrote: > Hi > first many congratulations for th s430, I assume it yours ? Yes, the beast is mine. It was just a small hobby project I started working on many months ago to fight boredom and it was victim of the snowball effect. I am afraid I have actually grown very dependent of my own creation. ;) Although the MSP430 is not an ideal architecture for FPGAs, the core size and code density is very good, and I am able to use the GCC toolchain seamlessly with it. Really, I have been able to do wonderful things with just 2 BlockRAMs. And when I ported it to Spartan-3 I got a multiplier peripheral almost for free, so the floating point routines now run very happily ever after. :) I have now a pipelined version that allows faster clocking. Sadly I don't have very much spare time left in order to verify and write-back the changes to the CVS faster. > yes I am afraid you are about right - the S3 partial reconfig - > my guess is nobody is using it, it could be useable but the > effort to get it done could be too high to be reasonable. > > it could, OTOH maybe you just about to get it working > the way you are trying. But dont expect much help, > its nomans land where you are walking! > ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig. > (maybe thats outdated info, but I had/have that impression) Hmmm... I am very sorry to realize this. It would be nice to hear from someone who has actually used the reconfiguration capabilities of the device. Maybe it is *not* reconfigurable at all and I am just wasting my time! :S I will keep trying, as you say. But I am afraid that, if I eventually get this to work, I will have to battle with the design every time I change the filter parameters or generate a new filter. The front effort was going to be worth only if the filter management was streamline after that... Thanks again. Best regards. -- /"If you would not be forgotten PabloBleyerKocik / As soon as you are dead and rotten, pbleyer / Either write things worth reading, @embedded.cl / Or do things worth writing."- Benjamin FranklinArticle: 79726
On Wed, 23 Feb 2005 10:51:01 -0800, Austin Lesea <austin@xilinx.com> wrote: >See: > >http://biz.yahoo.com/prnews/050223/sfw032_1.html > >Austin Hi Austin, I am a mainly X based consultant and I'd like to say that this is getting ridiculous. Why don't you leave the PRs at PRNEWS and keep the relatively high SNR of this group where it's at ? The technical tit for tat between you and Paul@A is nice but just copying the PRs here is not necessary IMO.Article: 79727
Andres,
I am not an Altera guy, but i think that the safe reset implies that the
very first flip-flop in a chain has to be reset
to a certain default value, not to the value generated by the internal
logic.
Imagine that you have a state machine implemented with a certain encoding
for each state.
If the reset is applied asynchronously, then your state register shall be
resetted, but some of the flipflops can start "moving" before others are get
out of reset. Consequently, your state machine could get into an undesirable
state.
So, Altera design assistant advises you to have something like this (hope
the code is right, I am not VHDL guy as well):
process (clk,Areset_n)
begin
if (Areset_n)
Areset_n_d <= "0";
Areset_n_sync <= "0";
elsif rising_edge(clk)
Areset_n_d <= "1";
Areset_n_sync <= Areset_n_d;
end if
end
Hope this helps.
Vladislav
"Andrés" <nospam_nussspucke@gmx.de> wrote in message
news:3831l0F5icp4hU1@individual.net...
> Hi FPGA people,
>
> I am using the VHDL module showed
> to synchronize my external asynchronous reset into my FPGA.
> When the external asynchronous reset gets inactive
> the flip flop chain makes sure that Reset_sync is
> deactivated synchronously.
>
> The QuartusII (version 4.2) DESIGN ASSISTANT shows the following
> MEDIUM warning after synthesis:
>
> >External reset ARESET_N should be synchronized using two cascaded
> >registers
>
> My question: Why should I synchronize the Areset_n to feed
> the Aset port of the flip flops ? If I did so
> there would arise the problem that the output of the flip flop chain
> (Reset_sync) would become uncertain when the PLL is not locked.
>
> Should I let is that way or should I trust the recommendation
> of the DESIGN ASSISTANT tool ?
>
> What is your opinion ?
>
>
> LIBRARY ieee;
>
> USE ieee.std_logic_1164.ALL;
>
> ENTITY safe_reset IS
> PORT ( Clk : IN STD_LOGIC;
> Areset_n : IN STD_LOGIC;
> PLL_locked : IN STD_LOGIC;
> Reset_sync : OUT STD_LOGIC
> );
> END safe_reset;
>
>
> ARCHITECTURE rtl OF safe_reset IS
>
> COMPONENT reset_flipflop
> PORT ( Clock : IN STD_LOGIC;
> Aset : IN STD_LOGIC;
> Data : IN STD_LOGIC;
> Q : OUT STD_LOGIC
> );
> END COMPONENT;
>
> SIGNAL l_q1 : STD_LOGIC;
> SIGNAL l_q2 : STD_LOGIC;
> SIGNAL l_q3 : STD_LOGIC;
> SIGNAL l_q4 : STD_LOGIC;
>
> SIGNAL l_ena_shift : STD_LOGIC;
>
> SIGNAL l_areset : STD_LOGIC;
>
> BEGIN
>
> Reset_sync <= l_q4;
> l_ena_shift <= not ('0' xor Pll_locked);
> l_areset <= not Areset_n;
>
>
> i1 : reset_flipflop
> PORT MAP ( Clock => Clk,
> Aset => l_areset,,
> Data => l_ena_shift,
> Q => l_q1
> );
> i2 : reset_flipflop
> PORT MAP ( Clock => Clk,
> Aset => l_areset,
> Data => l_q1,
> Q => l_q2
> );
> i3 : reset_flipflop
> PORT MAP ( Clock => Clk,
> Aset => l_areset,
> Data => l_q2,
> Q => l_q3
> );
> i4 : reset_flipflop
> PORT MAP ( Clock => Clk,
> Aset => l_areset,
> Data => l_q3,
> Q => l_q4
> );
>
> END rtl;
Article: 79728Hello Falk. Thanks for answering. Falk Brunner wrote: > There are many ways to skin a cat. Different filters can also be realized by > keeping the processing structure (MACs, delays etc.) but just reloading > filter coefficients, which can be done using BRAM, SRL16, SelectRAM. I am already doing this for some kind of filters when it is possible to do so. For example, my delays always have maximum taps and I control bypass writing to a memory-mapped register with the MCU. Then I get only the taps I need. The problem is that there are many audio processing structures that are very, very different. I even have a morph engine that stores an evolvent in *big* distributed RAM (takes almost all of the available slices of the FPGA), in order to convolve it with an incoming signal. The only way I can do this is to re-use most of the FPGA area available. > Or go for a complete hazzle free approach, reconfigure the whole FPGA and > keep an (complete) FPGA image for every different filter in FLASH memory > (its cheap) That was my first approach, but then I will need an external controller which is what I am trying to avoid, since I already need and have the MCU inside... Thank you for your suggestions. Regards. -- PabloBleyerKocik /"Artificial Intelligence: the art of making pbleyer / computers that behave like the ones in movies." @embedded.cl / -- Bill BulkoArticle: 79729
Hi just a few FPGA related news Actel ProAsic PA3 Engineering samples PA3 250 (not 600E !!) will be available Q3 NO WAY to get any engineering silicon before that. Q3 may be the last day of Q3 so Q4 end of year seems as more realistic. production volumes few weeks later ? PA4 (PA3+) - even as it was on the roadmap more than years ago the roadmap is no less clear than before, eg no fixed plans at all Altera Was there! This time there really was Altera directly and not some rep pretending to be Altera. I got a look at the Cyclone Cubicum and did see what I expected to see, halfway hidden was the FTDI chips that is used in Altera USB Blaster. I am 99% sure thats FT245BM so making DIY Altera USB Blaster cable should only a matter of writing the VID/PID to the EEPROM and connecting JTAG to the FT245 ok, maybe a litte more at EBV stand there was PCIexpress board with Altera GX on it, but when I wanted to know is it available for purchases then the answer was YES! After asking second time another guy did check it out for me and then it was not so much YES any more, there was no answer it will be inquired, etc... most likely not available. There was also a real nice Altera Cyclone 2 board with 3 USB host and 1 USB device connectors and lots of other things price EUR 249 should be available already Lattice was there in a tinybooth. but nevertheless was interesting - one thing new to me was the Block RAM in 5000M PLDs so far I have never paid attention to that. the "xp" thing, well all unofficial, the best info I was able to squeeze was that a press announcement about it is expected in less than 2 months and that the xp is basically EC/ECP with added Flash on chip, there should be possible to indirect self reprogramming by connecting the JTAG pins externally back to the FPGA fabric. ------- overall: lots of embedded linux stuff, pretty nice is linux inside RJ45 jack (price 99EUR) Philips: as second manufacturer has 3by3 mil 10 pin MLP packaged microcontroller (SiLabs was first long time ago) Ti PTH04070w: 3A SMPS module 11 by 14 mm, pretty nice for FPGA VCCINT AnttiArticle: 79730
Falk Brunner wrote: > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag >>EasyPath can also be reconfigured: IO, LUTs, DCMs, global resources are >>100% tested on every part. So if you are clever, you could change your >>design by changing those items that are 100% tested (like the LUT). We >>call this the ECO feature. You may at some time in the future change >>those 100% tested items, and be guaranteed that they will function (with >>no test program changes, and no added cost to you). > > > So far so good. But how is it handled by the software, especially P&R?? OK, > I could write tons of LOCs to lock out the not tested logic. But what about > routing? If the LUTs are 100% tested, and the config RAM must be 100% tested, then a designer could deploy their own (thorough) Power On Test, to verify full operation, should they have a more radical ECO. More than one P&R iteration could be available, to decrease the chance of a failure.... -jgArticle: 79731
Hi
I want to make my design generic but I got a problem
I have a kinf of counter and i want it generic in fonction of the reset
value of the counter
ex:
signal cpt : std_logic_vector(A downto 0);
if ( unsigned(cpt) = B) then
cpt <= (others =>'0');
else
cpt <= std_logic_vector(unsigned(cpt))+1;
end if;
I want to know if we can make a relationship between A and B because
A= ceil(log2(B));
And i want to only declare B as generic and calculate A. Is it possible or
should I declare 2 generic A and B ???
thanks
Alexis
Article: 79732mk wrote: > Hi Austin, > I am a mainly X based consultant and I'd like to say that this is > getting ridiculous. Why don't you leave the PRs at PRNEWS and keep the > relatively high SNR of this group where it's at ? The technical tit > for tat between you and Paul@A is nice but just copying the PRs here > is not necessary IMO. Since love is one step from hate (or that is what they say), I vote for ourselves to set up a fund to buy them one of those Love Cruise tours to the Caribbean. At least we will have peace for around two weeks here, and I bet they will have set all their differences down one way or another when they come back :D Just an idea... Maybe somebody has a better one ;) PabloBleyerKocik /"Ashes to ashes, funk to funky, we know Major Tom's a junky pbleyer / strung out on heaven's high, hitting an all time low." @embedded.cl / -- Ashes to ashes, David BowieArticle: 79733
I don't know if you are still looking for IP to write text but I have finish the pre-version of my VGA display , it takes input smbole code save it into a rom that save all the caracter code to display on the screen and then adress the rom with the font the actual configuration is: 640*480 pixels screen 8*8 pixel caracter (so the screen could display 80*60symbols) 25MHz/pixel actually not all the font is integrated (only A->Z) http://kclo4.free.fr/FPGA/vga.zip here is you could find the *.vhd files the top integrate the display function called afficheur_vga and dummy for test (DCM for dividing frequency and others stuff ) the constraint file is for spartan 3 digilent board if you want to test the design just P&R and program your board =>reset is the last slide switch =>the 3 first slide switch are for color of screen =>the push button are for the are respectevely a, b, c , enter (1sec refresh frequency, could be change by changing the test value of cpt in top.vhd) The design is not yet finish because I have to change some little thing as complet the font, make generic all I can and make a documentation. Regards Alexis "Marco" <marcotoschi@email.it> a écrit dans le message de news: ee8bfb0.-1@webx.sUN8CHnE... >I should interface the my SoC with an HITACHI SP14Q005 display, 320x240 >pixel. > > There is someone who could tell me what to do to write text on display?Article: 79734
While your business is probably important to them, they probably prioritize request based on the number of similar requests. Their ability to solve a request is based on if you included enough information. And have you made yourself available if an engineer has tried to get in touch with you? The other route you could try is post a description of problem to this news group. You might not be the only person who has run into this problem and maybe someone else has found a solution they are willing to share or they could explain why you are have this problem. DerekArticle: 79735
Derek, They definitely have enough info, as I have archived my project which produces the error. I wish an engineer would try to contact me. I have posted multiple updates to the open issue without a response. As for posting the problem here, unfortunately I can't do that b/c it would reveal confidential details. I can really only search the group for similar posts. To be honest, I was hoping some Altera folks were trolling around this board, and would help me out. I know on several occasion with Xilinx, I've gotten immediate support after posting here. JohnArticle: 79736
> Timing Analyzer is your friend. Tell him to check against tighter > constraints, and it will show you the failing paths. > Yes I found it, I use verbose report and that allright >> 2) When can we say that we have reached the max frequency possible for >> the >> design? In my mind it 's for when we made an IP with no timing constraint >> when can we say that we are fast enought?? Relative to time due to logic > and >> route , when we have more time due to route than logic or something >> else?? > > Again, timing analyzer is your friend. It will tell you exactly how much > time is spent in logic and routing. But what I wanted to know it is in the cese of making an IP(take DSP IP for example) when can we say that all effort we will do will be useless to get a better frequency??that we reach the max frequency possible?? Is there a criteria?? like being at 80% of the max frequence limit of the device or having worst path with only 2 or 3 level logic??? >> 3) Is it possible to put a part of the a design out of timing analyze? >> because a part of my design is only here for simulation (it generates >> stimuli when onboard) and the worst delay path is due to this part. Or >> should I analyze each part of my design separately without the test >> part?? > > Yes, you can exclude paths/parts from timing analyze. But why? At the start I added some stuff to make input for my design: a 25 bits counter to slown down refresh frequency of the push button and that was this counter that was the worth path so I finnaly decided to delete it from my design and make a top that include my design as component and this counter. All this are in fact only for educative , this project permit to me to discover a lot of tip about foundation and making design running faster Regards AlexisArticle: 79737
"KCL" <kclo4_NO_SPAM_@free.fr> schrieb im Newsbeitrag news:421cf072$0$11683$8fcfb975@news.wanadoo.fr... > But what I wanted to know it is in the cese of making an IP(take DSP IP for > example) when can we say that all effort we will do will be useless to get > a better frequency??that we reach the max frequency possible?? Is there a > criteria?? like being at 80% of the max frequence limit of the device or > having worst path with only 2 or 3 level logic??? To answer this question, you need experience. Then you know the critical points of a design and the target technology. Lets say for Xilinx the BRAMs are slowr than FlipFlops. SRL16 is also slower than normal FlipFlops. Similar things apply to other devices from other vendors. Routing is also a issue. Regards FalkArticle: 79738
"mk" <kal*@dspia.*comdelete> schrieb im Newsbeitrag news:06op11h2niaos6hjvmchgn4bqbe55ko48s@4ax.com... > Hi Austin, > I am a mainly X based consultant and I'd like to say that this is > getting ridiculous. Why don't you leave the PRs at PRNEWS and keep the > relatively high SNR of this group where it's at ? The technical tit > for tat between you and Paul@A is nice but just copying the PRs here > is not necessary IMO. ACK. Regards FalkArticle: 79739
"statepenn99" <statepenn99@yahoo.com> schrieb im Newsbeitrag news:1109192804.160650.269880@z14g2000cwz.googlegroups.com... > Derek, > > They definitely have enough info, as I have archived my project which > produces the error. I wish an engineer would try to contact me. I > have posted multiple updates to the open issue without a response. As > for posting the problem here, unfortunately I can't do that b/c it > would reveal confidential details. I can really only search the group > for similar posts. To be honest, I was hoping some Altera folks were > trolling around this board, and would help me out. I know on several > occasion with Xilinx, I've gotten immediate support after posting here. > > John > If your problem is serious and you have tried and not getting response then play it as hard you can, like if your customer is some big company then send email to Altera (not tech support but somewhere higher) and include cc: to some important person from your client, well it all depends, that is not always an option. I had todo that once when Atmel did not deliver for mass production for a big mobile company, the result was that for long time I got CC: with fedex tracking numbers whenever Atmel shipped the initial order piece by piece. Atmel is not Altera, but I tend to belive that occosianally both are hard to deal with. Raally, try to escalate the issue, that works with Xilinx, actually they in most cases escalate it even for you, if there problem is real. And Altera is "around" and lurking here as well, so they will catch up... AnttiArticle: 79740
Hi, I want to buy a development kit that has a strong processor and also DSP. I've found "DSP Development kit, Stratix II edition" from Altera and "ML401 evaluation platform" from Xilinx. Does anyone have experience in using them? if so which one is more reliable? Thanks a lot.Article: 79741
It seem that xilinx's guy doesn't like altera' guy During my internship in an huge french Defence electronic firm (for not telling the name but there is not a lot), I participated at a conf. on FPGA during which engineer from different project talk about their way of desing and things like that. And there were 2 guy (definitively pro Xilinx) that was always nearly insulting others engineers that use Altera for their project saying that Altera's device were not real FPGA... I was a little bit astonished by this attitude because I was thinking that engineer were open minded people and I discover that not. And as conclusion in the fight, I will just add my personnal (and little) experience from experienced a FAE from Xilinx and another from ALTERA well Altera listen to you , when you report a bug he don't forward you to the online website (that is forbidden for student like me : so student couldn't detect a bug ??) so my experience is more friendly with Altera than Xilinx (even if I use Spartan3 board) Regards Alexis "Pablo Bleyer Kocik" <pablobleyer@hotmail.com> a écrit dans le message de news: 1109190323.740422.284290@o13g2000cwo.googlegroups.com... > mk wrote: >> Hi Austin, >> I am a mainly X based consultant and I'd like to say that this is >> getting ridiculous. Why don't you leave the PRs at PRNEWS and keep > the >> relatively high SNR of this group where it's at ? The technical tit >> for tat between you and Paul@A is nice but just copying the PRs here >> is not necessary IMO. > > Since love is one step from hate (or that is what they say), I vote > for ourselves to set up a fund to buy them one of those Love Cruise > tours to the Caribbean. At least we will have peace for around two > weeks here, and I bet they will have set all their differences down > one way or another when they come back :D > > Just an idea... Maybe somebody has a better one ;) > > PabloBleyerKocik /"Ashes to ashes, funk to funky, we know Major Tom's a > junky > pbleyer / strung out on heaven's high, hitting an all time > low." > @embedded.cl / -- Ashes to ashes, David Bowie >Article: 79742
Yaju N wrote: > Apart from the current requirements, it seems that I have to worry > about the real estate for heat sinking. > The new TI TPS75003 seems to be good device, but it basically consists > of a linear regulator and not a switching one as I had thought. > > I guess I will have to compromise on the real estate for heat sinking. > Maybe I will include a "finned" heat sink. > > The search for the best voltage regulator continues..... I found a new company that is making a very advanced surface mount regulator module. They have combined everything onto the chip except for the capacitors and run it at 5 MHz. This includes the *inductor*! The module is only 0.5" x 0.32" and can provide up to 3 Amps. www.enpirion.com I just took another look at the web site and they now also have 1 Amp and 6 Amp versions. The 6 Amp version is only 0.67" x 0.32"! Rick Collins rick.collins@XYarius.com Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave. 301-682-7772 Voice Frederick, MD 21701-3110 GNU tools for the ARM http://www.gnuarm.comArticle: 79743
Hi all Does anyone know what is the cheapest 3.3V CPLD available? My desing uses 31 macrocells, and 33 I/O. Currently using Xilinx XC9536XL available for around US$0.70 a piece (for 100k quantities). The design is pretty slow GCK~2MHz. I need 100k+ quantities. Thanks ZKArticle: 79744
Pablo Bleyer Kocik wrote: > Hello Antti. Thanks for your reply. > > Antti Lukats wrote: > >>Hi >>first many congratulations for th s430, I assume it yours ? > > > Yes, the beast is mine. It was just a small hobby project I started > working on many months ago to fight boredom and it was victim of the > snowball effect. I am afraid I have actually grown very dependent of my > own creation. ;) Although the MSP430 is not an ideal architecture for > FPGAs, the core size and code density is very good, and I am able to > use the GCC toolchain seamlessly with it. Really, I have been able to > do wonderful things with just 2 BlockRAMs. And when I ported it to > Spartan-3 I got a multiplier peripheral almost for free, so the > floating point routines now run very happily ever after. :) > > I have now a pipelined version that allows faster clocking. Sadly I > don't have very much spare time left in order to verify and write-back > the changes to the CVS faster. > > >>yes I am afraid you are about right - the S3 partial reconfig - >>my guess is nobody is using it, it could be useable but the >>effort to get it done could be too high to be reasonable. >> >>it could, OTOH maybe you just about to get it working >>the way you are trying. But dont expect much help, >>its nomans land where you are walking! >>ASFAIK Xilinx (Spartan group!) has interest in S3 partial reconfig. >>(maybe thats outdated info, but I had/have that impression) > > > Hmmm... I am very sorry to realize this. It would be nice to hear from > someone who has actually used the reconfiguration capabilities of the > device. Maybe it is *not* reconfigurable at all and I am just wasting > my time! :S > > I will keep trying, as you say. But I am afraid that, if I eventually > get this to work, I will have to battle with the design every time I > change the filter parameters or generate a new filter. The front effort > was going to be worth only if the filter management was streamline > after that... > > Thanks again. Best regards. I have had email exchanges with a person at Xilinx about this. None of the Spartan chips are currently supported, but I have been told that Xilinx is "committed" to providing partial-reconfiguration for the Spartan 3 chips (this was over a year ago, so I'm not sure what "committed" really means ;). There are two problems with getting PR working in the Spartan 3. The first issue is the fact that PR has used tristate buffers to connect to long lines to provide the intermodule connections. This has worked in the Virtex family. However the V4 chips also have no tristate buffers. So Xilinx is working on that problem and I expect their solution will be portable to the S3 parts. But the second problem is the lack of interest in S3 PR in the customer base. I am surprised at this since it can make the difference between a $10 FPGA and a $20 FPGA and/or a $5 flash memory and a $10 flash memory. I believe you are looking to use PR the same way I want to. You don't need to do it on the fly with the rest of the chip running, you just need to download modules in different combinations to provide the final download that suits the current need. But I may be mistaken here. If you don't have an external processor to load the FPGA, were you planning to use the internal proc to do that? I may be mistaken, but I think there is a special block in the FPGA to allow internal logic to load a new design (I forget the name, it may be IMAP). I seem to recall that the Spartan 3 does not have this block so PR must be controlled from the outside. There are some limitations to loading the partial configuration while the rest of the chip is alive. It may be that you just plain can't do it, or it may just be that the chip does not allow blocks adjacent to the partial load to be active. There are also limitations in that an S3 PR block must use full columns while the Virtex chips (or maybe just V4) can load partial columns. I do recall that the S3 is much more limited in the way it can do PR than the Virtex parts. Rick Collins rick.collins@XYarius.com Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave. 301-682-7772 Voice Frederick, MD 21701-3110 GNU tools for the ARM http://www.gnuarm.comArticle: 79745
Austin, Does V4 incorporate any new packaging technology wrt SI over and above previous packages? Did Dr. Johnson help Xilinx design the V4 packages? Looking at the pinout of the balls on some of the packages for V4, it appears that Xilinx hasn't made it easy to layout the PCB. The FF668 package for the LX parts looks good, but the FF672 for the FX parts is a real dog's breakfast. There are Vccint, Vccaux, Vcco and GND balls all over the place. What's going on? Sometimes I wonder if the guys who design these package pinouts actually get to use them in a real system. Making the package perform well is only half the job. The performance depends on how well you can connect it to a PCB. Cheers, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:cvij7d$8v42@cliff.xsj.xilinx.com... > Check out: > > http://biz.yahoo.com/prnews/050223/sfw066_1.html > > AustinArticle: 79746
governer@gmail.com wrote: > Hi all > Does anyone know what is the cheapest 3.3V CPLD available? > My desing uses 31 macrocells, and 33 I/O. Currently using Xilinx > XC9536XL available for around US$0.70 a piece (for 100k quantities). > The design is pretty slow GCK~2MHz. I need 100k+ quantities. You definitely should be asking distribution on this, not a newsgroup. Distribution will work hard to get you good quotes and will compete against their competitors. But I will say that $0.70 is a pretty good price. Also, most CPLDs are in multiples of 16, so you may have to bump up to a 48 or 64 macrocell device which might not be competitive. I believe Lattice (or was it Actel) has some new parts coming out that are very price competitive, but they may all be larger than you want. Like I said, $0.70 might be hard to beat.Article: 79747
I understand you frustration. I was just trying to cover the obvious. When I get to where you are, I start calling anybody that I might have met or gotten a business card from. DerekArticle: 79748
Falk, You do not get to change routing. Only LUTs and other 100% tested structures. Austin Falk Brunner wrote: > "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag > news:cvib32$8v41@cliff.xsj.xilinx.com... > >>Digari, > > > >>EasyPath can also be reconfigured: IO, LUTs, DCMs, global resources are >>100% tested on every part. So if you are clever, you could change your >>design by changing those items that are 100% tested (like the LUT). We >>call this the ECO feature. You may at some time in the future change >>those 100% tested items, and be guaranteed that they will function (with >>no test program changes, and no added cost to you). > > > So far so good. But how is it handled by the software, especially P&R?? OK, > I could write tons of LOCs to lock out the not tested logic. But what about > routing? > > Regards > Falk > > >Article: 79749
Jim, We do not test 100% of the BRAM. We only test that which is used. Austin Jim Granville wrote: > Falk Brunner wrote: > >> "Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag >> >>> EasyPath can also be reconfigured: IO, LUTs, DCMs, global resources are >>> 100% tested on every part. So if you are clever, you could change your >>> design by changing those items that are 100% tested (like the LUT). We >>> call this the ECO feature. You may at some time in the future change >>> those 100% tested items, and be guaranteed that they will function (with >>> no test program changes, and no added cost to you). >> >> >> >> So far so good. But how is it handled by the software, especially >> P&R?? OK, >> I could write tons of LOCs to lock out the not tested logic. But what >> about >> routing? > > > If the LUTs are 100% tested, and the config RAM must be 100% tested, > then a designer could deploy their own (thorough) Power On Test, to > verify full operation, should they have a more radical ECO. > More than one P&R iteration could be available, to decrease the chance > of a failure.... > -jg >
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