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On Sun, 20 Feb 2005 11:40:58 +0100, Michel Billaud <billaud@labri.fr> wrote: >Hi, > >Some CS research papers propose the use of FPGA as PC co-processors >for very specialized hard computing task (like searching DNA sequences). > >It's easy to find starter kits in the $100-200 range to experiment with >FPGAs, but connecting them through the parallel port doesnt give a >supercomputer :-; and the price of PCI based cards seem to be 2 orders >of magnitude higher. Why is it so ? Is there no market niche for a >cheap (say $200-500) general purpose co-processor card ? These peope think there is ... http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253DUSA%2526SID%253D4746%2526DID%253DDF2%2526SRT%253D1%2526LID%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html and these people seem to think that's just too much money. http://www.fpga4fun.com/board_dragon.html - BrianArticle: 79501
On Fri, 18 Feb 2005 21:55:42 +0100, "IgI" <igorsath@hotmail.com> wrote: >Hi! > >I'm using Virtex-II (XC2V1000-FF896-4C) in one of the product which we have >been selling for over 3 years. Recently we got "new" batch of Virtex-II >chips and problems started to arise. >PCBs with chips from batch B and C are working fine, on the other hand none >of the 42 PCBs, where chips from batch A are used are working. >We are currently using ISE 5.2 SP3 for this design. I have verified the bit >stream by reading it back from the chip and it's ok. > > I >can't use ISE 6.1 or newer because the routing is not successful or ISE >simply doesn't meet the timing constraints (the chip is 99% full). Have you re-run timing analysis on the 5.3 design, but using the latest timing analyser and latest speed files? Sometimes the speed files are changed to reflect new information about the devices ... usually in the "right" direction. But if the old (formerly successful) design fails with new speed files, that might point you towards a solution. With 6.1, have you tried MPPR (multi-pass pacement and routing)? Sometimes modifying the placement (in FPGA editor) of failing paths and re-running "re-entrant routing" can fix problems, if there are only a small number of failing paths. - BrianArticle: 79502
"TonyF" <not@valid.address> schrieb im Newsbeitrag news:Wp%Rd.1219$%F6.1075@newsfe4-gui.ntli.net... > Just noticed that in your VHDL code you don't use inout ports, resulting > in 200% bloating of a normal inout port declaration. I presume this is > because XST is too lazy to parse inouts so that we have to do some kind Nonsense. XST can handle inouts quite good. Regards FalkArticle: 79503
There is a school of thought that all off chip IO should be inferred/instantiated at the top level, and not in sub-modules. "TonyF" <not@valid.address> wrote in message news:Wp%Rd.1219$%F6.1075@newsfe4-gui.ntli.net... > Antti Lukats wrote: > >> Hi all >> >> I re-found once again my own "Rules of Life" what I first published 21 >> aug >> 2001 >> >> 1 No Promises. >> 2 Keep Promises. >> 3 Give away what you do not need. >> 4 Do what you want to do. >> 5 Be Happy. >> >> In order to comply with Rules [5], [4] and specially [3] from the above >> list, I am giving a promise (those braking rule #1) that I will make all >> projects of my past live available as public domain. That includs all I >> can >> publish (ie all that IP that belongs to me and is not covered by 3rd >> party >> agreements), with the exception of maybe a few selected projects I am >> actually working on at the moment. >> >> In order to comply with [2] first project is made public today at: >> http://gforge.openchip.org >> >> there is OPB I2C IP-Core that uses the OpenCores I2C Core by implementing >> a >> OPB 2 Wishbone adapter. > > Just noticed that in your VHDL code you don't use inout ports, resulting > in 200% bloating of a normal inout port declaration. I presume this is > because XST is too lazy to parse inouts so that we have to do some kind of > backend annotation alongside HDL programming, resulting in a not very > elegant code. > > This is probably the price to pay for such a cheap tool, so I should not > really complain. Synplify will allow you to use inouts in sub modules, but > it costs much more than XST. > > TonyF > There is a school of thought that all off chip IO should be inferred/instantiated at the top level, and not in sub-modules. -NewmanArticle: 79504
Falk Brunner wrote: > "TonyF" <not@valid.address> schrieb im Newsbeitrag > news:Wp%Rd.1219$%F6.1075@newsfe4-gui.ntli.net... > > >>Just noticed that in your VHDL code you don't use inout ports, resulting >>in 200% bloating of a normal inout port declaration. I presume this is >>because XST is too lazy to parse inouts so that we have to do some kind > > > Nonsense. XST can handle inouts quite good. Only if they are at the top level. If they are in a sub-module, XST will complain about not finding the *_I, *_O and *_T ports in your sub-module (see my other post). TonyFArticle: 79505
newman5382 wrote: > There is a school of thought that all off chip IO should be > inferred/instantiated at the top level, and not in sub-modules. > In the end, everything is flattened and becomes top-level, but in your HDL code it is useful to have sub-modules for clarity, code maintenance and reusability. It should be obvious or possible to tell to a synthesis tool that your inout port in your sub-module really is an external port. TonyFArticle: 79506
Derek, thanks for the input, alas, I shall obviously have to acquire the finer points of teaching an exceedingly stupid apprentice (the HDL SW) how to do the job for me, when I could have done it myself in a fraction of the time. BTW, I got a Spartan-3 ev-kit. Cheers, Tom.Article: 79507
"TonyF" <not@valid.address> wrote in message news:rl1Sd.1774$%F6.772@newsfe4-gui.ntli.net... > newman5382 wrote: > >> There is a school of thought that all off chip IO should be >> inferred/instantiated at the top level, and not in sub-modules. >> > > In the end, everything is flattened and becomes top-level, but in your HDL > code it is useful to have sub-modules for clarity, code maintenance and > reusability. It should be obvious or possible to tell to a synthesis tool > that your inout port in your sub-module really is an external port. > > TonyF It is not my HDL code. Lots of things are judgement calls, and different people will choose differently. If I look at regular HDL (non-EDK) targeted code, if I see that all the primary I/O are defined in the top level, and not buried at some unknown level of the hierarchy, it gives me a warm fuzzy that the other person made some effort for other people to understand the flow of the design. As far as your complaint about the XST synthesys tool, since I own a bunch of Synplicity stock, I think it would be best for me to not address that issue. -NewmanArticle: 79508
thanks for note 1) integer count : usually i use std_logic for all my signal and use conversion function for arithmetic, so i have no problem of wrap around, 2) reset missing : does at startup all signal have a value unknow but equal to '1' or '0' so after max 16cycles cpt should back to 0 so there is a 16 cycle clock intial time that (depend of your application need but in most of DSP) is not important I think. Also for reset what is the best synchronous or asynchronous?? because synchronous reset seems to need less ressource?? 3)not a shift register but i think this not a real shift register he wanted :"parallel in serial out latching shift register" for me he asked for serializator (sorry my english is so bad so I translate as I can) if i wanted to do a shift register i will have done: data_reg <= data_reg(14 downto 0) & data_in; data_out <= data_reg(0); Finally I just will add that still people not explain very well what they wanted , we couldn't give them exactely what they want to do (and also that they could search by themself , it 's not not too bad for brain activity) And excuse me for my "errors" but I just notice that only a french guy with only 6month internship in VHDL developpement(and limited english comprehension) take time to answer to his problem. Regards Alexis "Christian Schneider" <please_reply_to_the@newsgroup.net> a écrit dans le message de news: cv9vne$3ua$1@online.de... > Well, there are some issues with this code example: > > 1) The reset is missing, this is a problem for the simulation > > 2) integer based counters tend to not wrap arount automatically, I do not > know for sure what synthesis might result, but simulation will fail > > 3) While the general behavior is ok with the above points corrected, this > is not a shift register. Sorry. See notes below. > > Try again! > Chris > > > KCL wrote: >> probably something like >> --------------------------------- >> signal cpt : integer range 0 to 15; --i'm not sure for this declaration > this is ok > >> usually i use only std_logic with convertion >> signal temp : std_logic_vector( 15 downto 0); >> >> process(clk) >> begin > > Missing reset here, initialize cpt here! > >> if rising_edge(clk) then >> cpt <= cpt +1 ; > This is a counter which does not wrap around, since it is of type integer! > Take care! > >> if cpt = 0 then >> temp <= in_parallel; >> end if; > Parallel loadable register. ok. > >> out_serie <= temp(cpt); > Multiplexer, with output register. NOT a shift register!! Where is the > shift?? > >> end if; >> end process; >> ---------------------------------------- >> >> >> there is many others way to do it you just have to test different >> solution to get the better and have imagination... >> >> alexis >> >> "bob" <kmart@nospam.com> a écrit dans le message de news: >> jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... >> >>>Shift register example? >>>Hi I am looking for a parallel in serial out latching shift register >>>in VHDL. >>>I want 16 bits but any example would be appreciated. >>> >>>Thanks >>> >> >>Article: 79509
Actually what i gived to you is like a state machine and the 2 MSB of the counter are the state of the machine "fpgawizz" <bhaskarstays@yahoo.com> a écrit dans le message de news: 57900d3bbffa517d7810a22c49caced3@localhost.talkaboutelectronicequipment.com... > Thanks KCL. I used a state machine to model that part of the design. Seems > like its working.ITs only a piece of a bigger part. I am trying to have > this display module be one of the modules for a VHDL vending machine. Do > you know any materials in the internet that can help me design this > vending machine. It has the following features: > 1) 5 products price - 55/60/65/70/75c > 2) 3 different coin inputs -25 c/10c/5c > 3) Need to display the product price and price entered via the 3 coin > inputs. > 4) When the value of product selected is reached, it should be dispensed > and any change displayed. > 5) System should reset after this and also reset if done asynchronously. > >Article: 79510
Tom, Initially, FPGA design was done in schematic form. In fact, schematic support is still available for development. (Some designs were done using our FPGA Editor initially -- extremely crude, and impossible to understand -- like having a wirewrap netlist as your only documentation). Why has it been all but abandoned? (Schematics are often still used at the top level of hierarchy, however by some designers) The complexity of the designs grew from being some glue logic, to being "super" glue logic, to being the whole system (or, perhaps more accurately, the heart of the system, and sometimes the heart, lungs, brains, and kidneys). When designs get to these large dimensions (million gate), a schematic is no longer an effective way to document the design, and allow it to be verified. 50 pages of schematic for the FPGA is just impossible to deal with. HDL initially started out as a means to verify the behavior of a digital system. It was soon adopted as a way to describe the system. A single language that allows for functional, and behavioral simulation, as well as creating test benches to verify the design, was just too powerful to ignore. All serious design is now done in either VHDL, or verilog, as these two languages have the necessary features to be effective tools for specifying, creating, verifying, and documenting digital systems. They have their faults, and there are some jobs that are poorly dealt with by HDLs, and there are plenty of extensions, improvements, and competitors out there working on this. Take the time to learn VHDL, or verilog. Or be relegated to the fringes. Austin Tom wrote: > A HW-designer's lament: I'm new to FPGA's, but not to HW design in general. Xilinx/Altera et al all characterize their FPGA's in terms of (very nice) HW features. Great, you buy an ev-kit, fire up the SW, only to discover that the SW, i.e, HDL, hides the HW from you. A design that could have been hand-wired in a matter of hours (using imaginary discrete chips having the function-blocks of the FPGA) now turns into an aggravated struggle against the SW (others have described it as pushing a rope, or searching for an incantation which will magically make the synthesis tool behave). Isn't there some way to do direct design instead of the tedious imposing of constraints upon an excruciatingly stupid piece of SW? Thoughts? Cheers, TomArticle: 79511
I made a mistake shift register is : > data_reg <= data_in & data_reg(14 downto 0) ; > data_out <= data_reg(0); "KCL" <kclo4_NO_SPAM_@free.fr> a écrit dans le message de news: 4218ad31$0$6618$8fcfb975@news.wanadoo.fr... > thanks for note > > > 1) integer count : usually i use std_logic for all my signal and use > conversion function for arithmetic, so i have no problem of wrap around, > > 2) reset missing : does at startup all signal have a value unknow but > equal to '1' or '0' so after max 16cycles cpt should back to 0 so there > is a 16 cycle clock intial time that (depend of your application need but > in most of DSP) is not important I think. > > Also for reset what is the best synchronous or asynchronous?? because > synchronous reset seems to need less ressource?? > > 3)not a shift register but i think this not a real shift register he > wanted :"parallel in serial out latching shift register" for me he asked > for serializator (sorry my english is so bad so I translate as I can) > if i wanted to do a shift register i will have done: > > > data_reg <= data_reg(14 downto 0) & data_in; > data_out <= data_reg(0); > > Finally I just will add that still people not explain very well what they > wanted , we couldn't give them exactely what they want to do (and also > that they could search by themself , it 's not not too bad for brain > activity) > And excuse me for my "errors" but I just notice that only a french guy > with only 6month internship in VHDL developpement(and limited english > comprehension) take time to answer to his problem. > > Regards > > Alexis > > "Christian Schneider" <please_reply_to_the@newsgroup.net> a écrit dans le > message de news: cv9vne$3ua$1@online.de... >> Well, there are some issues with this code example: >> >> 1) The reset is missing, this is a problem for the simulation >> >> 2) integer based counters tend to not wrap arount automatically, I do not >> know for sure what synthesis might result, but simulation will fail >> >> 3) While the general behavior is ok with the above points corrected, this >> is not a shift register. Sorry. See notes below. >> >> Try again! >> Chris >> >> >> KCL wrote: >>> probably something like >>> --------------------------------- >>> signal cpt : integer range 0 to 15; --i'm not sure for this declaration >> this is ok >> >>> usually i use only std_logic with convertion >>> signal temp : std_logic_vector( 15 downto 0); >>> >>> process(clk) >>> begin >> >> Missing reset here, initialize cpt here! >> >>> if rising_edge(clk) then >>> cpt <= cpt +1 ; >> This is a counter which does not wrap around, since it is of type >> integer! Take care! >> >>> if cpt = 0 then >>> temp <= in_parallel; >>> end if; >> Parallel loadable register. ok. >> >>> out_serie <= temp(cpt); >> Multiplexer, with output register. NOT a shift register!! Where is the >> shift?? >> >>> end if; >>> end process; >>> ---------------------------------------- >>> >>> >>> there is many others way to do it you just have to test different >>> solution to get the better and have imagination... >>> >>> alexis >>> >>> "bob" <kmart@nospam.com> a écrit dans le message de news: >>> jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... >>> >>>>Shift register example? >>>>Hi I am looking for a parallel in serial out latching shift register >>>>in VHDL. >>>>I want 16 bits but any example would be appreciated. >>>> >>>>Thanks >>>> >>> >>> >Article: 79512
newman5382 wrote: > It is not my HDL code. > > Lots of things are judgement calls, and different people will choose > differently. If I look at regular HDL (non-EDK) targeted code, if I see > that all the primary I/O are defined in the top level, and not buried at > some unknown level of the hierarchy, it gives me a warm fuzzy that the other > person made some effort for other people to understand the flow of the > design. The designer's HDL code should not target such low level. An inout is just that, an inout, not much to understand. In Xilinx FPGAs this will be inferred as an IOBUF that will provide the *_I, *_O and *_T ports. With other vendors or ASIC it might be inferred as something else (though equivalent). > As far as your complaint about the XST synthesys tool, since I own a bunch > of Synplicity stock, I think it would be best for me to not address that > issue. I did try my code with Synplify (outside EDK) and I didn't have this problem. Nevertheless I still think EDK/ISE is a nice tool for project management/implementation and great value for money. TonyFArticle: 79513
"newman5382" <newman5382@yahoo.com> wrote in message news:GP1Sd.96890$qB6.89122@tornado.tampabay.rr.com... > > "TonyF" <not@valid.address> wrote in message > news:rl1Sd.1774$%F6.772@newsfe4-gui.ntli.net... >> newman5382 wrote: >> >>> There is a school of thought that all off chip IO should be >>> inferred/instantiated at the top level, and not in sub-modules. >>> >> >> In the end, everything is flattened and becomes top-level, but in your >> HDL code it is useful to have sub-modules for clarity, code maintenance >> and reusability. It should be obvious or possible to tell to a synthesis >> tool that your inout port in your sub-module really is an external port. >> >> TonyF > > > It is not my HDL code. > > Lots of things are judgement calls, and different people will choose > differently. If I look at regular HDL (non-EDK) targeted code, if I see > that all the primary I/O are defined in the top level, and not buried at > some unknown level of the hierarchy, it gives me a warm fuzzy that the > other person made some effort for other people to understand the flow of > the design. > > As far as your complaint about the XST synthesys tool, since I own a bunch > of Synplicity stock, I think it would be best for me to not address that > issue. > > -Newman TonyF, I looked at the code section in question. It appeared to be two IO lines SDA, SCL that were broken out into input, output, and tristate control. I did an I2C design a while back, and I found it convenient to break out the signals in a similar manner. -NewmanArticle: 79514
I'm also interseted in it I'm writing an VGA display with incorporated ROM font , for test I just implemented part of font but in the future I will have to implemente all the font so knowing how to generate a file for the rom should be interesting.(I have already made a ROM for an altera component with dspbuilder but actually I doesn't know how to call a file in HDL and be recognized by xst as a rom) "Marco" <marcotoschi@email.it> a écrit dans le message de news: ee8bfb0.2@webx.sUN8CHnE... > To print text on display I need to have font on a rom. > > Could you explain how to create a file to copy into rom?Article: 79515
In article <jn2h11pglhi80fs226ffrp8kjgagjnabqn@4ax.com>, Brian Drummond <brian@shapes.demon.co.uk> wrote: > These peope think there is ... > > http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D7816%2526CCD%253 > DUSA%2526SID%253D4746%2526DID%253DDF2%2526SRT%253D1%2526LID%253D0%2526PVW%253D > %2526BID%253DDF2%2526CTP%253DEVK,00.html This web site is your friend: http://tinyurl.com/create.phpArticle: 79516
On Sat, 19 Feb 2005 18:01:21 -0800, Tom <tagerbaek@epo.org> wrote: > A HW-designer's lament: I'm new to FPGA's, but not to HW design in general. > Xilinx/Altera et al all characterize their FPGA's in terms of (very nice) HW > features. Great, you buy an ev-kit, fire up the SW, only to discover that > the SW, i.e, HDL, hides the HW from you. A design that could have been > hand-wired in a matter of hours (using imaginary discrete chips having the > function-blocks of the FPGA) now turns into an aggravated struggle against > the SW (others have described it as pushing a rope, or searching for an > incantation which will magically make the synthesis tool behave). Isn't > there some way to do direct design instead of the tedious imposing of > constraints upon an excruciatingly stupid piece of SW? If you really want to control exactly what goes into an FPGA, you can. For starters, you can bring up FPGA_Editor (not in the free webpack, but is in both the full and the evaluation versions of the software), and put exactly what you want exactly where you want it. This is sometimes the only way to do something, but is hardly a good way to do most designs. I mostly use this to see what was built by the tools, and to see what I want the tools to build. I suggest that novice designers should spend some time with FPGA_Editor to learn what is there and how it can be connected. There is XDL, a very low level language that allows for full control. This displays some information that FPGA_Editor does not for some of the older parts. This was very useful to me once, I have not used this for a while, but it is still around. At fairly widely useful level, look in the Xilinx Install Directory for: \vhdl\src\unisims\unisim_VCOMP.vhd This file has the component declarations for the real primitive elements that are in the parts. You properly include this library, and then you can write your design with a netlist of elements, each of which you can position in a fixed or a relative location. This is worth knowing how to do for a speed critical section of a design. For putting multiple items of the same type down learn about the VHDL "Generate" statement. Finally, spend enough time on the learning curve so that you understand what about logic will be built from a given source. If you are pushing the speed hard, you may want to use lots of primitives will full placement information. If you are pushing the speed somewhat, you may need to use some, and learn a little about floorplanning. My impression is that most designs are done with VHDL (or with Verilog) this way because: 1) The code is faster to write 2) The code easier to maintain 3) Performance is high enough for most uses. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 79517
When I was researching kits for myself I discovered that either the kits didn't have all the hardware I was looking for, had a lot of hardware I wasn't looking for or were way out of my price range. The conclusion I came to for why a lot of them are so expensive was the size and speed grade of the device the board was centered around and licensing for development software and PCI cores. One of the kits I gave some serious consideration to but decided they were still outside my price range was Alpha Data (http://www.alpha-data.com). The have a selection of card offerings and a lot of the software is available from their ftp server. You could start with an unpopulated card and add modules later. I even found a company with a 3D graphics accelerator that I think could have fitted one of the module's sites. If you take a look at the kits that connect through the parallel, serial or USB ports tend to be the bottom of the line as far as speed grades (well maybe not all of them). But what I finally ended up settling on was one of the Altera's NIOS II development kits. For a limited time they are offering it with Stratix II EP2S60ES (engineering sample). After the initial offering I guess they are only going to sell it with the EP2S30 (production device). I also have an interest in high performance, parallel processing and supercomputer (like) applications. In the corner of one of the rooms in my apartment sits a couple of cabinets with ~160 T800 transputer processors. One of the projects I have in the back of my mind is using NIOS II processor cores design something similar. While at one of the Altera sponsored events in Ma. (I think it was SOPC World) one of the other attendees asked how many processors could fit on a device. The rep couldn't provide an answer but it was one of the first things I tried with my kit. I found I could add 16 fast NIOS II processors with 9k of CACHE and a SDRAM controller and still have about 25 % of the device left for other peripherals. While I realize it isn't anywhere as fast as PCI, I could have easily added an Ethernet core to communicate to a host. Most of the kits offered are meant to just get you started. After you get started you really are kind of expected to started developing you own platform or boards. DerekArticle: 79518
Austin, thanks, I got the message regarding HDL (still I find 50 pages of hierarchical schematics a lot more readable than 50k lines of code, though). But look: the purpose is to use Spartan-3/400s as front-ends for 200Msps DACs and ADCs. I'll be using only the BRAMs and maybe 3-5% of the CLBs, so the logic is simple, but the required speed is critically close to the published S3 limits. Things like ensuring nice, parallel data-flows spring to mind; for example, one could shuffle the bit order in the RAM to prevent needlessly crossed lines. However, I haven't been able to find any pertinent information in the S3 documentation. There's a 1000 tricks and considerations like the above, which every HW-designer knows, but they all reside in that very boundary where HDL-synthesis takes over. I have nothing against HDL, I just wanna get this thing flying, fast. Cheers, TomArticle: 79519
Michel Billaud wrote: > Hi, > > Some CS research papers propose the use of FPGA as PC co-processors > for very specialized hard computing task (like searching DNA sequences). > > It's easy to find starter kits in the $100-200 range to experiment with > FPGAs, but connecting them through the parallel port doesnt give a > supercomputer :-; and the price of PCI based cards seem to be 2 orders > of magnitude higher. Why is it so ? Is there no market niche for a > cheap (say $200-500) general purpose co-processor card ? > > (Just wondering) Writing a PCI driver for the various Windows PC platforms is not that trivial. Then come the powerusers that wish changes or don't the stuff to run because they understand it differently. Meaning such an undertaking requires a hotline with seasoned staff to answer questions that the users are able to get it going. Who is going to pay for this support ? Beside that the powerful chips, meaning the big and fast ones, are sometimes beyond the 500$ mark for the chip alone, no printed circuit board yet. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 79520
Phil, thanks for the valuable info. I will try it before my 60-day SW evaluation period expires. As it were, my design is indeed very simple and very fast. Cheers, TomArticle: 79521
I'm having a problem using the Xilinx Memory Interface Generator program to create a 48bit (x8 componentst) controller in a 456 pin Spartan X3c1500. The documentation says it works, put when I run the program it always says "could not find the pins for all the clks and data masks". I'm using banks 2/3 data and 5/6 adr. I'm using the newest release 5 version SteveArticle: 79522
Tom, Well, as for fast, HDL is the way to go (as in get it done quickly). Time saved by simulating, etc. will pay off later. Fast (as in performance) is tougher. Even in a schematic, you can not tell the place and route software how to route everything. In fact, constraints with or without a schematic are required to get the best performance. Or, as one suggested, open up FPGA Editor, and see what is happening. (May do that in any event). The tradeoff is a difficult one: become an HDL expert and a constraints expert, or stick with schematics and hack constraints... I prefer the first, as it will serve you better as you do other projects. It will start slower, and finish faster, though. Austin tom wrote: > Austin, thanks, I got the message regarding HDL (still I find 50 pages of hierarchical schematics a lot more readable than 50k lines of code, though). But look: the purpose is to use Spartan-3/400s as front-ends for 200Msps DACs and ADCs. I'll be using only the BRAMs and maybe 3-5% of the CLBs, so the logic is simple, but the required speed is critically close to the published S3 limits. Things like ensuring nice, parallel data-flows spring to mind; for example, one could shuffle the bit order in the RAM to prevent needlessly crossed lines. However, I haven't been able to find any pertinent information in the S3 documentation. There's a 1000 tricks and considerations like the above, which every HW-designer knows, but they all reside in that very boundary where HDL-synthesis takes over. I have nothing against HDL, I just wanna get this thing flying, fast. Cheers, TomArticle: 79523
Hi, There is a short presentation on modeling synchronous edge triggered FSMs in Verilog, at: http://www.engr.sjsu.edu/crabill The VHDL syntax will be different, but the modeling techniques are the same. Hope that helps, Eric fpgawizz wrote: > > Where is a good place to find info on building VHDL moore FSMs? I am trying > to design a vending machine with the following features on a spartan 3 > kit. > It has the following features: > 1) 5 products price - 55/60/65/70/75c > 2) 3 different coin inputs -25 c/10c/5c > 3) Need to display the product price and price entered via the 3 coin > inputs.(first 2 digits display coin input values, last 2 digits display > product price, use any digits to display change out) > 4) When the value of product selected is reached, it should be dispensed > and any change displayed. > 5) System should reset after this and also reset if done asynchronously. > > The books I have talk about FSMs for 4-5 pages. Not good enough for me to > start thinking about this the right way. > thanksArticle: 79524
"TonyF" <not@valid.address> schrieb im Newsbeitrag news:ZX0Sd.1675$%F6.1428@newsfe4-gui.ntli.net... > > Nonsense. XST can handle inouts quite good. > > Only if they are at the top level. If they are in a sub-module, XST will > complain about not finding the *_I, *_O and *_T ports in your sub-module > (see my other post). ???? If you have ionout between modules that go not offside, XST can handle them too. But I wouldnt use inout inside the FPGA, there is no reason to do so and after all it will not translate in "real" tristates in newer FPGA families and uses up more ressources than seperate ins and outs. Regards Falk
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