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Jeremy Stringer wrote: > Stephen Williams wrote: > >> Rene Tschaggelar wrote: >> >>> Writing a PCI driver for the various Windows PC platforms is >>> not that trivial. Then come the powerusers that wish changes >>> or don't the stuff to run because they understand it differently. >> >> >> >> That is being generous. Actually, writing a Windows PCI driver is >> a royal pain if you want any kind of high performance bus mastering >> et al. I can't in fact imagine being able to get away with giving >> a customer any kind of Windows driver for an FPGA. > Another option would be to write a PCI driver for Linux - there's lot of > source code for drivers that already exist, for a start. It all depends > on who you want using it :) I know this was/is the approach taken by > WAND (www.wand.net.nz) when they were originally doing research on > network measurement gear. > > Does anybody know how the relative difficulty of the two approaches > differs? I would have suspected that linux would be slightly easier due > to more examples/code available, better documentation, and more > open-source people to discuss the code with. Linux drivers are tons easier. Day Job writes Linux drivers for our boards *first*, so that we can debug the boards if we need to, and only after the Linux driver and hardware is stable do we even *start* writing the Windows driver. This approach really does save us a great deal of pain and suffering. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 79551
Does anybody know what is meant by "RAM-based emulation device" ? DSP56651 is a development device for DSP56652. DSP56670 is a development device for DSP56690. What is the difference between emulation device to the actual device ? I got this statement from Motorola (well...Freescale) webpage. These so called "DSP56XXX" ASICs are an SoC with a u-Controller and a DSP device which supports multiple cellular standards (TDMA, CDMA, GSM, etc). Their target is cellphones...Article: 79552
I used the wysiwyg option for a cpld design, and the compiler generates wrong code. What's it's purpose ? MIKEArticle: 79553
Peter Alfke wrote: > Well, ell. > CE is not such a good solution when the two clocks are unrelated or > have an uncertain phase relationship. The worst one could do is to feed > an asynchronous CE into a long counter. First synchronizing the CE to > the faster clock domain, before using it, is better. > It is hard to make a definitive suggestion when the real design is > unknown... > What does the counter output do, how many clock domains are involved, > etc? > Peter Alfke Another solution, on admittedly sparse information, could be to have two counters, and then mux the outputs ? Seems any system to MUX clocks will need special care to avoid extra clocks, or dangerously narrow clocks. Because the speed is relatively slow, you could preface the MUX with a faster clocked state engine, that conditions both clocks, and extracts genuine edges. These edges becomes the CE to the main counter. -jgArticle: 79554
I do not want to sound obnoxious, but "my" clock multiplexer is safe. It does not create a glitch nor a runt pulse, provided metastability settles within one half period. And that is practically guaranteed: at the quoted clock rates, MTBF is many billion times longer than the expected life of the universe... And as I wrote before, no matter how you design with two clocks of unknown phase relationship, you have to deal with metastability, and everything becomes probabilistic... Peter AlfkeArticle: 79555
On Sat, 19 Feb 2005 21:46:46 -0800, AL wrote: > > >Hi, Thanks Bart for that answer. Yeah that's actually what I am working on right now, and stuck on one part, how do you know when it fail, and how do you know what the bit error rate is? In simulation I can see everything, but when I actually download the code to the FPGA, I don't know what's going on in there. I tried reading the result back via JTAG register, but it didn't work, BSCAN JTAG only allows me to read back register with very simple program. With a program this complicated, it didn't work. In addition to this bit error rate measurement, my boss wants a DNL and INL measurement; so as soon as I get done with this bit error rate measurement, I have to work on the DNL and INL part. Greatly appreciate if anyone can help! Thanks, Ann < The bit error rate measurement is fairly simple once you have the transmit and receive blocks with a compare. Build a counter large enough for your fail count (with an overflow indication in case it exceeds your expected fail count) increment the counter on every miscompare. Wire the counter output to a register that you could read with your JTAG interface and read the fail count. The bit error rate is simply the ratio of the number of bad compares to the number of bits transmitted. There are some variations to the calculation if you want log error rate etc but it should be a quick calculation. If you are having trouble reading out the result you could build a serial or parallel interface of your choosing to the PC. Something like SPI, I2C, 4 bit parallel (or just wire out to a bunch of 7 segment displays.) I have had good results building a serial 3 wire custom SPI interface on the FPGA and using the PC printer port to clock the FPGA register bits out. For your INL and DNL measurements I am not sure where they would fit in with what I understand about your project. From the work I have done with INL and DNL measurements there is usually a DAC or an ADC that is the subject of the measurement. If you can give some more details about the functional blocks you are trying to test I might be able to propose a few options. Regards, BartArticle: 79556
Hello: Could someone please tell me the procedure for the MicroBlaze for downloading a program to memory external to the fpga. Also how do you specify the start address and the stack and heap size to the compiler? Thanks, FayetteArticle: 79557
Hi Johan, Johan Bernspång wrote: > I was able to both convert to pdf and to send directly to the printer > from the printing wizard in ChipScope. I've installed service pack 3 for > ChipScope 6.3, I don't know if that has anything to do with it... Might > be worth a try if you havn't. Hmmm, installed SP3 but no change. Time to open a webcase I suppose... > I can email you some of my waveforms as pdf:s if that makes you > happier.. =) A generous offer, but probably won't help me debug my DMA bandwidth issues :) JohnArticle: 79558
Thanks Zak !! Which specific module do you use in you day to day work ? ec "ZAK" <a1kapoor@yahoo.com> ëúá áäåãòä:1108931106.677729.101720@o13g2000cwo.googlegroups.com... > Hi Eliahu, > > Just do a google search. You will find tons of matches. > I bought one from: > > http://www.digilentinc.com/ > > I am pretty happy with it. > > ZAK >Article: 79559
I have this issue where i have a top level module say A.vhd that has a state machine. I also have about 3 components - B.vhd, C.vhd and D.vhd which i am going to use to make up my top level vhd module. I have process statements in B,C and D and I want them to kick off at states 1,2 and 3 which I have defined in my main module. so I have a 3 state FSM with states 1,2, and 3 in A.vhd and at state 1, I want the process in b.vhd to kick off and at state 2 i want the process in c.vhd to kick off and at state 3, I want the process in d.vhd to kick off. Can someone guide me through this pls? thanksArticle: 79560
Dear Friends,
This is Vasudev Kulkarni, a new member.
I am working on EDK6.3i, my code is not getting synthesized.... Infact, it
gives an error, "memory conflict, system virtual memory is low" as saying.
My system has 512 MB ram, and 40GB Hard disk capacity, and moreover, my
code is a small random number generator....
Please, suggest what to do to synthesize the code.
Thanks,
Vasudev Kulkarni
Article: 79561The problem with a C compiler for a picoblaze is its too small to be seriously useful. The overhead in a complier is too large for such a tiny processor. I would stick with well documented assembler. Simon "Martin Riddle" <martinriddle@hotmail.com> wrote in message news:nD9Sd.31729$s16.31002@trndny02... > Isnt that GNU? > > "ramy" <eng_ramy_gad@yahoo.com> wrote in message news:468282399cf6dbc07fac483062f74ec2@localhost.talkaboutelectronicequipment.com... > > does anyone have a c compiler for the picoblaze? > > > >Article: 79562
The other question you need to ask is "can I still get them in 25 years time" They usually require some kind of servicing :-) Simon "Alessandro Strazzero" <alessandro.strazzero@virgilio.it> wrote in message news:391fed46.0502180459.5ad267fb@posting.google.com... > Dear everybody, > > the goal of my post is to collect your opinions about the use of Altera Cyclone > devices in a rugged environment. I have to design a board which should control > a chopper based on GTOs. The environment is a railway vehicle and the following > are the conditions I have to consider: > > - extreme temperature range (-40°C to +85°C) > - strong mechanical vibrations > - long life duration (> 25 years) > - high degree of reliability > - very low frequency of maintenance > > From the point of view of the design I think Altera Cyclone is the best choise > for this kind of project beacuse its high flexibility. But I have some doubts > about its functionality in a rugged environment like above. > > Did you experience the use of Altera Cyclone in a rugged environment ? > What are your opinions about my choise ? > > Best Regards > > /Alessandro StrazzeroArticle: 79563
Hi Bart, For the DNL and INL test, all I know so far is that I have an 8 bits ramp coming in from a transmitter, and I need to make the FPGA do DNL and INL measurements. What other information do you need? Please let me know. Also, have you ever used JTAG to read register result before? Thanks, AnnArticle: 79564
wysiwyg effects the place and route,or the logic asignment in the case of a cpld and in this mode the logic is not minimised or refactored which means that in most cases the logic is faster than a design which has had a lot of reduction and refactoring performed. The compiler producing 'wrong code' isnt effected by how much logic optimisation is performed I suggest you look elsewhere for the cause of your problems.Article: 79565
Hi, Thanks for all the helpful responses. But I still have another question. Has anyone ever used JTAG to read back a register content??? I ran into some problem doing this, and need some help. When I put a constant number into the register and read it back, it works, but when I have that number changed depending on an if else statement, it doesn't work anymore. For example, in the following code: always @(posedge CLK_IN) begin if(RESET) begin num = 20+1; end else begin num = 1+1; end It would give me 00010011 or 21 even though the RESET signal has changed. I tried using the CASE statement instead: always @(posedge CLK_IN) begin case(RESET) 2'd0: num = 20+1; 2'd1: num = 2+2; default: num = 3+4; endcase end Now it always gives me 00000000 when I tried to read it back. Do you have any idea why? Thanks, AnnArticle: 79566
"newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag news:0s2Sd.104087$JF2.54716@tornado.tampabay.rr.com... > > "newman5382" <newman5382@yahoo.com> wrote in message > news:GP1Sd.96890$qB6.89122@tornado.tampabay.rr.com... > > > > "TonyF" <not@valid.address> wrote in message > > news:rl1Sd.1774$%F6.772@newsfe4-gui.ntli.net... > >> newman5382 wrote: > >> > >>> There is a school of thought that all off chip IO should be > >>> inferred/instantiated at the top level, and not in sub-modules. > >>> > >> > >> In the end, everything is flattened and becomes top-level, but in your > >> HDL code it is useful to have sub-modules for clarity, code maintenance > >> and reusability. It should be obvious or possible to tell to a synthesis > >> tool that your inout port in your sub-module really is an external port. > >> > >> TonyF > > > > > > It is not my HDL code. > > > > Lots of things are judgement calls, and different people will choose > > differently. If I look at regular HDL (non-EDK) targeted code, if I see > > that all the primary I/O are defined in the top level, and not buried at > > some unknown level of the hierarchy, it gives me a warm fuzzy that the > > other person made some effort for other people to understand the flow of > > the design. > > > > As far as your complaint about the XST synthesys tool, since I own a bunch > > of Synplicity stock, I think it would be best for me to not address that > > issue. > > > > -Newman > > TonyF, > I looked at the code section in question. It appeared to be two IO lines > SDA, SCL that were broken out into input, output, and tristate control. I > did an I2C design a while back, and I found it convenient to break out the > signals in a similar manner. > > -Newman http://wiki.openchip.org/index.php/EDK:Using_Tristate_Ports I hope the above page answers the _I _O _T issue in full :) besides that there could be issues in my code, its old and was first attempt but proved somewhat functional, it has been tested with som real I2C devices (during that testing a bug in opencores i2c core was found) Antti PS EDK is a 'beastie' there are some things that just have to made the way EDK expects them to be or major problems can occour.Article: 79567
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42176496$0$33864$91cee783@newsreader01.highway.telekom.at... > Hello Piotr, > > With a 1C20, speedgrade 6 and using Quartus physical synthesis, I achieve > 116 MHz > (using fast-fit, in contrast: 92MHz), with speedgrade 8 (a bit cheaper...) > this > drops to 89 MHz (typical design, with SDRAM-controller). The real fmax of > course depends on your design, e.g. which periperals you are using, how full > your chip is, etc. > > If you need the CPU only for simple control tasks, you might also > considering to use our ERIC5 (www.entner-electronics.com). However, there is > no support for fast multiplications and divisons, it is more comparable to a > ATMEL AVR in performance (but higher fmax). Hi Thomas, could you please give Quartus resource utilization for ERIC5 when targetting EPM240 and executing from UFM? On your website you claim it would be 50% and that ERIC5 was initially targetted for MAX2. I am just curious to see that report :) Antti PS the two other companies that used to offer 9-Bit processors IP-Cores are now dead and vanished, hope you have better luck!Article: 79568
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:37rj4hF5ea8fvU1@individual.net... > > "TonyF" <not@valid.address> schrieb im Newsbeitrag > news:Wp%Rd.1219$%F6.1075@newsfe4-gui.ntli.net... > > > Just noticed that in your VHDL code you don't use inout ports, resulting > > in 200% bloating of a normal inout port declaration. I presume this is > > because XST is too lazy to parse inouts so that we have to do some kind > > Nonsense. XST can handle inouts quite good. > > Regards > Falk yes and no. XST can handle inout, YES , but: 1) for EDK the _I _O _T useage is required to be "EDK compliant" - this issue has nothing todo with XST inout handling 2) inout use with xilinx tools is an issue sometimes: the control port of ChipScope cores is a single port that is kinda inout as one wire has different direction, that causes very often problems, the chipscope cores are delivered as netlist and used with verilog/vhdl wrapper where the inout port is declared as unidir, this works, usually... sometimes it works better when the wrapper is defined as inout. I am just pointing out that there are cases where the 'inout' or not inout is an issue withing the xilinx toolchain AnttiArticle: 79569
Guys, many thanks for your input. I've seen the writing on the wall and will dive into HDL. BTW the fpga editor looks promising - even I can understand it at some level. Cheers, TomArticle: 79570
On Sun, 20 Feb 2005 06:42:35 -0800, tom <tagerbaek@epo.org> wrote: >Derek, thanks for the input, alas, I shall obviously have to acquire the finer points of teaching an exceedingly stupid apprentice (the HDL SW) how to do the job for me, when I could have done it myself in a fraction of the time. BTW, I got a Spartan-3 ev-kit. Cheers, Tom. A damn good start into HDL: Peter Ashenden's "The VHDL Cookbook" downloadable from http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf and it won't take long to read. His dead tree book "Designer's Guide" is pretty good too... - BrianArticle: 79571
TonyF wrote: > Just noticed that in your VHDL code you don't use inout ports, resulting > in 200% bloating of a normal inout port declaration. I presume this is > because XST is too lazy to parse inouts so that we have to do some kind > of backend annotation alongside HDL programming, resulting in a not very > elegant code. Usually it is a good style of coding not to use inouts inside the design. Especially if the design should be portable to different architectures and tools. Usually IO-pads are implemented at the toplevel, especially in ASIC based designs where the IO-ring is generated usually with automatic tools. Also I have seen formal tools to choke with internal inout ports during RTL->gate verification sometimes. --KimArticle: 79572
Jedi <me@aol.com> wrote in message news:<hgMMd.1754$zk.836@read3.inet.fi>... > Anybody has an idea why the NIOSII 1.1 toolchain build fails > on Linux/BSD systems with: > > *** ld does not support target nios2-elf > *** see ld/configure.tgt for supported targets > make: *** [configure-ld] Error 1 > > Somehow it looses "nios2-unknown-elf"... > > > It builds fine on Win2k under Cygwin... Have you used the same value for $prefix for both binutils and gcc? Is $prefix/bin in your path? Cheers, JonArticle: 79573
hi buddies anyone to respond thanks a lot...........Article: 79574
Hi finally I can announce it: http://www.eubus.net/hydraXC Reconfigurable "dream" - small and fully reconfigurable computing module. Designed to be as reconfigurable as possible, eg all of its intelligence is loaded at the boot time. The smart system management controller allows safe update of the OS image as well as the FPGA bitstream over any supported communication channel (LAN or serial or other). Of course the new hardware and OS can simply be copied to the removable media (miniSD) card, no JTAG cable (or any cable) required. There will be more information on the embedded 2005 in Nurnberg at Xilinx stands (248, 511) Antti PS if someone wants to meet me in person I will be around booth #511 tomorrow tuesday 12:00
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