Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
i dont understand....how is the internal clock delay greater than the data delay?? another thing....consider a simple gate ...what is the minimum time for which an input has to be held at the gate for its corresponding output to show ?....if there were a spike low-high-low of say 3 ns at the input , and gate Tpd is say 7 ns , would output register ?....and if it doesnt , doesnt the gate too then have some sort of a hold time requirement? and isnt this then where hold time originates?Article: 79951
cecilia annovi wrote:
> type is real, (float precision) so I'm working, to get my pourpuse, with
> floating point. Well, I found the multiplier for floating point in the mega
> wizard plug in manager (altfpmult) and it works well, but I can't find an
> adder/subtracter for floating point! I' ve tried to built one with VHDL, but
> I'm far from the target (it's not so easy..).
> So I ask you if you can find me an adder subctracter
look in:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/
-- Mike Treseler
Article: 79952On 26 Feb 2005 07:05:37 -0800, manan.kathuria@gmail.com wrote: >hi everybody , i have a few questions regarding setup and hold timing >1. what is the reason a hold time / setup time is needed....i tend to >think its down at the transistor level but i cant exactly put my finger >on it ...something to do with the prop delay? > >2. would a level triggered , i.e. non master slave type flip flop have >a setup time or just a hold time?.....since there is no intermediate >now... > >3. what happens if the hold/setup time is not met....does the output >not change or does it become unpredictable? You can imagine the setup and hold problem as a sampling settling issue. Imagine you are sitting on a table and someone far away is showing you red/blue flags. Every so often you have to lift your head see what color the flag is. If you catch the flag in transition you can't actually tell. Actually it's a window of time during which the sampling will be problematic. In the past it used to be that the starting time of the window was always before the clock and the end time was always after the clock so setup/hold times. These days with negative hold times, it's not that clear cut. The main thing is that you have to sample a signal when it is stable. If it is changing when you're looking at it, your result will not be consistent. With a latch, the same problem exists and the data has to be stable during a certain window so setup/hold parameters still exist. If this requirement is not met, the output is not predictable. It could get arbitrarily one or the other value or it could stay at an indeterminate electrival level for an arbitrarily long time (it could be metastable). For a synchronous digital circuit, violating the setup/hold times mean that your results will not be predictable.Article: 79953
>From experience, how common is it for the PLB DDR controller on the ML 310 board using a V2P30 to issue Rearbitrate (Retry) requests to the PLB master that initiated the memory transaction. I saw one such case in the following thread, but I wasn't sure if it was a bug the master logic code or just typical behavior from the DDR. http://groups-beta.google.com/group/comp.arch.fpga/messages/ae2fac060379039e,d2d9c82be77955dc,adc03dda153a66c8,0e8a8efc03c0f46d,f210c45498355b46?thread_id=72bc1bce10a2a4ac&mode=thread&noheader=1&q=#doc_ae2fac060379039e At present, I am using the PLB BRAM, which in my experience, has never issued a retry. However, I intend on migrating to using the DDR in the near future. Thanks in advance. NNArticle: 79954
The next version of Quartus will have a floafting point, addition/subtraction megafunction. It is due to be released in early Q2 of 2005. - Subroto Datta Altera Corp. "cecilia annovi" <shaula82@tiscali.it> wrote in message news:4220b713$0$6320$5fc30a8@news.tiscali.it... > hi > my name is Cecilia and I'm a student in engineering at the university of > Modena & Reggio Emilia. For my disseration I must work with Altera's FPGA. > I must analize signals from an EEG with multipliers and adders. the > signal's type is real, (float precision) so I'm working, to get my > pourpuse, with floating point. Well, I found the multiplier for floating > point in the mega wizard plug in manager (altfpmult) and it works well, > but I can't find an adder/subtracter for floating point! I' ve tried to > built one with VHDL, but I'm far from the target (it's not so easy..). > So I ask you if you can find me an adder subctracter (obviously free...! > the univesity wouldn't spend any money for my project!!)and can explain me > the way to use it (I don't have the complete knowledge of the Quartus!) > I'm using the Quartus II SJ web edition version 4.2 Built > 156.I'll develop my project on a Cyclone II technology. Thank you....! > Cecilia > > > NB. I've alredy searched in the IP megastore but their cores are too much > expensive! >Article: 79955
JJ wrote: > Wierd story, been along time since I went to junk stores, l used to buy > Plasma display tubes, TTL & cmos rams 20yrs ago but after getting into > VLSI (at Inmos on the Transputer) never actually built anything outside > the chip. But FPGAs allow an old VLSI guy without his own fab to do > something only a company with a Fab could do 5-10yrs ago. > > I contemplated trying to turn MicroBlaze and perhaps Nios into > Transputer replacements by adding on extra HW but came away thinking it > would be better to start over with sail set in the right direction day > 1. The benchmarks posted in the "NiosII Vs MicroBlaze thread" for Leon, > MicroBlaze & Opencores 1200 would seem to justify my pt but I am not > complete yet. > > Good luck with your MPP endevours too! > > regards > > johnjakson at usa dot com > > The Transputer Will be back (T2 movie) > speaking of transputers, does enough documentation exist to accurately reproduce them in a fpga?Article: 79956
Hi, I guess I don't understand something about pipeling. In my case, the whole system runs at master clock, which I would like to be 100MHz or more. Right now, the whole MAC unit is combinational logic and needs to produce an answer for each clock cycle (time x=1/100MHz). Are you guys saying that if I would run the mac at 3 times the master clock (300MHz) with a three stage pipeline, I could compute the answer fast enough? Thanks, David glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in message news:<cvo67a$828$1@gnus01.u.washington.edu>... > gretzteam wrote: > > I can't really use pipelining here. The MAC is all combinationnal; i > > receive inputs at time 0, and I need an answer by time x. I don't see > > how pipelining would help. > > What is x? > > If x is one clock cycle then you need either faster logic or > a lot more of it. I believe this can be done easily with a > three cycle pipeline, so that you get an answer out every cycle, > which each one taking three cycles. > > -- glenArticle: 79957
David wrote: > Hi, > I guess I don't understand something about pipeling. In my case, the > whole system runs at master clock, which I would like to be 100MHz or > more. Right now, the whole MAC unit is combinational logic and needs > to produce an answer for each clock cycle (time x=1/100MHz). Are you > guys saying that if I would run the mac at 3 times the master clock > (300MHz) with a three stage pipeline, I could compute the answer fast > enough? Howdy David, Using different terms, let's try another analogy on this Saturday: imagine an automobile assembly line. It puts out a certain number of cars per hour. If you add another step in the assembly process, you can still get the same number of cars per hour out - it just takes a little longer for it to roll off the assembly line. Circuits work the same way. If your main requirement is to be able to handle a certain number of calculations per second, you can possibly break the calculations up into smaller parts which are easier to do in series: rather than doing a multiply and an accumulate in the same cycle, do the multiply in one cycle, and the addition in the next cycle. While the accumulation is occuring during this 2nd cycle, the 2nd piece of data is being multiplied. On the 3rd cycle, the 2nd piece of data is now in the accumulator and a 3rd piece of data enters the multiplier. You get the same number of calculations per second out of the circuit (or perhaps even more, since you can meet timing now!), but it takes 20 ns rather than 10 ns. If you can't stand the extra delay, then you may need to up the clock rate (and then you will sure enough have to pipeline!). Hope that helps, MarcArticle: 79958
Yes sort of, see see the comp.sys.transputer NG FPGA thread status (Rams post), at the last Wotug conf Tanaka etc reported on a 24MHz near complete T425 clone cycle similar design, no timer though, no FPU ofcourse. Its their 1st step to understanding a new direction to build TP style design. I decided to skip this step, Occam capable cpus don't need to look like the old stack design and shouldn't for perf reasons. http://www.wotug.org/cpa2004/papers/361-tanaka.pdf Interesting read anyway. A few months ago on another TP thread, another student said he would do the same thing, but reverse engineering takes alot of resources that Tanaka had at his Uni. regards johnjakson at usa dot comArticle: 79959
Join us this coming Tuesday (11:00 Pacific Time) when Dr. Howard Johnson will explain the effects of ground bounce and crosstalk caused by simultaneously switching outputs. This is a highly technical talk (you will love it) with many screen shots taken with an 8 GHz scope, and with detailed comparisons of good and bad BGA packages. I will give the short "marketing" intro and conclusion, but it is Howard's show. You may know him as the author of "High-speed Digital Design", the standard reference book found on many of our bookshelves (and benches). Howard is not only a well-known and respected expert in this treacherous field, he is also a lively speaker and an excellent teacher. Enjoy ! You can register for this upcoming live webseminar, and also for the two archived predecessors: http://www.xilinx.com/events/webcasts/tol/01feb05.htm Peter Alfke,Xilinx ApplicationsArticle: 79960
Hi: Is it possible to use the Platform Cable USB with XMD. Could you please tell me how to configure this so that XMD will use this cable. Thanks, FayetteArticle: 79961
Dear all, I am a newbie and am currently having a project to develop an I2C protocol in VHDL. My aim is to communicate between two Xilinx XC4005XL, one as master and one as slave. I wonder if any of you could provide me with some ideas on how I should start. I2C has 2 wires, SCL and SDA; all I have to do is to play with these two wires? What else should be considered? What I should do next? Thanks a lot!Article: 79962
Well you could just wiggle the wires and see what happens or you could check out the i2c core at opencores.org and you could even get the documentation and read how it all works.Article: 79963
Vladislav Muravin wrote: > what is this counter for? It is supposed to be a candidate for doing sampling on signals and therefore addressing memory at a "high" speed! ThanksArticle: 79964
Göran Bilski wrote: > Hi, > > When using Xilinx, the SRL16 is a very good candidate for prescaler > implementation. > In which way would you use this shift register LUT for prescaler implementation!Article: 79965
"Jezwold" <edad3000@yahoo.co.uk> wrote in message news:1109493349.897361.135530@o13g2000cwo.googlegroups.com... > Well you could just wiggle the wires and see what happens or you could > check out the i2c core at opencores.org and you could even get the > documentation and read how it all works. ;-) Also, if he's looking to sell these, he will need to obtain a license from Phillips.Article: 79966
"Benjamin Menküc" <benjamin@menkuec.de> wrote in message news:cvq1ib$104$05$1@news.t-online.com... > Hi, > > I am planning to start fpga designing. I am not sure wheather I should start > with the livedesign kit from Altium or just with ISE? I want do develop a > spread spectrum system. I am not sure yet wheather I want to use an embedded > processor or not, but most likely I will. > > Can somebody give me some hints? > > regards, > Benjamin > > The livedesign kit from Altium comes with a nice proto board. The main claim to fame is that using their tools one can build and test an FPGA without knowing much about any HDL . This is true. Also comes with a few soft CPU cores. On a down side: 1. Doesn't understand Verilog. 2. Compared to a "real" system like ISE or Quartus ... it's a joke. The "virtual tools" are a far cry from say ChipScope. 3. Eval license is only 30 days. After that you have to buy a ridiculosly expensive full license. By contrast you can do pretty much anything with free ISE. So it's nice to play with for a beginner, but in the present form IMHO not very useful for *real work*.Article: 79967
> ;-) Also, if he's looking to sell these, he will need to obtain a > license from Phillips. IIRC you do if you want to market it with "I2C" mentioned anywhere, but if you call it something else (e.g. Two-Wire Interface or TWI) then you do not. I see "TWI" in data sheets that look remarkably like I2C at first glance and may be identical. Then again, they may have just made a mistake in the implementation so that it doesn't fully meet the I2C spec and they would get sued if a customer product failed for not meeting the spec. I2C may not be the best choice for the OP. I2C is an open-collector bus, great for talking to multiple slaves without conflict causing damage. However, it is speed limited by the rate the passive pull-ups can pull up. SPI is less clever but simpler because it does not need a clever conflict arbitration scheme. And faster as well. OP> I am a newbie and am OP> currently having a project to develop an I2C protocol in VHDL. The protocol is already developed and specified. Regarding implementation, I2C slave behaviour should be done with hardware assistance, while I2C master behaviour is easily implemented by bit-bashing a pair of open-collector pins. OP> I2C has 2 wires, SCL and SDA; all I have to do is to play with these two wires? Yep. You can even bit-bash I2C master behaviour on an LPT port. OP> What else should be considered? How will you set the address(es) of the slave(s)? How will you handle protocol failures (slave not responding, duff data, etc)? Is there a CPU in your system? How will you develop code for the 4005? IIRC it is obsolete and no longer supported by the Xilinx webpack. OP> What I should do next? If you've been set this as a university project, and the exercise is specifically for you to learn I2C, then I guess one is stuck with it. If it is your own project, ask if you really need the extra sophistication of I2C. Are there ever going to be more than one slave? If not, the slave arbitration features are pointless. As a further aside, if SPI is not to your liking then you could look at the Inmos Transputer Link protocol that Inmos developed for high-speed comms between networked transputers. I have the data sheet I could scan for you. 20 Mbits/sec, about 2 MByte/sec data rate. That's about 200 times faster than I2C, and simpler too.Article: 79968
Hello,
I am trying to get acquainted with the amount of logic it takes to
implement common structures to an FPGA. I built a simple VHDL 2x16bit
memory like follows and targeted it to a xc4013 device (which includes
block RAMs)
----
entity mem is
port( Dr: in std_logic_vector(15 downto 0);
wr: in std_logic;
clock: in std_logic;
clear: in std_logic;
Rr: out std_logic_vector(15 downto 0);
Ad: in std_logic_vector(1 downto 0)
);
end mem;
------------------------------------------------------------------
architecture behv of mem is
type ram_type is array (0 to 3) of
std_logic_vector(15 downto 0);
signal tmp_ram1_r: ram_type;
begin
process(clock, clear)
begin
if clear = '1' then
-- do nothing
elsif (clock='1' and clock'event) then
if (wr='1') then
tmp_ram1_r(conv_integer(Ad))<= Dr;
end if;
end if;
end process;
Rr <= tmp_ram1_r(conv_integer(Ad));
end behv;
----
I use Synplify 7.0.3 to synthesize the design and get the following
resource usage report:
Resource Usage Report for fft_2mem
Mapping to part: xc4013xlabg256-07
Cell usage:
GND 1 use
VCC 1 use
I/O primitives:
IBUF 20 uses
OBUF 16 uses
BUFG 1 use
I/O Register bits: 0
Register bits not including I/Os: 0
RAM/ROM usage summary
Single Port Rams (RAM16X1S): 16
Logic Mapping Summary:
FMAPs: 17 of 1152 (2%)
HMAPs: 0 of 576 (0%)
Total packed CLBs: 9 of 576 (2%)
(Packed CLBs is determined by the larger of three quantities:
Registers / 2, HMAPs, or FMAPs / 2.)
What are the 17 FMAPs used for in this design? I though that Single
Port RAMs took care of everything that I am asking the entity to do
(write the 16-bit data to a specified address) . When I look into the
technology mapping view provided by Symplify and there is no evidence
of those 17 FMAPs.
I will appreciate your help in this matter.
Rafael Arce
Student, University of Puerto Rico
Article: 79969hi all, Is the maximum frequency of operation of a sequential circuit wholly determined by the setup time analysis equation CLKlaunch+ Dmax - CLKcapture + Tsetup <= clock period or are there some other factors that are also involved? THanks MananArticle: 79970
hi all , is the maximum frequency of operation of a sequential circuit determined wholly by its setup analysis eqn ....or are there any other factors that have a bearing too?? Thanks MananArticle: 79971
thank you very much...but when the new version of Quartus will be released? I'll have my dissertation in april! thanks again Cecilia "Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio news:Xg8Ud.9017$4J7.5761@newssvr31.news.prodigy.com... > The next version of Quartus will have a floafting point, > addition/subtraction megafunction. It is due to be released in early Q2 of > 2005. > > - Subroto Datta > Altera Corp. > > "cecilia annovi" <shaula82@tiscali.it> wrote in message > news:4220b713$0$6320$5fc30a8@news.tiscali.it... >> hi >> my name is Cecilia and I'm a student in engineering at the university of >> Modena & Reggio Emilia. For my disseration I must work with Altera's >> FPGA. I must analize signals from an EEG with multipliers and adders. the >> signal's type is real, (float precision) so I'm working, to get my >> pourpuse, with floating point. Well, I found the multiplier for floating >> point in the mega wizard plug in manager (altfpmult) and it works well, >> but I can't find an adder/subtracter for floating point! I' ve tried to >> built one with VHDL, but I'm far from the target (it's not so easy..). >> So I ask you if you can find me an adder subctracter (obviously free...! >> the univesity wouldn't spend any money for my project!!)and can explain >> me the way to use it (I don't have the complete knowledge of the >> Quartus!) >> I'm using the Quartus II SJ web edition version 4.2 Built >> 156.I'll develop my project on a Cyclone II technology. Thank you....! >> Cecilia >> >> >> NB. I've alredy searched in the IP megastore but their cores are too much >> expensive! >> > >Article: 79972
JJ wrote: > Yes sort of, see see the comp.sys.transputer NG > > FPGA thread status (Rams post), at the last Wotug conf Tanaka etc > reported on a 24MHz near complete T425 clone cycle similar design, no > timer though, no FPU ofcourse. Its their 1st step to understanding a > new direction to build TP style design. I decided to skip this step, > Occam capable cpus don't need to look like the old stack design and > shouldn't for perf reasons. > > http://www.wotug.org/cpa2004/papers/361-tanaka.pdf > > Interesting read anyway. A few months ago on another TP thread, another > student said he would do the same thing, but reverse engineering takes > alot of resources that Tanaka had at his Uni. > > regards > > johnjakson at usa dot com > Thanks, ill have to keep an eye out there.. I have an old Buchsbaum book that discusses 'current' technology CPU's ( current when i bought the thing ) and it also discussed the Transputer T800, but it never did seem to have enough detail to recreate it.. Back then i was going to do it in a 8051 ( yes, i know about speed issues ) since FPGAs really didnt exist yet...Article: 79973
cecilia annovi wrote:
> thank you very much...but when the new version of Quartus will be released?
> I'll have my dissertation in april! thanks again Cecilia
> . . .
> but how can I use these packages? I don't have much experience with VHDL...
> I have already tried to include a package in a project but unsuccessfully
> ...thanks a lot again Cecilia
Consider simplifying or delaying your dissertation.
A marketing "Q2" means July 1, and learning vhdl
any sooner is unlikely.
-- Mike Treseler
Article: 79974Preben, it's a deal: You tell us no details, we give you no advice. That's what you seem to want. Peter Alfke
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z