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RobertP wrote: > > time violations when synchronized to the main clock. I know about > ASYNC_REG constraint that makes that no 'X' propagates through the > desing when timing violation happens. However the timing violations are > still reported in Modelsim, and because there are many of them it is > difficult to spot the messages that may be really important. > Is there any way to switch off reporting setup/hold timing warnings for > a particular flip/flop? Any other ideas? You can use the tcheck_set command in modelsim to remove timing checks from the synchronising elements. You can remove one single check or all of them. See the example below. Note that if you try to remove nonexisting check or element Modelsim sometimes crashes :) tcheck_set /dut_top/dut_inst/foobar1 "( PERIOD (posedge CLK) )" OFF tcheck_set /dut_top/dut_inst/foobar2_reg OFF --KimArticle: 77601
Douglas Sykora a écrit : > I am trying to find the state register which is called state in my code, but > of course it can not be found with the node finder. Does anyone have any > suggestions on how to find the signals using the RTL viewer, equations, > *.map.rpt, or *.fit.rpt. > My code is written in VHDL and I am using Quartus II 4.1. I am doing > synthisis in Quartus II. Hello Look at the compilation report, in the "analysis & synthesis/state machines" section. There you'll find how your states are encoded and the associated FF names -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 77602
Uwe Bonnes wrote: > Ise works quite a long way. Calling > XST from ISE is dead slow, due to a Linux kernel bug. However you can't > use the programming tools talking to the hardware. I tried to install the ise 6.3 with wine, but it didn't work. Do you have some hints? (Using SuSE 9.2 prof) Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 77603
> I am trying to design an interface between an XScale PXA255 CPU and an > Altera FPGA - we have a working SRAM-like asynchronous interface, but > would like to make it synchronous for improved performance and lower > latency. > Has anyone solved this problem before or know of a suitable > way to do it? I did this on a Virtex2 with four Chip-selects from the CPU: - the first one was used for reading/writing registers we built inside the FPGA, fixed/low latency, just adress-decoding - the next was used for a fast read-only SRAM access with bursts-of-8 - whenever the CPU wanted to read the other modules in the FPGA had to wait. Fixed latency, something around 8 cycles but with burst access. A little complicated priority handling inside the ram-controller but it worked :-) - on a second SRAM we could not afford any priority for the CPU - only if one of the other 2 modules had no writes the transfer (single rd/wr) from the CPU was possible. The CPU was blocked with the ready-pin. In our case this was possible as this was only for debugging purposes. The priority issue for ram-access was much easier that way. - The last chip-select was used for a second low-speed bus that came out of the fpga. There we attached some more peripheral there as the PXA-FPGA bus had to run at 100 MHz ... As Jeff stated - it's possible but the solution depends on what you want to do .. bye, MichaelArticle: 77604
Michael Schuster <schusterSoccer@enertex.de> wrote: > Uwe Bonnes wrote: > > Ise works quite a long way. Calling > > XST from ISE is dead slow, due to a Linux kernel bug. However you can't > > use the programming tools talking to the hardware. > I tried to install the ise 6.3 with wine, but it didn't work. Do you have > some hints? (Using SuSE 9.2 prof) There are several web sites, dedicated to Wine and Xilinx. First try to get help there, then ask again with precise information what's going wrong. One pitfall during the installation are messageboxes that get put _under_ other windows. Move the windows to click okay and continue. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 77605
Kim Enkovaara wrote: > > You can use the tcheck_set command in modelsim to remove timing checks from > the synchronising elements. You can remove one single check or all of them. > See the example below. Note that if you try to remove nonexisting check > or element Modelsim sometimes crashes :) > > tcheck_set /dut_top/dut_inst/foobar1 "( PERIOD (posedge CLK) )" OFF > tcheck_set /dut_top/dut_inst/foobar2_reg OFF > Looks like a goog solution, but unfortunately this command is available in Modelsim SE and not in Modelsim PE nor Modelsim SE that we have in the office. -- Regards RobertP.Article: 77606
"Jezwold" <edad3000@yahoo.co.uk> writes: > It might be better to use one of the fpga's which have built in sram > and save yourself a lot of problems.A full dram interface is quite > complex and sdram interface is a major design. > I doubt there's be enough internal SRAM for a frame buffer of any great size, except maybe in the really big devices! DRAM isn't that hard and neither is SDRAM. I did one as my first major bit of FPGA work. With the help of the micron datasheets and VHDL models I made one to do just what I wanted - which was also for video, so had no refresh! After lots of simluation, the first synthesized version Just Worked, which surprised me (even though that's how it's supposed to work :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 77607
Hi newsgroup folks, I am trying to use the new EC/ECP - DDR interface which can be instantiated in the IP-Manager of ispLEVER4.2 When trying to map it I get a memory error and the mapping is aborted. I am using WINDOWS2000 SP4 Has someone tried to use this new interface ? Have you experienced such errors? What other experiences did you have with that new interface? Thank you for you opinion. Rgds AndréArticle: 77608
If you can't find SRAM lying around, or don't have enough I/O pins to handle the non-multiplexed address, I'd suggest SDRAM first for ease of use, however if you're not up for a real challenge stay away from DDR parts. Older asynchronous DRAM has a relatively simple interface, but you may find it hard to operate at a reasonable rate for video buffer unless your data bus is quite wide. I've used SDRAM at 100 MHz with little difficulty in meeting timing on Virtex (not Virtex II) and Spartan II in the slowest speed grades. DDR SDRAM can halve your data bus width but it is a challenge to meet timing even at 100 MHz unless you go to a more recent part with DDR registers in the IOB. Not to mention the headache of SSTL_II and its termination and reference voltage requirements, and 2.5V Vccq... Generally I don't use any standard IP for the SDRAM control, but roll my own state logic for the job at hand, which in video buffers is usually streaming input and output with dedicated bandwidth for each (much simpler than general random access). I haven't tried using CPLD's for this, but the state logic is not huge so I imagine it could fit in one. Most of my designs are IO limited in even small FPGA's. If your SDRAM has excess bandwidth, a simple approach to control is to have a constant "superstate" length, say 21 clock cycles which would perform either 16 writes (burst to each of 4 banks), 16 reads, or one auto-refresh - depending on the requirements at the start of the "superstate." The extra cycles are sufficent to leave the memory precharged and ready for the next task. Good Luck, Gabor Martin Thompson wrote: > "Jezwold" <edad3000@yahoo.co.uk> writes: > > > It might be better to use one of the fpga's which have built in sram > > and save yourself a lot of problems.A full dram interface is quite > > complex and sdram interface is a major design. > > > > I doubt there's be enough internal SRAM for a frame buffer of any > great size, except maybe in the really big devices! > > DRAM isn't that hard and neither is SDRAM. I did one as my first > major bit of FPGA work. With the help of the micron datasheets and > VHDL models I made one to do just what I wanted - which was also for > video, so had no refresh! After lots of simluation, the first synthesized > version Just Worked, which surprised me (even though that's how it's > supposed to work :-) > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 77609
On 11 Jan 2005 11:45:50 -0800, "Gabor" <gabor@alacron.com> wrote: >High impedance is always relative to something. In this case I am >using the Vref pin of the LP2995, which was designed to create a more >stable reference voltage than the Vtt (termination) output. The Vtt >is used to source and sink current from a lot of 50 ohm resistors and >has a good deal of noise on it. OK. I misunderstood your post - I thought that the LP2995 was dedicated to providing your reference. If it's biasing a bunch of terminations then it will, as you say, be noisy. Your heads-up is useful - thanks. However, I still take issue with your use of the word "impedance", which seems to me to describe small-signal behaviour, whereas you are using it to describe the current-limited large-signal behaviour of a reference output. My guess is that the LP2995's Vref output exhibits a small-signal impedance of an ohm or less. Yes, I know I'm being pedantic. Sorry, it's the way I'm made. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 77610
Uwe Bonnes wrote: > Michael Schuster <schusterSoccer@enertex.de> wrote: >> Uwe Bonnes wrote: > >> > Ise works quite a long way. Calling >> > XST from ISE is dead slow, due to a Linux kernel bug. However you can't >> > use the programming tools talking to the hardware. >> I tried to install the ise 6.3 with wine, but it didn't work. Do you have >> some hints? (Using SuSE 9.2 prof) > > There are several web sites, dedicated to Wine and Xilinx. First try to > get help there, then ask again with precise information what's going > wrong. One pitfall during the installation are messageboxes that get put > _under_ other windows. Move the windows to click okay and continue. Well 1. I didnot find any site with it, though I've searched more than 2 hours. 2. You told "On a well configured and recent wine, Ise works quite a long way" The last sounds to me, you have such a config (?). Again, if you can give me a hint, an adress, please do so. Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 77611
On Mon, 10 Jan 2005 10:59:22 +0100, Michael Schuster wrote: > Hello, > we want to start with xilinix on our linuxboxes (SuSE). We're new to xilinix > -tools. I've seen, that the ISE tools might run with wine under linux. My > Q: Does it work with the usb-download or perhaps is there a site to look > at? > > Thanks > Michael The standard Xilinx tools are Linux native, the free webpack tools aren't. I'd suggest that you buy the tools. I'm running the tools on Mandrake 10.1, Whitebox (RHEL 3), and on Fedora Core 3, they work fine on both of those all of those distributions. You won't have any trouble with SUSE. The only thing that you can't do under Linux at the moment is use Chipscope. It's also not practical to use Impact, the driver support is limited to the kernel in Redhat 8.0 which is obsolete and was one of Redhat's worst releases. Hopefully 7.1 will add Linux support for Chipscope and Impact, but until then you might have to keep a old Windows machine in your lab. My clients generally keep some old PII or PIII clunker with Win2K in the lab for downloads.Article: 77612
Michael Schuster wrote: > Uwe Bonnes wrote: > >> Michael Schuster <schusterSoccer@enertex.de> wrote: > Well > 1. I didnot find any site with it, though I've searched more than 2 hours. Oh no, just typed and found I searched for xilinix instead of xilinx ... > The last sounds to me, you have such a config (?). Again, if you can give > me a hint, an adress, please do so. This holds true. Michael -- Remove the sport from my address to obtain email www.enertex.de - Innovative Systemlösungen der Energie- und ElektrotechnikArticle: 77613
B. Joshua Rosen wrote: > > The standard Xilinx tools are Linux native, the free webpack tools aren't. > I'd suggest that you buy the tools. I'm running the tools on Mandrake > 10.1, Whitebox (RHEL 3), and on Fedora Core 3, they work fine on both of > those all of those distributions. You won't have any trouble with SUSE. > The only thing that you can't do under Linux at the moment is use > Chipscope. It's also not practical to use Impact, the driver support is > limited to the kernel in Redhat 8.0 which is obsolete and was one of > Redhat's worst releases. Hopefully 7.1 will add Linux support for > Chipscope and Impact, but until then you might have to keep a old Windows > machine in your lab. My clients generally keep some old PII or PIII > clunker with Win2K in the lab for downloads. You must still be running ISE6.2 (like me) ;) Actually, even with 6.2, Xilinx provided driver source code for the driver needed by Impact, and it compiles and runs fine on RH9. I would guess that it will also work fine on RHEL3. Supposedly 6.3 includes a Linux version of Chipscope. One of these days I'll get around to installing that version and trying it out. 6.3 also officially supports RHEL. -- My real email is akamail.com@dclark (or something like that).Article: 77614
Jonathan Bromley wrote: > On 11 Jan 2005 11:45:50 -0800, "Gabor" <gabor@alacron.com> wrote: >>High impedance is always relative to something. In this case I am >>using the Vref pin of the LP2995, which was designed to create a more >>stable reference voltage than the Vtt (termination) output. (snip) > However, I still take issue with your use of the word > "impedance", which seems to me to describe small-signal > behaviour, whereas you are using it to describe the > current-limited large-signal behaviour of a reference > output. My guess is that the LP2995's Vref output > exhibits a small-signal impedance of an ohm or less. As far as I know, it can be either V/I or dV/dI, and you just have to know which one it is. For real measurements you have to change enough to measure the change big or small. -- glenArticle: 77615
On Wed, 12 Jan 2005 08:53:04 -0800, Duane Clark wrote: > B. Joshua Rosen wrote: >> >> The standard Xilinx tools are Linux native, the free webpack tools aren't. >> I'd suggest that you buy the tools. I'm running the tools on Mandrake >> 10.1, Whitebox (RHEL 3), and on Fedora Core 3, they work fine on both of >> those all of those distributions. You won't have any trouble with SUSE. >> The only thing that you can't do under Linux at the moment is use >> Chipscope. It's also not practical to use Impact, the driver support is >> limited to the kernel in Redhat 8.0 which is obsolete and was one of >> Redhat's worst releases. Hopefully 7.1 will add Linux support for >> Chipscope and Impact, but until then you might have to keep a old Windows >> machine in your lab. My clients generally keep some old PII or PIII >> clunker with Win2K in the lab for downloads. > > You must still be running ISE6.2 (like me) ;) Actually, even with 6.2, > Xilinx provided driver source code for the driver needed by Impact, and > it compiles and runs fine on RH9. I would guess that it will also work > fine on RHEL3. > > Supposedly 6.3 includes a Linux version of Chipscope. One of these days > I'll get around to installing that version and trying it out. 6.3 also > officially supports RHEL. I wasn't aware that they had released a Linux version of Chipscope, that's good news. I am running 6.3SP2, not 6.2, but 99% of my Xilinx tool time is doing synthesis, place and routes. I don't spend much time in the lab and when I do it's at a client so I use whatever they have installed. The performance of fpga_editor and floorplanner seems much better, they are both working fine across an ethernet connection now. At one time the X-Windows performance was awful but now it's fine, I wonder if that means that they've switched toolkits for 6.3 or if the old toolkit has been fixed.Article: 77616
On Wed, 12 Jan 2005 16:41:10 +0100, Michael Schuster wrote: > Uwe Bonnes wrote: > >> Michael Schuster <schusterSoccer@enertex.de> wrote: >>> Uwe Bonnes wrote: >> >>> > Ise works quite a long way. Calling >>> > XST from ISE is dead slow, due to a Linux kernel bug. However you can't >>> > use the programming tools talking to the hardware. >>> I tried to install the ise 6.3 with wine, but it didn't work. Do you have >>> some hints? (Using SuSE 9.2 prof) >> >> There are several web sites, dedicated to Wine and Xilinx. First try to >> get help there, then ask again with precise information what's going >> wrong. One pitfall during the installation are messageboxes that get put >> _under_ other windows. Move the windows to click okay and continue. > Well > 1. I didnot find any site with it, though I've searched more than 2 hours. > 2. You told "On a well configured and recent wine, Ise works quite a long > way" > The last sounds to me, you have such a config (?). Again, if you can give me > a hint, an adress, please do so. > > Michael I have a page that provides information on running Xilinx tools on Linux with wine. I stopped maintaining it when Xilinx started offering native Linux tools. However you should fine it helpfulfor running webpack undre wine. http://www.polybus.com/xilinx_on_linux.htmlArticle: 77617
Hi, I was looking for some low-cost FGPA board for a home project. What I need it to have is -USB 2.0 -Analog output/input (either) -optionally several switches, leds, maybe display, but not necessary if has nice software control -possibly pins to access FPGA ports directly, like a 40 or 50 pin connector What I've found so far is http://www.opalkelly.com/ - nice looking small board for under $200, which does not have analog ports. Thank you in advanceArticle: 77618
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:cs16o1$2619$1@agate.berkeley.edu... > Uh, you'd be suprised what a researcher would want to do. EG, one > research bit I did loaded Xilinx designs after placement but before > routing, ripped up all the registers, duplicated them for C-slowing, > retimed, reinserted all the new registers, and wrote back out the > placement. > > I could EASILY see an interesting research project which "meer mortal > researchers" could attempt which would be take a bunch of easypath > parts, map the actual defects, and route around defets albeit at a > performance penalty. As I said, I wont stop anyone. But this looks like something for someone with too much free time on hands. No offence intended ;-) Regards FalkArticle: 77619
Michael Schuster <schusterSoccer@enertex.de> wrote: > > The last sounds to me, you have such a config (?). Again, if you can give > > me a hint, an adress, please do so. > This holds true. > Michael You don't give basic information: - Does your wine installation run basic programs ( e.g. notepad) ? That's a sign that it is at least somehow configured sensible. - Does it run more challenhing programs - What version is it? - And most important: What exactly doesn't work when you install Webpack? Does it unpack the installation files? If not, unzip manual like xilinx-download> unzip 6_3_02i_pc.exe best in its own directory Can you start setup.exe in that directory ... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 77620
Hi, protel demo board ? http://www.altium.com/livedesign/ usmgn "lomtik" <lomtik@gmail.com> a écrit dans le message de news: 1105553514.301760.36010@f14g2000cwb.googlegroups.com... > Hi, > I was looking for some low-cost FGPA board for a home project. > What I need it to have is > -USB 2.0 > -Analog output/input (either) > -optionally several switches, leds, maybe display, but not necessary if > has nice software control > -possibly pins to access FPGA ports directly, like a 40 or 50 pin > connector > > What I've found so far is http://www.opalkelly.com/ - nice looking > small board for under $200, which does not have analog ports. > Thank you in advance >Article: 77621
"lomtik" <lomtik@gmail.com> wrote in news:1105553514.301760.36010 @f14g2000cwb.googlegroups.com: > Hi, > I was looking for some low-cost FGPA board for a home project. > What I need it to have is > -USB 2.0 > -Analog output/input (either) > -optionally several switches, leds, maybe display, but not necessary if > has nice software control > -possibly pins to access FPGA ports directly, like a 40 or 50 pin > connector > > What I've found so far is http://www.opalkelly.com/ - nice looking > small board for under $200, which does not have analog ports. > Thank you in advance > > What is your board going to do? We have a new DSP (SHARC ADSP-2126x) and Altera Cyclone module and board coming out very soon. It is designed for embedded applications. Details will be on our web site in the next few weeks. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 77622
I would like to spilt up information on a memory data bus into its components. Some text have suggested aliases as a way of doing it. Is it the best way? Modelsim doesn't seem to show the aliases that I define, or, more likely, I don't know how to get Modelsim to show aliases. How is that done? Brad Smallridge b r a d @ a i v i s i o n . c o m 415-661-068Article: 77623
Al Clark wrote: > "lomtik" <lomtik@gmail.com> wrote in news:1105553514.301760.36010 > @f14g2000cwb.googlegroups.com: > > >>Hi, >>I was looking for some low-cost FGPA board for a home project. >>What I need it to have is >>-USB 2.0 >>-Analog output/input (either) >>-optionally several switches, leds, maybe display, but not necessary if >>has nice software control >>-possibly pins to access FPGA ports directly, like a 40 or 50 pin >>connector >> >>What I've found so far is http://www.opalkelly.com/ - nice looking >>small board for under $200, which does not have analog ports. >>Thank you in advance >> this one looks like what I've been looking for a while (a bigger FPGA would be better but what can i do ? ;o) However, anyone knows whats the status of the USBhigh-speed drivers for Linux ? XEM3001's apparently using Cypress CY68013 FX2 - is it supported under Linux ? lukasz > > > What is your board going to do? We have a new DSP (SHARC ADSP-2126x) and > Altera Cyclone module and board coming out very soon. It is designed for > embedded applications. Details will be on our web site in the next few > weeks. >Article: 77624
Hello everybody, I'm developing a software on a Cyclone FPGA. However now we are think about the security of the device : i mean, the code is stored on a flash extern to the Cyclone. What can prevent someone from copying the data on this flash and clone the product we are doing ? In Quartus there is a security bit that made me fell confortable, however it works only with a Max device. What solution do I have to protect our software ? Best regards Nick
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