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Hi Fred, Thank you for providing the code. The results in Quartus II 4.1, 4.2, are incorrect. If you the "exit" statement in Stop_Sense with a return '0', this will synthesize correctly in 4.1 and 4.2. This problem will be fixed in Quartus II 5.0.The modified VHDL is shown below: library ieee; use ieee.std_logic_1164.all; entity yy is generic ( width : natural := 4); port ( stopcell : out std_ulogic_vector(width - 1 downto 0); isboundarycell, stopnextcells : in std_ulogic_vector(width -1 downto 0)); end yy; architecture bhv of yy is function Stop_Sense ( IsSigCell, StopNextCells : std_ulogic_vector(Width-1 downto 0); CurrentCell : natural range 0 to Width-1; LookAheadDepth : natural range 1 to 16 ) return std_ulogic is begin L1:for i in 1 to LookAheadDepth - 1 loop if (CurrentCell - i) >= 0 then if StopNextCells(CurrentCell - i) = '1' then return '1'; elsif IsSigCell(CurrentCell - i) = '1' then return '0'; -- replaced exit statement !!!! end if; end if; end loop; return '0'; end; --signal StopNextCells : std_ulogic_vector (Width-1 downto 0); --signal StopCell : std_ulogic_vector (Width-1 downto 0); --signal IsBoundaryCell : std_ulogic_vector (Width-1 downto 0); begin StopCells: for i in 0 to Width-1 generate StopCell(i) <= Stop_Sense(IsBoundaryCell, StopNextCells, i, 2); end generate; end bhv; Hope this helps, - Subroto Datta Altera Corp.Article: 76901
gja, Sorry. Hit 'enter' too soon. Yes, the output structures are all identical: just select the number of pull down nmos devices, and the number of pull up pmos devices required for a given interface standard. Austin gja wrote: > Austin, thank you very much for your response. You may have addressed it, > but it was not clear to me, what about the output structures that were the > second part of my question? Are LVTTL output structures the same as LVCMOS33 > ? > > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:cppnj8$8g81@cliff.xsj.xilinx.com... > >>gja, >> >>All single ended non reference voltage standards use the same schmidt >>trigger single ended input circuit. >> >>All single ended reference voltage standards use the same differential >>comparator which has one input tied to Vref. >> >>All differential input standards use the same differential comparator >>(different that the single ended Vref one above). >> >>These three input circuits are selected by the type of standard chosen, >>and are designed to operate over the range of the Vcco voltages used, >>and designed to meet all input standards stated. >> >>The actual specifications obviously exceed (are better than) what is >>required by a standard, as the circuits have to do all of the jobs, over >>all process, voltage, and temperature corners. >> >>The published specifications are those of the standards, as publishing >>anything else would confuse those who don't understand how to interpret >>the specifications (like some purchasing agents or component engineers >>who mindlessly compare us to our competition). >> >>Austin >> >>gja wrote: >> >> >>>For Virtex II parts, I see that the Vih and Vil levels are the same for >>>LVTTL and LVCMOS33, my question is are the input structures really > > different > >>>or are they the same for the two standards. Also, are the output > > structures > >>>for LVTTL the same as LVCMOS33, since both Vol are the same, and LVTTL > > Voh > >>>is a subset of LVCMOS33 Voh. >>> >>> > > >Article: 76902
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in news:cpq10h$frl$1@gnus01.u.washington.edu: > > > Al Clark wrote: > >> I have a bdf schematic with some pins labeled DAI[13..1] & and >> DAI[14], DAI [15], etc. > > (snip) > >> After I compile, Quartus creates new assignments of my DAI pins to >> DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc >> assignments. > (snip) > >> Why are the brackets dropped in some cases at not in others? > > Hopefully someone from Altera will explain it, but I have seen some > effects that seem to be due to compatability with MaxPlus, which as I > understand it assigned names without the brackets. > > As I remember .bdf is the MaxPlus extension, and .gdf is the Quartus > extension. Rewrite the file as .gdf and maybe it will work. > > The assignments, as I understand it, are stored in a different file. > Sometimes I just edit the assignments file by hand if I can't get it > to work otherwise. > > -- glen > > bdf is the Quartus version, gdf is the older MaxPlus version. The files are in bdf format. I did have the MaxPlus menu turn on in Configure. I have since changed to the Quartus style menu, but I don't know if the problem went away. I didn't have any problem making the files work by renaming, I just don't like fixes that I don't understand. I didn't even see the problem until I looked at the pinout file. I couldn't get the right signals at DAI[20] etc because the system automatically created and assigned DAI20 to an unused pin (and left the original DAI[20] untouched) -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 76903
"everything except the squeal"? Now that is pretty graphic. EasyPath(tm) is no different that selling an FPGA that has a laser fuse blown to replace a defective column of logic. Gee, I wonder who does that with every part they sell? Get over it: a few bad memory bits (out of 20 million) is not a "slightly defective" part -- it is >99.99985% perfect. AustinArticle: 76904
I am using coregen to generate FIFOs for my design and get typically 77LUTs and 38Registers for a 1 BLOCK RAM FIFO. Seems like a lot. I remember using Cypress parts and all the addressing and such for a FIFO was already pretty much incorporated into the Channel RAM, no logic was used outside the Channel RAM to do the basic RAM functions including FIFO. Am I doing Xilinx right? Is there some primitive I should be using instead? Brad Smallridge b r a d @ a i v i s i o n . c o mArticle: 76905
I would like to store several hundred convolution coefficients for a real time computer vision core using Xilinx's V2 8000 series FPGA. does anyone know the best way to do this? How many logic cells / block RAM does storing many constant coeff's take? Is there anyway to estimate the number of LC/BRAM needed to store, say X coeff's. Would it be better to store the coeff's in some off chip memory (like SRAM)? Also is there a way to import these coefficients into the VHDL using some kind of automated process (i suppose i could write a text parser in C to import all the coefficients into the VHDL before synthesis, but maybe there is a tool to do this kind of thing)? To have to type out several hundred numbers every time I wished to change the filter is ridiculous... thanks -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 76906
Nate Goldshlag wrote: > We are using a Stratix device and have an extensive verilog test bench. > When we use the behavioral models altera_mf.v and 220model.v that come > from Quartus II version 4.2 (just out) and run the test bench (with > vcs) it compiles just fine but gets lots of errors. Many of the > failures were things like register X reads xxx and should be something > real. I thought maybe I might have to regenerate all the RAMs and such > that were generated with the Megawizard plug in manager so I did that. > It had no effect. I do not have time to track down the specifics of > why we got failures since I have a chip to develop. Needless to say I > have gone back to 4.1 SP2 and its altera_mf.v and 220model.v, which > work just fine. > > Does anyone else have experience, good or bad, with 4.2? > > Nate Hi Nate, Would it be possible to send me a code sample that reproduces this problemor your design so that we can investigate this further. I checked with the person in charge of simulation models and he said that these type of message should not occur. Subroto Datta Altera Corp.Article: 76907
Al Clark wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in > news:cpq10h$frl$1@gnus01.u.washington.edu: > > > > > > > Al Clark wrote: > > > >> I have a bdf schematic with some pins labeled DAI[13..1] & and > >> DAI[14], DAI [15], etc. > > > > (snip) > > > >> After I compile, Quartus creates new assignments of my DAI pins to > >> DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc > >> assignments. > > (snip) > Available at http://www.danvillesignal.com Hi Nate, BDF is the Quartus extension for the schematic editor while GDF is the Max+Plus II version of the schematic editor. The netlist extractor semantics are the same for both of the editors. Backwards compatibility between Max+Plus II and Quartus for schematic editing and extraction is a key goal, as there are lots of legacy schematics that have been and are being transferred to Quartus from Max+Plus II. Basically the behavior you describe ([] being dropped, and the name recreated without []) can occur in one or more of the following cases. 1. Some members of a group are of type input and some of type output. e.g. A[0..11] is a input and A[12] is an output. In that case the bus is stored internally as individual bits and the bits are named A0, A1..., A12. 2. Some members of a group do not exist. e.g. I have A[0..5] and A[7..12] but A[6] is missing. In that case the bus is stored internally as individual bits and the bits are named A0, A1..., A12. 3. The user has mixed notation in their design. e.g. I have used both A[5] and A5 in the same schematic. In that case it will be stored internally as A5. If you are not sure which case applies to your schematic, do send your design over and we can take a look. The best way to ensure that the pin names used to make assignments exist is to first compile the design through Process->Start Analysis and Synthesis. Then use the View->Node Finder and use the Pins filter to find the node names for pin assignments. These names may be dragged into the Assignment Editor. Alternatively the Assignment Editor Drop Down in the To field will show the names that can be used for Pin Assignment. Hope this helps, - Subroto Datta Altera Corp.Article: 76908
>I would like to store several hundred convolution coefficients for a real >time computer vision core using Xilinx's V2 8000 series FPGA. >does anyone know the best way to do this? How many logic cells / block RAM >does storing many constant coeff's take? Is there anyway to estimate the >number of LC/BRAM needed to store, say X coeff's. Would it be better to >store the coeff's in some off chip memory (like SRAM)? If you have enough RAM on chip, that's the obvious simple way to do it. Should be easy to figure out how much you need. Just compute how many bits you need and round up the width to fit an integer number of chips. Round up more if your size isn't a power of two and such. >Also is there a way to import these coefficients into the VHDL using some >kind of automated process (i suppose i could write a text parser in C to >import all the coefficients into the VHDL before synthesis, but maybe there >is a tool to do this kind of thing)? To have to type out several hundred >numbers every time I wished to change the filter is ridiculous... search for data2bram -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76909
Kevin Neilson wrote: > Synplify now reads the defparam 'INIT' used for instantiated SRLs, so > you can initialize the value of the SRL16 for both simulation and > synthesis with a single defparam. However, I'm wondering if there is a > way to infer SRL16 Johnson rings or shift registers with an initial > value. This can be done with registers by setting the 'reset' value of > the register to the desired value, but you can't have a reset clause > with SRLs or they won't get inferred as SRLs. It would be nice to be > able to infer a Johnson ring because if you want to instantiate SRLs you > need to instantiate one for each 16 bits of the register which makes it > hard to parameterize it. I also have another question: I put a register on the output of the SRL to register the output. I assumed that the register would be placed in the same slice as the SRL, but the placer puts them in different CLBs. Why would it do that? -KevinArticle: 76910
"Subroto Datta" <sdatta@altera.com> wrote in news:1103141267.156862.5200 @z14g2000cwz.googlegroups.com: > Al Clark wrote: >> glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote in >> news:cpq10h$frl$1@gnus01.u.washington.edu: >> >> > >> > >> > Al Clark wrote: >> > >> >> I have a bdf schematic with some pins labeled DAI[13..1] & and >> >> DAI[14], DAI [15], etc. >> > >> > (snip) >> > >> >> After I compile, Quartus creates new assignments of my DAI pins to >> >> DAI1, DAI2, DAI3, etc and ignores all my DAI[1], DAI[2], etc >> >> assignments. >> > (snip) > >> Available at http://www.danvillesignal.com > > > Hi Nate, > > BDF is the Quartus extension for the schematic editor while GDF is > the Max+Plus II version of the schematic editor. The netlist extractor > semantics are the same for both of the editors. Backwards compatibility > between Max+Plus II and Quartus for schematic editing and extraction is > a key goal, as there are lots of legacy schematics that have been and > are being transferred to Quartus from Max+Plus II. > > Basically the behavior you describe ([] being dropped, and the name > recreated without []) can occur in one or more of the following cases. > > 1. Some members of a group are of type input and some of type output. > e.g. > A[0..11] is a input and A[12] is an output. In that case the bus is > stored internally as individual bits and the bits are named A0, A1..., > A12. This is the case for my example. > > 2. Some members of a group do not exist. e.g. I have A[0..5] and > A[7..12] but A[6] is missing. In that case the bus is stored internally > as individual bits and the bits are named A0, A1..., A12. Maybe also true > 3. The user has mixed notation in their design. e.g. I have used both > A[5] and A5 in the same schematic. In that case it will be stored > internally as A5. > > If you are not sure which case applies to your schematic, do send your > design over and we can take a look. > > The best way to ensure that the pin names used to make assignments > exist is to first compile the design through Process->Start Analysis > and Synthesis. Then use the View->Node Finder and use the Pins filter > to find the node names for pin assignments. These names may be dragged > into the Assignment Editor. Alternatively the Assignment Editor Drop > Down in the To field will show the names that can be used for Pin > Assignment. > > Hope this helps, > - Subroto Datta > Altera Corp. > > Thank you for your explanation. Can you tell me where this information is in your documentation? I have a new question: I have unused inputs that may be used in a future design. They must be inputs to avoid contention with other devices. I assigned the pin as a reserved input in the assignment editor and also individually assigned it as an tri input. Will the pullup be present? If not, how do I assign an unused pin as an input with a pullup. I am using a Cyclone. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 76911
I've been using PACE, which is a pretty nice tool. It has less functionality but is much easier to use than Floorplanner. However, I have a question about it. Say I have a design that has a top-level module, 'top_level', and three modules underneath, named 'level2_a', 'level2_b', and 'level2_c'. I can place 'top_level' using PACE. I can place any of the submodules separately. However, what if I want to create a block and drop in 'level2_a' and 'level2_b', but not 'level2_c'? I can't seem to figure out how to do that. -KevinArticle: 76912
Just got the popup about the ISE 6.3.03i service pack, went to the Xilinx site and the page says 6_3_03i_pc.exe is 110Mb. Downloaded it and it came out to 261Mb ??Article: 76913
Austin Lesea wrote: > > "everything except the squeal"? > > Now that is pretty graphic. > > EasyPath(tm) is no different that selling an FPGA that has a laser fuse > blown to replace a defective column of logic. > > Gee, I wonder who does that with every part they sell? > > Get over it: a few bad memory bits (out of 20 million) is not a > "slightly defective" part -- it is >99.99985% perfect. Isn't being 99.99985% perfect like being 0.00015% pregnant? ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76914
On Wed, 15 Dec 2004 15:37:15 -0500, gja wrote: > Just got the popup about the ISE 6.3.03i service pack, went to the Xilinx > site and the page says 6_3_03i_pc.exe > is 110Mb. Downloaded it and it came out to 261Mb ?? The 139MB is a mistake, the Firefox downloader says it's 297.7MB for the Linux version.Article: 76915
This is leftover from a couple of discussions a week or two ago. There is something interesting that I don't understand. In general, if I have an input clock and I want to generate an output clock, and the output clock is (much) slower than the input clock, I can do that with a FSM. The jitter on the output clock can be up to 1/2 of the input clock off. (If it's off more, move it over by one.) If you are lucky and the numbers work out exactly, you get no jitter. (For example, dividing by 4.) But how close is the frequency? The output frequency is out = in * X / Y Y is the number of states in the FSM. Some combinations of X and Y give a better match to the target frequency. I'm pretty sure a math wizard would use continued fractions to explain it. I know how to implement this if Y is a power of 2. That's just an adder and it generally fits well into FPGA. Given a minute or 3, I can work out the value of the constant to add. It's easy to get closer to the target frequency by using more bits in the adder. If the bottom bit of the constant isn't a 1, then the adder will skip 1/2 (or 3/4 or..) of the states. So there are sweet spots where the bottom bit of the constant is a 1. This approach is also convenient if you want to make a sine wave rather than a square wave since you can feed the top N bits of the adder to a ROM lookup table. But powers of 2 may not work as well as some simple pairs of X and Y. Is there a simple implementation technique for arbitrary Y that fits well into FPGAs? Is it something as simple as use an adder and reset it back to 0 after Y steps? Is there a good web page or book that covers this area? Next step is to understand the spectrum of the synthesised clock. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76916
Use Direct Digital Synthesis (DDS) which really means that you accumulate phase angles. Think of a 10-bit binary accumulator. If the value you accumulate is 1, then it will take 1024 clock pulses to overflow. If you accumulate a 2, it will take 512 clock ticks etc. The overflow frequency is thus determined by the 10-bit value you are accumulating, with a resolution of 1 part in 1024 (but also with a max jitter of half a clock period.) With a 27-bit accumulator clocked at 100 MHz, you can generate any integer Hz frequency, but with 5 ns jitter. Peter Alfke, Xilinx ApplicationsArticle: 76917
16V* is most pupular low cost chip. from 1984, Abel 1.1 and many DOS stuff. If you want, I can burn a CD for you. I block E-mail in this AOL. hope your E-mail addr. is real one.Article: 76918
In the new Virtex-4 devices, we incorporate a FIFO controller in every BlockRAM,so the controller is free, and it can handle asynchronous clocks at up to 500 MHz. The high logic count for the controller that you quoted may be due to elaborate design tricks to cope with fast asynchronous clocks, and the need to generate a reliable EMPTY and FULL signal, even at very high speed. And perhaps also a partial FULL/EMPTY output. That requires duplicated Binary and Gray counters with sophisticated comparators and special precautions against metastability problems (All of which we did in the hidden controller in Virtex-4). If you are not running so fast, some of this can be eliminated in your Virtex-II or Spartan design, but you have to be careful. Asynchronous clocks can bite you, unless you really know what you are doing... Peter AlfkeArticle: 76919
ASICs would be very happy if they could promise 99.99985% testability ... Peter AlfkeArticle: 76920
Rick, The simple answer? No, it is not. One bad bit doth not a bad chip make. If it did, the entire RAM business would be out of business. All RAM (and EPROM) use redundant rows or columns, and redundant repair (or self repair) structures. Music CD's run with error correction correcting errors all the time (there is practically no interval where there is a single packet with 0 errors). Cell phones work with forward error correction, and they too run in the errored region all the time. Austin rickman wrote: > Austin Lesea wrote: > >>"everything except the squeal"? >> >>Now that is pretty graphic. >> >>EasyPath(tm) is no different that selling an FPGA that has a laser fuse >>blown to replace a defective column of logic. >> >>Gee, I wonder who does that with every part they sell? >> >>Get over it: a few bad memory bits (out of 20 million) is not a >>"slightly defective" part -- it is >99.99985% perfect. > > > Isn't being 99.99985% perfect like being 0.00015% pregnant? ;) >Article: 76921
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag news:beudnbybkd66N13cRVn-qg@megapath.net... > The jitter on the output clock can be up to 1/2 of the input > clock off. (If it's off more, move it over by one.) If you > are lucky and the numbers work out exactly, you get no jitter. > (For example, dividing by 4.) > > But how close is the frequency? The output frequency is > out = in * X / Y > Y is the number of states in the FSM. What you describe is called DDS, Direct Digital Synthesis. Go to www.analog.com, they have plenty of stuff for that. And also a very good tutorial on the toppic. > This approach is also convenient if you want to make > a sine wave rather than a square wave since you can > feed the top N bits of the adder to a ROM lookup table. > > But powers of 2 may not work as well as some simple pairs > of X and Y. Is there a simple implementation technique > for arbitrary Y that fits well into FPGAs? Is it something Again, DDS. It look a little bit weired on the first sight, but then turn out to a (almost) perfect oscillator. Regards FalkArticle: 76922
B. Joshua Rosen wrote: > On Wed, 15 Dec 2004 15:37:15 -0500, gja wrote: > > >>Just got the popup about the ISE 6.3.03i service pack, went to the Xilinx >>site and the page says 6_3_03i_pc.exe >>is 110Mb. Downloaded it and it came out to 261Mb ?? > > > The 139MB is a mistake, the Firefox downloader says it's 297.7MB for the > Linux version. > The sizes on the web page are being corrected. Meanwhile, here are the correct numbers: 6_3_03i_sol.tar.gz --> 287 MB 6_3_03i_lin.tar.gz --> 291 MB 6_3_03i_pc.exe --> 261 MB BretArticle: 76923
Antti,
Can you add the LMB signals to your ChipScope trace? What is the
processor doing during these 512 cycles of inactivity in between GPIO
writes? One way to help find this out is to cross-reference the objdump
output of the ELF file with the I-LMB to find out where in your code the
processor is.
One thing you may want to try to do with to replace the GPIO drivers
with simple XIo_Out32 commands that may take fewer processor clock
cycles to execute. It's possible the during this 512 clock cycle OPB
inactivity, MicroBlaze is actually executing the rest of the GPIO driver
code.
Matt
Antti Lukats wrote:
> Hi all,
>
> Christmas is closing so everybody is making presents. So is Xilinx. I just
> got mine! Read the story below:
> ***********************************************************************
> ISE/EDK/ChipScope update to 6.3
>
> In attempt to get our EDK based SoC systems up and running again in EDK 6.3
> I ended up creating simplest possible SoC using BSB (because none of working
> EDK 6.2 projects worked after update no matter any attempts to get them
> working). Attempted to debug in XMD: fatal disaster BRAM can be loaded from
> elf, can also look at the disassembly all is ok. Any attempt to trace or
> execute simplest program and all goes pasta, not any more possible to view
> (or write) even to LMB RAM ! Then I added ChipScope bus analyzer core to OPB
> bus. And simplified the test application. Here is the source code:
>
> -----------------------------------------------------------
> // Xilinx Christmas Lights application ver 1.0
> while (1) {
> i++;
> WriteToGPOutput(XPAR_LED_7SEGMENT_BASEADDR, i);
> }
> -----------------------------------------------------------
> This is running in MicroBlaze SoC at system frequency 50MHz. Pretty much all
> leds should be lit, right? Or?
>
> It looks like (due to Christmas feeling !?) Xilinx tools have decided for me
> that my application should be "Christmas Lights" - because that how it
> works! The LEDS are blinking in fancy true random fashion at "human" blink
> rate, ie very slowly. The visual effects are pretty cool, really!
>
> When looking in ChipScope (OPB bus analyzer) I see writes to the GPIO port:
> 0x00800000, 0x01000000,0x02000000,0xFFFFFFE,0xFFFFFFC... Those are 5 example
> sequential writes to GPIO port (from the above program!), notice that
> between the GPIO writes there is always more than 512 OPB clocks of no OPB
> bus activity.
>
> And yes, I did UNINSTALL ALL ISE/EDK/ChipScope before update, then installed
> all the new versions plus service packs, etc..
>
> ***********************************************************************
>
> Antti
>
>
Article: 76924No, as far as I know I picked the Synchronous option. And there seems to be no way to elliminate the Empty and Full flag outputs, which I don't think I will be using, left them open in the instantiation. There also is no relative placing of the support counters, either with respect to each other or close to the RAM block. Nice to know that the Virtex has some of this stuff built in. Brad
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