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Brian Davis wrote: > Gregory Burd wrote: > >>so I thought that there must be some FPGA with at least >>8MB of SDRAM packaged as a Type I PCMCIA card >> > > In the close-but-no-cigar category (type II), see also: > http://www.comblock.com/download/com1300.pdf > Type II PCMCIA/Cardbus, XC3S400, 32 Mb SDRAM, $295 USD > > Brian > I think I mixed up the PCMCIA sizes. Type II is okay, Type III (double that of Type II) is not. I have exactly one Type II slot to use on the Mac PowerBook G4. So, I think this card is a good option and not too expensive either. Now, if only it had Mac OS/X driver and development software... -gregArticle: 77026
You can purchase boundary scan software tools from Universal Scan that can do this. See http://www.universalscan.com/ for details. JohnArticle: 77027
"John LeVieux" <jlavie@yahoo.com> wrote in message news:1103563471.915040.223740@c13g2000cwb.googlegroups.com... > I had to add large capacitors to the LDO > regulator outputs in order to meet the minimum ramp rates. > Hmm, nasty. Next time you may want to consider using a simple RC network in the feedback path to limit the ramp rate. Cheaper, smaller and without enormous amounts of current being dumped from the supply into your monster output capacitors. Most modern switching circuits (I use the easy to use LTC3414) have 'soft start' modes which limit turn on current. Cheers, Syms.Article: 77028
Hello,
(I'm a beginner in vhdl programmation, so excuse me if my questions seem
trivial.)
I have to create a VHDL design witch runs on altera's cyclone FPGA. To
do that, I use your microtronix dev board, but not the SOPC builder
components.
The goal of the design is to create a data storage box, a kind of hard
disk where the disk is replaced by some SDRAM and a Compact Flash Card.
Does somebody know where I could find doc about this topic ? I mean, doc
about making a controller for a Compact Flash Card (it should have be
done yet),
managing read/write between flash card/sdram/controller of the
datastorage in an efficient way, etc.
I also want to be able to read/write in SDRAM and for that, I use the
Altera's SDRAM controller found here :
http://www.altera.com/products/ip/iup/memory/m-alt-sdr-sdram.html
I create a state machine to interface the SDRAM's controller and the
others part of the design. This state machine manages sdram
initialisation, and read/write queries.
All simulations work fine, but when I load my code on the board, it does
not work.
I thought it was a problem with the use of onboard clocks, but it seems
that there is something else : an other design which only made two write
statement and then alternatively read each one works fine.
I really don't know what might be the source of the problem, so what are
the things I have to check ? Are there frequently done mistakes in using
this SDRAM controller ? (I join my broken code and the working one)
I also want to split my big state machine in several parts which are
semantically consistant : one for the init, an other for reading
queries, etc. And I don't know how to
handle this problem. What is 'the right way' to do this in vhdl ?
Many thanks
--------------------------------------------------------------------------------
Working design
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sdramInit IS
GENERIC (
NOP_TIME : integer := 2;
CONSTANT C_NOP : std_logic_vector (2 DOWNTO 0) := "000";
CONSTANT C_PRECHARGE : std_logic_vector (2 DOWNTO 0) := "100";
CONSTANT C_REFRESH : std_logic_vector (2 DOWNTO 0) := "011";
CONSTANT C_LOAD_MODE : std_logic_vector (2 DOWNTO 0) := "101";
CONSTANT C_LOAD_REG1 : std_logic_vector (2 DOWNTO 0) := "110";
CONSTANT C_LOAD_REG2 : std_logic_vector (2 DOWNTO 0) := "111"
);
PORT (
clk : IN std_logic;
data_to_mp : IN std_logic_vector (31 DOWNTO 0);
rst_1 : IN std_logic;
ack_to_mp : IN std_logic;
data_to_sd : OUT std_logic_vector (31 DOWNTO 0);
cmd_to_sd : OUT std_logic_vector (2 DOWNTO 0);
adresse_to_sd : OUT std_logic_vector (22 DOWNTO 0);
dm_to_sd : OUT std_logic_vector (3 DOWNTO 0);
data_to_7seg : OUT std_logic_vector (6 DOWNTO 0);
led1 : OUT std_logic;
led2 : OUT std_logic);
END sdramInit;
ARCHITECTURE archi OF sdramInit IS
TYPE TYPE_STATE IS (reset,
nop,
precharge, prechargeNop,
loadmode, loadmodeNop,
load_reg2, load_reg2Nop,
load_reg1, load_reg1Nop,
refresh1,
refresh2,
ecriture,
ecriture2,
lecture,
lecture2,
fin,
wait1,
wait2,
wait0,
fetch1,
fetch2,
nopn,
nopn1,
nopn2,
nopn3);
SIGNAL etat : TYPE_STATE;
SIGNAL counter : integer RANGE 0 TO 255;
signal nccounter : integer range 0 to 100000000;
BEGIN -- archi
PROCESS (clk, rst_1)
BEGIN -- PROCESS
IF rst_1 = '0' THEN -- asynchronous reset (active low)
etat <= reset;
cmd_to_sd <= C_NOP;
adresse_to_sd <= "00000000000000000000000";
data_to_sd <= "00000000000000000000000000000000";
dm_to_sd <= "1100";
counter <= 0;
led1 <= '0';
led2 <= '0';
nccounter <= 0;
ELSIF clk'event AND clk = '1' THEN -- rising clock edge
CASE etat IS
WHEN reset => etat <= nop;
counter <= 0;
WHEN nop => cmd_to_sd <= C_NOP;
IF counter = NOP_TIME THEN
etat <= precharge;
counter <= 0;
ELSE
etat <= nop;
counter <= counter + 1;
END IF;
WHEN precharge => IF ack_to_mp = '1' THEN
etat <= prechargeNop;
ELSE
cmd_to_sd <= C_PRECHARGE;
etat <= precharge;
END IF;
WHEN prechargeNop => cmd_to_sd <= C_NOP;
etat <= loadmode;
WHEN loadmode => IF ack_to_mp = '1' THEN
etat <= loadmodeNop;
ELSE
cmd_to_sd <= C_LOAD_MODE;
adresse_to_sd <= "00000000000001000010000";
-- a10 : reserved = 0
-- a9 : Write Burst = 1 (single location access)
-- a8-7 : Op mode 00
-- a6-4 : CAS latency : 001 ( 1 )
-- a3 : BT 0 ( sequential )
-- a2-0 : busrt length 000 ( 1 )
etat <= loadmode;
END IF;
WHEN loadmodeNop => cmd_to_sd <= C_NOP;
etat <= load_reg2;
WHEN load_reg2 => IF ack_to_mp = '1' THEN
etat <= load_reg1;
ELSE
cmd_to_sd <= C_LOAD_REG2;
-- adresse_to_sd <= "00000000000011000011010"; -- 1562 c'est pour
100 MHz
adresse_to_sd <= "00000000000001000000000"; -- 521 c'est pour 33
MHz
etat <= load_reg2;
END IF;
-- WHEN load_reg2Nop => cmd_to_sd <= C_NOP;
-- etat <= load_reg1;
WHEN load_reg1 => IF ack_to_mp = '1' THEN
etat <= refresh1;
ELSE
cmd_to_sd <= C_LOAD_REG1;
-- adresse_to_sd <= "00000000000001001101101"; -- old value
adresse_to_sd <= "00000000000001000101001";
-- a12-9 : burst lenght : 0001
-- a8 : sdram controller mode : 0 (normal)
-- a7-4 : refresh command duration in clocks ???? t rrd = 14 ns
/ 30 ns
-- a3-2 : ras to cas in number of clocks ??? trcd = 20 ns / 30
ns ? -- bizarrement, marche bcp mieux avec une valeur de 2
-- a1-0 : cas latency : 1
etat <= load_reg1;
END IF;
-- WHEN load_reg1Nop => cmd_to_sd <= C_NOP;
-- etat <= refresh1;
WHEN refresh1 => IF ack_to_mp = '1' THEN
cmd_to_sd <= C_NOP;
etat <= refresh2;
ELSE
cmd_to_sd <= C_REFRESH;
etat <= refresh1;
END IF;
WHEN refresh2 => IF ack_to_mp = '1' THEN
cmd_to_sd <= C_NOP;
etat <= nopn;
ELSE
cmd_to_sd <= C_REFRESH;
etat <= refresh2;
END IF;
when nopn => cmd_to_sd <="000";
etat <= nopn1;
when nopn1 => cmd_to_sd <="000";
etat <= nopn2;
when nopn2 => cmd_to_sd <="000";
etat <= nopn3;
when nopn3 => cmd_to_sd <="000";
etat <= ecriture;
WHEN ecriture => cmd_to_sd <= "010";
data_to_sd <= "00000000000000000000000011111001";
adresse_to_sd <= "00000000000000000000000";
IF ack_to_mp = '1' THEN
etat <= wait0;
ELSE
etat <= ecriture;
END IF;
WHEN wait0 => cmd_to_sd <= "000";
if nccounter<9 then
nccounter <= nccounter +1;
etat <= wait0;
else
nccounter <= 0;
etat <= ecriture2;
end if;
WHEN ecriture2 => cmd_to_sd <= "010";
data_to_sd <= "00000000000000000000000000001111";
adresse_to_sd <= "00000000000000000000001";
IF ack_to_mp = '1' THEN
etat <= wait2;
ELSE
etat <= ecriture2;
END IF;
WHEN lecture => cmd_to_sd <= "001";
led1 <= '1';
led2 <= '0';
adresse_to_sd <= "00000000000000000000000";
IF ack_to_mp = '1' THEN
etat <= fetch1;
ELSE
etat <= lecture;
END IF;
WHEN fetch1 =>cmd_to_sd <= "000";
-- wait RCD + CL + 2 = 1 + 20 ns + 2clk = 3 clk
if nccounter<2 then
nccounter <= nccounter +1;
etat <= fetch1;
else
data_to_7seg <= data_to_mp (6 DOWNTO 0);
nccounter <= 0;
etat <= wait1;
end if;
WHEN wait1 =>
if nccounter<4000000 then
nccounter <= nccounter +1;
etat <= wait1;
else
nccounter <= 0;
etat <= lecture2;
end if;
WHEN lecture2 => cmd_to_sd <= "001";
led1 <= '0';
led2 <= '1';
adresse_to_sd <= "00000000000000000000001";
IF ack_to_mp = '1' THEN
-- data_to_7seg <= data_to_mp (6 DOWNTO 0);
etat <= fetch2;
ELSE
etat <= lecture2;
END IF;
WHEN fetch2 =>cmd_to_sd <= "000";
-- wait RCD + CL + 2 = 1 + 20 ns + 2clk = 3 clk
if nccounter<2 then
nccounter <= nccounter +1;
etat <= fetch2;
else
data_to_7seg <= data_to_mp (6 DOWNTO 0);
nccounter <= 0;
etat <= wait2;
end if;
WHEN wait2 =>
cmd_to_sd <= "000";
if nccounter<4000000 then
nccounter <= nccounter +1;
etat <= wait2;
else
nccounter <= 0;
etat <= lecture;
end if;
WHEN fin => etat <= fin;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END archi;
---------------------------------------------------------------------------------
My design
---------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Module SdramInterface
-- Fonctionnal description :
-- this module is an interface between the sdram controller and others
parts
-- of the design (say "ext").
-- Its goal is to manage sdram initialisation and read/write queries.
-- It implements a state machine with 4 main states :
-- - initialisation of the SDRAM,
-- - wait for a command,
-- - write on SDRAM and
-- - read on SDRAM
ENTITY sdramInterface is
GENERIC (
-- command to the SDRAM controller
CONSTANT C_NOP : std_logic_vector (2 DOWNTO 0) := "000";
CONSTANT C_init_precharge : std_logic_vector (2 DOWNTO 0) := "100";
CONSTANT C_REFRESH : std_logic_vector (2 DOWNTO 0) := "011";
CONSTANT C_init_load_mode : std_logic_vector (2 DOWNTO 0) := "101";
CONSTANT C_init_load_reg1 : std_logic_vector (2 DOWNTO 0) := "110";
CONSTANT C_init_load_reg2 : std_logic_vector (2 DOWNTO 0) := "111";
constant C_WRITEA : std_logic_vector (2 DOWNTO 0) := "010";
constant C_READEA : std_logic_vector (2 DOWNTO 0) := "001";
-- commands from/to ext
constant READ_OK : std_logic_vector (1 DOWNTO 0) := "01";
constant READ_MODE : std_logic_vector (1 DOWNTO 0) := "01";
constant WRITE_OK : std_logic_vector (1 DOWNTO 0) := "10";
constant WRITE_MODE : std_logic_vector (1 DOWNTO 0) := "10";
-- Parameter of the sdram
constant ASIZE : integer := 23; -- adress size
constant DSIZE : integer := 32; -- data size
constant DSIZE_sur_8 : integer := 4; -- data mask size
constant BL : integer := 1; --burst lengh
constant TL_W : integer := 1; --latence time on a write command
constant TL_R : integer := 4; --latence time on a read command
-- conf of sdram chip (load_mode command)
-- a10 : reserved : 0
-- a9 : Write Burst : 0
-- a8-7 : op mode : 00
-- a6-4 : CAS latency : 001 ( 1 )
-- a3 : BT : 0 ( sequential )
-- a2-0 : busrt length : 000 ( 1 )
constant CONF_init_load_mode : std_logic_vector (22 downto 0) :=
"00000000000000000010000";
-- Config of REG1 : altera controller parameter
-- a12-9 : burst lenght : 0001
-- a8 : sdram controller mode : 0 (normal)
-- a7-4 : refresh command duration in clocks : t(rrd)/clock period =
14 ns / 30.5 ns = 1 (??)
-- a3-2 : ras to cas (rcd) in number of clocks : t(rcd)/clock period
= 20 ns / 30.5 ns (? idem, 1 ?)
-- a1-0 : cas latency : 01
constant CONF_REG1 : std_logic_vector (22 downto 0) :=
"00000000000001000101001";
-- Config de REG2 : period beetwin refresh
-- value is obtained by the calcul 15.625us/T, where T is clock period
(in micro second)
-- constant CONF_REG2 : std_logic_vector (ASIZE-1 downto 0) :=
"00000000000011000011010" -- 1562 when clock= 100 MHz, T = 0.01 us
constant CONF_REG2 : std_logic_vector (22 downto 0) :=
"00000000000001000000000" -- 512 when clock= 32.768 MHz, T = .0305us
);
PORT (
-- NOTATION :
-- what is transfered to ext is prefixed by _ext_
-- what is transfered to the controller is prefixed by _cont_
clk : IN std_logic;
rst_n : IN std_logic;
-- to/from extr
i_ext_donnees : IN std_logic_vector (DSIZE-1 DOWNTO 0); --data from
ext (data to write on SDRAM)
i_ext_masqueEcriture : std_logic_vector (DSIZE_sur_8 - 1 downto 0);
--data mask
i_ext_adresse : in std_logic_vector (ASIZE-1 downto 0); --adress
i_ext_demande_rw : in std_logic_vector (1 downto 0); --ext queries
o_ext_donnees : OUT std_logic_vector (DSIZE-1 DOWNTO 0); --data to
ext (data read from SDRAM)
o_ext_sdram_ready : OUT std_logic; --wait for read/write
o_ext_rw_ok : out std_logic_vector (1 downto 0); -- ack read/write
o_ext_erreur : out std_logic; --error
-- to/from the controller
i_cont_donnees : IN std_logic_vector (DSIZE-1 DOWNTO 0); -- data
from the controller (data read on SDRAM)
i_cont_accuseCommande : IN std_logic; -- command to controller ack
o_cont_donnees : OUT std_logic_vector (DSIZE-1 DOWNTO 0); -- data
to the controller (data to write on SDRAM)
o_cont_commande : OUT std_logic_vector (2 DOWNTO 0); -- command to
the controller
o_cont_adresse : OUT std_logic_vector (ASIZE-1 DOWNTO 0); -- adress
o_cont_masqueEcriture : OUT std_logic_vector (DSIZE_sur_8 - 1
DOWNTO 0) -- mask
);
end sdramInterface;
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////--
ARCHITECTURE archi OF sdramInterface is
type type_etatProcessPrincipal is (
etat_reset, etat_erreur,
-- init states
init_attente_stab,
init_precharge, init_prechargeNop,
init_load_mode, init_load_modeNop,
init_load_reg1, init_load_reg2,
init_refresh1, init_refresh2,
init_2nop,
-- wait command state
etat_attente_instruction,
-- read states
ecriture_init,
ecriture_attente_latence,
ecriture_boucle_donnees,
-- write states
lecture_init,
lecture_attente_latence,
lecture_boucle_donnees
);
signal etat_suivant : type_etatProcessPrincipal;
signal compteur_ecriture : integer range 0 to TL_W; -- write latence
counter
signal compteur_lecture : integer range 0 to TL_R; --read latence counter
signal compteur_bl : integer range 0 to BL; -- burst lenght counter
signal i : integer range 0 to 3000; -- init counter
-- register
signal reg_o_ext_donnees : std_logic_vector (DSIZE-1 downto 0);
signal reg_o_cont_donnees : std_logic_vector (DSIZE-1 downto 0);
signal reg_o_cont_masqueecriture : std_logic_vector (3 downto 0);
signal reg_o_cont_adresse : std_logic_vector (ASIZE-1 downto 0);
BEGIN -- archi
process (clk, rst_n)
variable num_ecriture : std_logic;
begin
if rst_n = '0' then -- asynchronous reset, active low
etat_suivant <= init_attente_stab;
compteur_ecriture <= 0;
compteur_lecture <= 0;
compteur_bl <= 0;
i <= 0;
--to/from cont
o_cont_commande <= C_NOP;
reg_o_cont_adresse <= (others => '0');
reg_o_cont_donnees <= (others => '0');
reg_o_cont_masqueEcriture <= (others => '0');
--to/from ext
reg_o_ext_donnees <= (others => '0');
o_ext_rw_ok <= "00";
elsif clk'event and clk = '1' then
case etat_suivant is
--*******************************************************************************************
-- State to manage the micron SDRAM chip and altera controller
--
-- o_cont_adresse is the bus to pass the config parameter
--*******************************************************************************************
when init_attente_stab =>
o_cont_commande <= C_NOP;
if i < 3000 then --wait 100 us, ie 30*100 clk
o_cont_commande <= C_NOP;
i <= i + 1;
etat_suivant <= init_attente_stab;
else
etat_suivant <= init_precharge;
end if;
when init_precharge =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_prechargeNop;
else
o_cont_commande <= C_init_precharge;
etat_suivant <= init_precharge;
end if;
when init_prechargeNop =>
o_cont_commande <= C_NOP;
etat_suivant <= init_load_mode;
when init_load_mode =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_load_modeNop;
else
o_cont_commande <= C_init_load_mode;
reg_o_cont_adresse <= CONF_init_load_mode;
etat_suivant <= init_load_mode;
end if;
when init_load_modeNop =>
o_cont_commande <= C_NOP;
etat_suivant <= init_load_reg2;
when init_load_reg2 =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_load_reg1;
else
o_cont_commande <= C_init_load_reg2;
reg_o_cont_adresse <= CONF_REG2;
etat_suivant <= init_load_reg2;
end if;
when init_load_reg1 =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_refresh1;
else
o_cont_commande <= C_init_load_reg1;
reg_o_cont_adresse <= CONF_REG1;
etat_suivant <= init_load_reg1;
end if;
when init_refresh1 =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_refresh2;
else
o_cont_commande <= C_REFRESH;
etat_suivant <= init_refresh1;
end if;
when init_refresh2 =>
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= init_2nop;
i <= 0;
else
o_cont_commande <= C_REFRESH;
etat_suivant <= init_refresh2;
end if;
when init_2nop =>
o_cont_commande <= C_NOP;
if i < 2 then
i <= i + 1;
etat_suivant <= init_2nop;
else
i <= 0;
etat_suivant <= etat_attente_instruction;
end if;
--*******************************************************************************
-- wait state : nothing is done until a read or write command is done
by ext.
--*******************************************************************************
when etat_attente_instruction =>
o_cont_commande <= C_NOP;
reg_o_cont_adresse <= (others => 'X');
reg_o_cont_donnees <= (others => 'X');
reg_o_cont_masqueEcriture <= (others => 'X');
o_ext_rw_ok <= "00";
-- is there a new demand ?
case i_ext_demande_rw is
when READ_MODE =>
etat_suivant <= lecture_init;
when WRITE_MODE =>
etat_suivant <= ecriture_init;
when others =>
etat_suivant <= etat_attente_instruction;
end case;
--******************************************************************************************
-- states of a burst write
--******************************************************************************************
when ecriture_init =>
compteur_ecriture <= 0;
o_cont_commande <= C_WRITEA;
o_ext_rw_ok <= "00";
--register data
reg_o_cont_adresse <= i_ext_adresse;
reg_o_cont_donnees <= i_ext_donnees;
reg_i_ext_masque <= i_ext_masque;
if i_cont_accuseCommande = '1' then
o_cont_commande <= C_NOP;
etat_suivant <= ecriture_attente_latence;
else
etat_suivant <= ecriture_init;
end if;
-- wait for the write-latency
when ecriture_attente_latence =>
o_cont_commande <= C_NOP;
if compteur_ecriture < (TL_W - 1) then
compteur_ecriture <= compteur_ecriture + 1;
o_ext_rw_ok <= "00"; --not in burst loop
etat_suivant <= ecriture_attente_latence;
else
compteur_ecriture <= 0;
etat_suivant <= ecriture_boucle_donnees;
o_ext_rw_ok <= WRITE_OK;
compteur_bl <= 1; --first burst data is wrote
end if;
-- next words of the burst message, one word per clock tick
when ecriture_boucle_donnees =>
o_cont_commande <= C_NOP;
if compteur_bl < BL then
o_ext_rw_ok <= WRITE_OK;
etat_suivant <= ecriture_boucle_donnees;
compteur_bl <= compteur_bl + 1;
else --and of burst
o_ext_rw_ok <= "00";
etat_suivant <= etat_attente_instruction;
end if;
--- end of write burst states ---
--******************************************************************************************
-- state of a read burst
--******************************************************************************************
when lecture_init =>
compteur_lecture <= 0;
o_ext_rw_ok <= "00";
reg_o_cont_adresse <= i_ext_adresse;
o_cont_commande <= C_READEA;
if i_cont_accuseCommande = '1' then --now, only TL_R ticks remain.
o_cont_commande <= C_NOP;
compteur_lecture <= 0;
etat_suivant <= lecture_attente_latence;
else
etat_suivant <= lecture_init;
end if;
-- wait for the right number of ticks
when lecture_attente_latence =>
o_cont_commande <= C_NOP;
if compteur_lecture < (TL_R-1) then
compteur_lecture <= compteur_lecture + 1;
etat_suivant <= lecture_attente_latence;
o_ext_rw_ok <= "00";
else
reg_o_ext_donnees <= i_cont_donnees;
etat_suivant <= lecture_boucle_donnees;
o_ext_rw_ok <= READ_OK;
compteur_bl <= 1; --number 0 of the burst done
end if;
-- next words of the burst, one per clock tick.
when lecture_boucle_donnees =>
if compteur_bl < BL then
reg_o_ext_donnees <= i_cont_donnees;
o_ext_rw_ok <= READ_OK;
compteur_bl <= compteur_bl + 1;
etat_suivant <= lecture_boucle_donnees;
else
o_ext_rw_ok <= READ_OK;
etat_suivant <= etat_attente_instruction;
end if;
--- end of read burst states ---
when etat_erreur => etat_suivant <= etat_erreur;
when others => etat_suivant <= etat_erreur;
end case; --end of state machine
end if;
end process;
--***********************************************************************************
-- others parallel instructions
--***********************************************************************************
--error and ready signal to ext
o_ext_sdram_ready <= '1' when etat_suivant = etat_attente_instruction
else '0';
o_ext_erreur <= '0' when etat_suivant = etat_erreur else '1';
--registered outputs
o_cont_adresse <= reg_o_cont_adresse;
o_cont_donnees <= reg_o_cont_donnees;
o_cont_masqueEcriture <= reg_o_cont_masqueEcriture;
o_ext_donnees <= reg_o_ext_donnees;
end archi;
Article: 77029Hello: OpenSoc Design has released version 0.2 of its SystemC to Verilog Synthesizable subset translator. This release includes: - Support for C++ enumerate data types - More SystemC constructions supported - Directives to support custom translation as: -//Translate off, //Translate on: To avoid translate some areas of code -//Verilog, //EndVerilog: To indicate the translator to not translate the code between the directives You can download it for free from www.opensocdesign.comArticle: 77030
1) EDK 6.3 seems to have introduced a new SW bug, if the "global pointer optimization" is checked irratic behaviour happens. This is what caused problems to Rudolf Usselman (at least I think so) 2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope service pack!! and not for Spartan II-E, but only for newer families! well good thing of course in any case AnttiArticle: 77031
Except that it's not good enough. The storage qualifier should be a clock enable for the whole unit. Otherwise, P&R can stop because it's impossible to meet the clock timing recommendations, even though it'd be OK if the qualification was done with an enable. When you select a clock for the ILA, you should also be able to select an enable to associate with that clock. The enable should connect to the CE pins of all the storage devices. You can use an AND gate for the WE on the SRLUTs, I suppose. C'mon Xilinx, FIX IT! Or release the HDL for ChipScope so we can fix it for you. Don't make me reverse engineer it! ;-) Cheers, Syms. "Antti Lukats" <avrbasic@hotmail.com> wrote in message news:34d005c8.0412201018.5e57a75a@posting.google.com... > 2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope > service pack!! and not for Spartan II-E, but only for newer families! > well good thing of course in any case > > AnttiArticle: 77032
There was a designer named Gray who spelled his name with an A He showed us a trick which counter to pick. Thank heavens for dear Mr. Gray. Happy Holidays! Peter AlfkeArticle: 77033
>1) EDK 6.3 seems to have introduced a new SW bug, if the "global >pointer optimization" is checked irratic behaviour happens. This is >what caused problems to Rudolf Usselman (at least I think so) > > > Please try SP2 when its out. This is fixed in the service pack.Article: 77034
On Mon, 20 Dec 2004 10:36:56 -0800, "Symon" <symon_brewer@hotmail.com> wrote: >Except that it's not good enough. The storage qualifier should be a clock >enable for the whole unit. Otherwise, P&R can stop because it's impossible >to meet the clock timing recommendations, even though it'd be OK if the >qualification was done with an enable. When you select a clock for the ILA, >you should also be able to select an enable to associate with that clock. >The enable should connect to the CE pins of all the storage devices. You can >use an AND gate for the WE on the SRLUTs, I suppose. C'mon Xilinx, FIX IT! >Or release the HDL for ChipScope so we can fix it for you. Don't make me >reverse engineer it! ;-) >Cheers, Syms. Yes! I agree 470%! (My approval percentages are arrived at with the same methods FPGA manufacturers use to come up with gate counts.) Bob Perlman Cambrian Design Works >"Antti Lukats" <avrbasic@hotmail.com> wrote in message >news:34d005c8.0412201018.5e57a75a@posting.google.com... >> 2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope >> service pack!! and not for Spartan II-E, but only for newer families! >> well good thing of course in any case >> >> Antti >Article: 77035
Vadim Vaynerman wrote: >Sorry about that, I missclicked... > >My question is this: is there ANY Xilinx FPGA that comes in a PLCC84 or PC84 package that is supported by the WebPck tools? I couldn't find that package for Spartan II devices, only for CPLDs, and I really want to use an FPGA. Any Ideas? > > I use the 5V XCS10PC84C. I don't know if webpack supports it. I use an old version of the Xilinx iSE tools which has support for the 5 V devices. The older Foundation software also supported these. JonArticle: 77036
Hi Brad, This looks like fun. Could you answer the following questions: 1) what type of FIFO are you using, i.e. what is it's timing? I'm running this presently on a Spartan 3 at 48Mhz. I also had a similar problem with a Cypress design. I think the issue is generic. A Xilinx COREGEN based FIFO will store data when write enable is high and the FIFO isn't full, it will put valid data only 1 clock cycle after read_enable was asserted with the FIFO not empty. 2) will the line length be stable once you start running or can it vary from line to line/frame to frame? Yes, stable. 3) you do quite some registering of your signals, so let me double check: you wan't the lines to align at the FIFO (or somewhere else) as long as the first pixel of each line is properly aligned or do you have have other latency/alignment requirements? No other reqirements. 4) Flushing of the FIFO: does the FIFO has to flush itself or can I assume continous operation (no care for the last line of data when you switch of the source)? Continuous. 5) Could you also give a bit more details on the relationships between the input signals (same frequency, aligned, same line widths of each image)? The vline comes on at the same time valid data is available at vin. This is a pretty typical sensor or image format sinario. I hope you don't mind me mailing you directly, but I have some bad experiences with spam flooding my e-mail. You can reports without any problem, just keep out anything that resembles my e-mail address. For further conversation, I'd prefer to use my personal e-mail address (see CC:). Kind regards, Alvin.Article: 77037
Antti, Antti Lukats wrote: > 1) EDK 6.3 seems to have introduced a new SW bug, if the "global > pointer optimization" is checked irratic behaviour happens. This is > what caused problems to Rudolf Usselman (at least I think so) Could you please open a case with our technical support hotline in regards to this issue and provide an example for the hotline engineer? Matt > > 2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope > service pack!! and not for Spartan II-E, but only for newer families! > well good thing of course in any case > > AnttiArticle: 77038
Kumar Vijay Mishra wrote: > Hi all, > > I am using Altera Quartus 4.0 edition, which is working fine, as far > as compilation of designs etc. is concerned. However whenever I click > on Tools --> SOPC Builder (after opening a project), it gives me the > following message in a message box: > > ------ > Error: Path to Quartus SOPC Builder installation: > > c:/program files/quartus/sopc_builder > > contains spaces, which is not permitted. You will need to install > Quartus at a location without spaces in its path. > > ---------- > > After clicking OK on message box, the SOPC template disappears and the > tool is never instaniated. > > I don't want to reinstall my Quartus edition again. If anybody has an > idea on how this error can be removed or how I can change the path of > SOPC Builder instaniation (say by putting "program files" as > "progra~1" somewhere, as we normally do in such cases), please help > asap. > > Thanx in advance. You might the following workaround, but officially we still reccomend that you install somewhere without spaces in the path. Try using DOS's subst command to map the path with spaces in it to a drive letter would work. For example: > subst Q: "C:\Program Files\My Quartus Installation With Spaces In It" Then try running Quartus/SOPC Builder from the Q: drive. Jesse Kempa Altera Corp. jkempa at altera dot comArticle: 77039
Thanks Peter, I took your advice and I attached the code below. It's for a 9 bit input, 9 bit output, 2K deep FIFO. Seems to simulate OK. > Brad, if your FIFO uses one common clock for write and read, and you > really do not care about FULL or EMPTY (because your system design > takes care of or avoids that situation), then just ignore the core > generator and simply hook two counters to the two address ports, and > declare one port the write input side, and the other one the read > output side. That means you need one slice per two address bits, and > totally exactly as many slices as your addressing is wide, i.e. 16 max. > > Most of the complexity (and trouble and frustration...) of a FIFO > design is due to the asynchronous nature of the two clocks, while > reliable EMPTY/FULL signals must be decoded. > Peter Alfke library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity fifo9 is port( clk : in std_logic; reset : in std_logic; fifowren : in std_logic; fiforden : in std_logic; fifoin : in std_logic_vector(8 downto 0); fifoout: out std_logic_vector(8 downto 0) ); end fifo9; architecture Behavioral of fifo9 is component RAMB16_S9_S9 generic ( WRITE_MODE_A : string := "READ_FIRST"; WRITE_MODE_B : string := "READ_FIRST"; INIT_A : bit_vector := X"000"; SRVAL_A : bit_vector := X"000"; INIT_B : bit_vector := X"000"; SRVAL_B : bit_vector := X"000"; INITP_00 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector(255 downto 0) := X"0000000000000000000000000000000000000000000000000000000000000000" ); port (DIA : in STD_LOGIC_VECTOR (7 downto 0); DIB : in STD_LOGIC_VECTOR (7 downto 0); DIPA : in STD_LOGIC_VECTOR (0 downto 0); DIPB : in STD_LOGIC_VECTOR (0 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (10 downto 0); DOA : out STD_LOGIC_VECTOR (7 downto 0); DOB : out STD_LOGIC_VECTOR (7 downto 0); DOPA : out STD_LOGIC_VECTOR (0 downto 0); DOPB : out STD_LOGIC_VECTOR (0 downto 0) ); end component; signal fifowraddr : std_logic_vector(10 downto 0); signal fifordaddr : std_logic_vector(10 downto 0); begin bram00 : RAMB16_S9_S9 port map ( DIA => fifoin(7 downto 0), DIB => (others=>'0'), DIPA => fifoin(8 downto 8), DIPB => (others=>'0'), ENA => '1', ENB => '1', WEA => fifowren, WEB => '0', SSRA => '0', SSRB => '0', CLKA => clk, CLKB => clk, ADDRA => fifowraddr, ADDRB => fifordaddr, DOA => open, DOB => fifoout(7 downto 0), DOPA => open, DOPB => fifoout(8 downto 8) ); fifocnt: process(clk) begin if(clk'event and clk='1') then if(reset='1') then fifowraddr<=(others=>'0'); fifordaddr<=(others=>'0'); else if(fifowren='1') then fifowraddr<=fifowraddr+1; end if; if(fiforden='1') then fifordaddr<=fifordaddr+1; end if; end if; end if; end process; end Behavioral;Article: 77040
On my system the documents are under C:\xilinx\doc\usenglish\books\docs\ and then a directory for each pdf file.Article: 77041
Before you start hand-routing a PCI connector (not to mention plugging tin-plate "fingers" into a gold socket) why not check out: http://www.getcatalyst.com/adapters.jsp The PCIPX-64 extender brings all PCI signals to .1 x .1 headers which you can plug another board on with the appropriate mates. The header to header spacing is not a multiply of .1" so you can't use standard breadboard for this, but you can design a rectangular PC board that is easy to fab at one of the cheap quick-turn places and connect to this PCI riser for about $79.00 US. Don't worry about the "keying" option (3V vs 5V) unless you're also going to use the card as an extender. Only the socket is voltage keyed, the board itself is universal. Good luck, Gabor Ben Jackson wrote: > In article <1103414414.755056.267120@f14g2000cwb.googlegroups.com>, > Shreyas Kulkarni <shyran@gmail.com> wrote: > >will a two layer PCB suffice for this purpose? > > I made (at home, even) a 2 layer PCB which worked, but it's probably not > a good idea. There are cheap board places that will make a 4 layer board > where the interior layers are limited to gnd/vcc for not that much more > than a 2 layer board. > > You can see my board at: http://ben.com/minipci/ > > >are plated through holes are necessory? any alternative? > > You will have to have vias (there are necessary signals on both sides) > but you can do it with wires if necessary (like you would at home). > > >what will be the approximate cost for a PCB with plated through holes? > > There are places you can check like expresspcb, pcbexpress (yes, they're > different), olimex. You'll probably be stuck cutting your own registration > slots, though. Not many places cut outlines with notches that small. > > >can i hand solder the PQFP/TQFP packages to the board? > > Yes, it's not hard. Use a lot of flux, tack the corner pins and then > you can 'wipe' the solder on. Use solder wick to correct bridges. > Or you can order (fairly expensive) solder paste and reflow in your > toaster oven (google it). > > >can you recommend me a good soldering gun assembly (of course low cost) > >for that purpose? > > You don't want a gun for fine work. Get a quality solder station with > a fine tip. > > -- > Ben Jackson > <ben@ben.com> > http://www.ben.com/Article: 77042
In this FIFO code, I get a design rule warning, even though I specify the
DOPA as OPEN. How come?
Thanks,
Brad Smallridge
WARNING:DesignRules:332 - Blockcheck: Dangling RAMB16A output. Pin DOPA0 of
comp
bram00 is not connected.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity fifo9 is
port(
clk : in std_logic;
reset : in std_logic;
fifowren : in std_logic;
fiforden : in std_logic;
fifoin : in std_logic_vector(8 downto 0);
fifoout: out std_logic_vector(8 downto 0)
);
end fifo9;
architecture Behavioral of fifo9 is
component RAMB16_S9_S9
generic (
WRITE_MODE_A : string := "READ_FIRST";
WRITE_MODE_B : string := "READ_FIRST";
INIT_A : bit_vector := X"000";
SRVAL_A : bit_vector := X"000";
INIT_B : bit_vector := X"000";
SRVAL_B : bit_vector := X"000";
INITP_00 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector(255 downto 0) :=
X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (DIA : in STD_LOGIC_VECTOR (7 downto 0);
DIB : in STD_LOGIC_VECTOR (7 downto 0);
DIPA : in STD_LOGIC_VECTOR (0 downto 0);
DIPB : in STD_LOGIC_VECTOR (0 downto 0);
ENA : in STD_logic;
ENB : in STD_logic;
WEA : in STD_logic;
WEB : in STD_logic;
SSRA : in STD_logic;
SSRB : in STD_logic;
CLKA : in STD_logic;
CLKB : in STD_logic;
ADDRA : in STD_LOGIC_VECTOR (10 downto 0);
ADDRB : in STD_LOGIC_VECTOR (10 downto 0);
DOA : out STD_LOGIC_VECTOR (7 downto 0);
DOB : out STD_LOGIC_VECTOR (7 downto 0);
DOPA : out STD_LOGIC_VECTOR (0 downto 0);
DOPB : out STD_LOGIC_VECTOR (0 downto 0)
);
end component;
signal fifowraddr : std_logic_vector(10 downto 0);
signal fifordaddr : std_logic_vector(10 downto 0);
begin
bram00 : RAMB16_S9_S9
port map (
DIA => fifoin(7 downto 0),
DIB => (others=>'0'),
DIPA => fifoin(8 downto 8),
DIPB => (others=>'0'),
ENA => '1',
ENB => '1',
WEA => fifowren,
WEB => '0',
SSRA => '0',
SSRB => '0',
CLKA => clk,
CLKB => clk,
ADDRA => fifowraddr,
ADDRB => fifordaddr,
DOA => open,
DOB => fifoout(7 downto 0),
DOPA => open,
DOPB => fifoout(8 downto 8)
);
fifocnt: process(clk)
begin
if(clk'event and clk='1') then
if(reset='1') then
fifowraddr<=(others=>'0');
fifordaddr<=(others=>'0');
else
if(fifowren='1') then
fifowraddr<=fifowraddr+1;
end if;
if(fiforden='1') then
fifordaddr<=fifordaddr+1;
end if;
end if;
end if;
end process;
end Behavioral;
Article: 77043Hi Marc Randolph, > > eliben@gmail.com wrote: >> Hello, >> >> We're employing FPGAs in industrial conditions >> (wide temperature range, noise). Currently we >> are using ACEX1K. Some people are reluctant to >> move to the new technologies (Stratix, Stratix II) >> because of their low core voltage. >> >> Are there are articles about the reliability of >> various FPGAs in industrial applications ? Any >> information about the lower reliability of 1.8 >> and 1.5 volt core devices ? > > A linear regulator should keep the core as clean as is needed for the > devices to operate reliably. I/O voltage(s) remain the same. > > Remember that most modern devices are not able to deal with much more > than 3.5V I/O... so if some of the industrial things you are > interfacing to are still in the 5V world, you'll have to get inventive > (opto's maybe? relays?) Altera's Cyclone devices will go to about 4.1V before cracking up. Don't know how hardy the Cyclone II devices will be though. As an aside: I did find a neat trick regarding ESD stuff about Cyclones: the built-in PLLs are a wonderful way of filtering high-frequency noise from your board clock. Just put one of the PLL's outputs in 1:1 mode. Any external noise inserted on the clock trace will of course influence the VCO in some way, but in the output of the PLL this will be visible as some amount of clock jitter, not as a whole clock spike. Of course the 4.1V constraint is in effect here too. BenArticle: 77044
Not PLL, I am looking at various types of synchronization techniques for signals crossing clock boundaries. - NeilArticle: 77045
eliben, I was waiting for all responses to trickle in before wading in. Why would any technology be less reliable? Are you concerned about the robustness of the technology to overvoltages? If this is the case, this is beyond the issue of reliability, it is an issue of not liking the absolute maximum ratings, which have gotten lower as the technolgy shrinks. Again, this has nothing to do with reliability. If you apply 1000V to a 110V light bulb, it will blow out. Is it less reliable? No, it is not. If you can not prevent voltage surges inside your environment, then you should be using 4000 series 15V CMOS (or better yet, tubes). If you can prevent voltage surges, then you are free to use any technology you choose to. 90 nm Spartan 3 and Virtex 4 have the same predicted operating life as 220 nm Virtex or Spartan 2. How is this possible? Well, it is easy: we design to meet a desired life, and we do not do anything that would cause the device to have a shorter lifetime. Foundry rules. As for comments on ramp on power supply rates, etc. these all have nothing to do with your basic question, and also have nothing to do with reliability. As for power supply design, consult National, TI, Bellnix, Linear Tech, Intersil: http://www.xilinx.com/products/design_resources/power_central/index.htm Take your choice, and all of these suplliers have pre-engineered solutions for you that Xilinx has already validated. One more comment, new (since Virtex II) FPGAs (from Xilinx) have no power on SURGE behavior on the core supplies. Older Xilinx products had small surge levels (~ a few amperes worst case in the 4K and early Virtex and Virtex E days). Some 130 and 90 nm FPGAs (from other vendors) have LARGE SURGES and also LARGE LEAKAGE currents which necessitates careful power supply design (and lots of power). And it isn't just the core supply either. Note the start up power on the other supplies as well (might need to consult the vendor's spreadsheet tools on their websites). http://focus.ti.com/lit/ml/slyb113/slyb113.pdf See page 3: "Stratix II FPGA Power Requirements1 VCCINT (core voltage) 1.15 V min, 1.2 V typ, 1.25 V max ICCINT (core current) EP2S15: 4 A max Inrush to start-up included EP2S30: 6 A max EP2S60: 7 A max EP2S90: 9 A max EP2S130: 12 A max EP2S180: 16 A max" Please read my old (now) tech note on the subject: http://tinyurl.com/6rksg AustinArticle: 77046
I use a Cyclone on a gate drive for a high power IGBT - a VERY noisy environment. The precautions I took were : - Convert I/O to/from 5v directly adjacent to the device. The higher voltage signals then proceed around the PCB - Around the FPGA itself, create multiple ground/power planes - including one on an external layer to serve as a shield - Make provision for additional shielding (i.e. copper planes mounted above the FPGA sub-system) - didn't use this in the end. - Use an accurate linear reg. and set the internal voltage at the upper end of the tolerance I don't know which of these were important, but the device has performed like a champ I do have a concern concerning longevity (often much more important in industrial stuff than commercial). This is to do with the stability of the sub-micron geometries used in devices such as this. To alleviate these concerns, I make sure it runs really cool. I don't know if anyone else can comment on this concern. Gary <eliben@gmail.com> wrote in message news:1103526760.055590.264630@z14g2000cwz.googlegroups.com... > Hello, > > We're employing FPGAs in industrial conditions > (wide temperature range, noise). Currently we > are using ACEX1K. Some people are reluctant to > move to the new technologies (Stratix, Stratix II) > because of their low core voltage. > > Are there are articles about the reliability of > various FPGAs in industrial applications ? Any > information about the lower reliability of 1.8 > and 1.5 volt core devices ? > > Tx >Article: 77047
As I understand it (!) Stephen Trimberger (Xilinx and much distinguished previous work) presented a paper recently on this fairly recently. "Symon" <symon_brewer@hotmail.com> wrote in message news:31qgosF3cc0s9U1@individual.net... > Hmm, that's very interesting. I wonder if the FPGA vendors have got their > SLICEs back to front? I.e. the FFs should feed directly into the LUTs within > the SLICEs, instead of the other way round that exists now. If it saved even > 20% of the power, it'd be worth it. Instead of using all the FFs for > pipelining, you use them to replicate signals within the SLICEs to prevent the > glitchy power thing. Hmm, interesting indeed! Thanks Ray. > Cheers, Syms.Article: 77048
Symon wrote: > Hmm, that's very interesting. I wonder if the FPGA vendors have got their > SLICEs back to front? I.e. the FFs should feed directly into the LUTs within > the SLICEs, instead of the other way round that exists now. If it saved even > 20% of the power, it'd be worth it. Instead of using all the FFs for > pipelining, you use them to replicate signals within the SLICEs to prevent > the glitchy power thing. Hmm, interesting indeed! Thanks Ray. You mean put four FF's on the LUT inputs, instead of one on the output? I suppose that reduces glitching inside the LUT (RAM), but it still leaves glitches through the routing. Also, four FF's are likely to take more power than one. -- glenArticle: 77049
Hi Jesse, Thankyou for the tip. It did work. KVM.
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