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Leon Heller wrote: > "vax, 9000" <vax9000@gmail.com> wrote in message > news:cq9kds$334$1@charm.magnus.acs.ohio-state.edu... >> Hi, group, >> I am looking for one piece of low cost alterma MAX II (EPM1270) >> development kit. What I need is basically the chip mounted on a small >> board >> with JTAG pins and almost all I/O pins available. The $150 Altera kit >> provides only some 40+ I/O pins, with many features that I don't need. >> Does >> such a kit exist? I'd expect lower cost than $150. $80(with shipping) is >> OK, $50 is prefered. If you know of this product, please let me know. > > I'll design and make you one for $80, if you can supply me with a couple The $80 was supposed to include the chip... Is it feasible for us to find enough people who want the chip too, to split the tray and the cost? I need only one or two. It might be OK for somebody to buy a tray, then sell the rest 89 pieces on ebay. I called a local supplier today but they said they didn't have the chip (though their website said they had). I searched through www.findchips.com to find them. vax, 9000 > of the chips (one for me and one for you). They are only available by the > tray (90 pcs), AFAIK. > > LeonArticle: 77076
The devil in all of the cost is the download cable. Often the download cable costs as much as the original kit price. So either you also need to build your own download cable or you are better off buying a development board that exceeds your needs. Cheers, Jim > "vax, 9000" <vax9000@gmail.com> wrote in message > news:cq9kds$334$1@charm.magnus.acs.ohio-state.edu... > >>Hi, group, >> I am looking for one piece of low cost alterma MAX II (EPM1270) >>development kit. What I need is basically the chip mounted on a small >>board >>with JTAG pins and almost all I/O pins available. The $150 Altera kit >>provides only some 40+ I/O pins, with many features that I don't need. >>Does >>such a kit exist? I'd expect lower cost than $150. $80(with shipping) is >>OK, $50 is prefered. If you know of this product, please let me know. > > > I'll design and make you one for $80, if you can supply me with a couple of > the chips (one for me and one for you). They are only available by the tray > (90 pcs), AFAIK. > > Leon > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 77077
David Colson wrote: (snip) > Thanks for the info. Now I fell better. We are using Spartan II, IIe and > IIIs in out brusless motor drives. Which have large voltage and current > swings up to 340 volts and 18 amps, and only inches away form the FPGA! Consider timers like: http://www.intermatic.com/?action=subcat&sid=112 Well, likely not FPGAs but I believe they are digital electronic devices with memory. Most of these not only have to switch loads like 120V and 4A, incandescent or some fluorescent, they are powered by such current. (One can switch 15A 277VAC, though it has help from a battery.) At least one, and I believe all, are series connected with the load being controlled. When the switch is off, the have 120V AC power. When on, less than 1V at 300mA or more. Some have a battery for backup, but not all do. -- glenArticle: 77078
"vax, 9000" <vax9000@gmail.com> wrote in message news:cqa64a$4h4$1@charm.magnus.acs.ohio-state.edu... > Leon Heller wrote: > >> "vax, 9000" <vax9000@gmail.com> wrote in message >> news:cq9kds$334$1@charm.magnus.acs.ohio-state.edu... >>> Hi, group, >>> I am looking for one piece of low cost alterma MAX II (EPM1270) >>> development kit. What I need is basically the chip mounted on a small >>> board >>> with JTAG pins and almost all I/O pins available. The $150 Altera kit >>> provides only some 40+ I/O pins, with many features that I don't need. >>> Does >>> such a kit exist? I'd expect lower cost than $150. $80(with shipping) is >>> OK, $50 is prefered. If you know of this product, please let me know. >> >> I'll design and make you one for $80, if you can supply me with a couple > > The $80 was supposed to include the chip... > Is it feasible for us to find enough people who want the chip too, to > split > the tray and the cost? I need only one or two. It might be OK for somebody > to buy a tray, then sell the rest 89 pieces on ebay. I called a local > supplier today but they said they didn't have the chip (though their > website said they had). > I searched through www.findchips.com to find them. I have a supplier who can provide small quantities of Altera parts, but I'd have to order about 100 GBP worth, about $200 with shipping and tax. LeonArticle: 77079
Eric, "Large" is not in S3 vocabulary. They (Spartan) have no "large" devices.....by definition. If it is "large" then it belongs to the Virtex family.....also by definition. That said, the 3S5000 is a pretty "large" part, but still a lot smaller than the XCV4LX200 (largest V4 basic logic device). S3 also has no start up surge. Yes. Triple oxide is not required in order to control the surge, but it doesn't hurt (offers even more options to the designers). V2, V2Pro, and S3 are all dual oxide, and they all have no surge. Austin Eric Smith wrote: > Austin Lesea <austin@xilinx.com> writes: > >>That is why we are quite happy with the advantages we gained from the >>triple oxide technology in V4: half to 1/3 the leakage of other large >>90nm FPGAs, > > > The "other large 90mm FPGAs" being Spartan 3? > > >>and no start up surges. > > > I thought Spartan 3 already had that? If so, how is it a feature > of "triple oxide technology"?Article: 77080
David, You must still beware of induced magnetic fields (which can not be enitrely shielded by any means). A 1 turn transformer from your motor to the wiring of the pcb may be an issue. Be sure to have someone look at how much induced voltage there is in the loops present in your PCB from the motor fields. If the magnetic field can be held at 90 degrees to the PCB loops, then it will not be an issue (no transfomer effect). Austin David Colson wrote: > Austin Lesea wrote: > >> David, >> >> This issue is at least as old as the static configuration latches that >> are used to hold the configuration: >> >> what will cause config bits to change? >> >> In order to make FPGAs work (at all), one has to start with a very >> robust memory cell design. NOT SRAM! >> >> We use specially engineered (for the myriad of requirements we have) >> cross coupled CMOS latches. >> >> They can be slow. >> >> They can be heavily loaded (the more loads the better). >> >> They must run at the highest internal voltage we have to be used to >> control the pass gates (also good for stability). >> >> They must be immune to read disturb (as we can readback while operating). >> >> They must be easy to write. >> >> They must be very low leakage. >> >> They must meet our SEU (soft error upset) reliability criteria. >> >> If the power supply itself glitches, the POR (power on reset) circuit >> uses dummy memory cells to detect if they can be upset (selected sizes >> of loads to mimic the most sensitive memory cell). So, if there is >> enough of a power supply glitch to flip a memory cell used for >> configuration, the POR will trip, and the device will reconfigure (as >> it lost it memory from the glitch). >> >> How else can you flip those bits? >> >> 1) Place in nuclear reactor >> 2) Inject massive amounts of current into the substrate by excessive >> undershoot (as in many many amperes from a bunch of IOs switching at >> once -- exceeds the Latch up spec, but no latch up will occur, just >> de-programming) >> 3) exceeding the absolute maximum specifications in other ways we >> haven't dreamed of (yet) >> >> Austin > > Thanks for the info. Now I fell better. We are using Spartan II, IIe and > IIIs in out brusless motor drives. Which have large voltage and current > swings up to 340 volts and 18 amps, and only inches away form the FPGA! > > > Dave ColsonArticle: 77081
>> I had to add large capacitors to the LDO
>> regulator outputs in order to meet the minimum ramp rates.
>>
>Hmm, nasty. Next time you may want to consider using a simple RC network in
>the feedback path to limit the ramp rate.
That seems fishy. Won't that also screw up the transient response
when you are running normally?
Cheaper, smaller and without
>enormous amounts of current being dumped from the supply into your monster
>output capacitors. Most modern switching circuits (I use the easy to use
>LTC3414) have 'soft start' modes which limit turn on current.
>Cheers, Syms.
Soft start is good. They aren't common on the low cost switching
chips I've been looking at recently.
LTC3414 looks good. (But that's only from a quick glance at the
data sheet.)
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Article: 77082Shreyas, I certainly agree with Ben Jackson's comments. My 2 layer PCI target card is at the bottom of www.ece.pdx.edu/~steenl. I think I went through 4pcb.com. Plated holes are standard in all the places I know of. There is a via-rivet that allows you to make via connections on non-plated boards, but I have no experience with that. A tech soldered the PQFP, and I used a soldering iron for the voltage regulators and caps. You can see the difference in quality from the picture. Good luck, -Steen Shreyas Kulkarni wrote: > Hi there, > > currently i have been working on a project involving developement of a > simple PCI target for data acquisition. all that i want is a "simple" > target device that will get detected and will work properly as a > target, i.e. cause data transfer from the PCI card to the PC when > requested. i need to keep the cost at bare minimum. i cannot use the > readymade kits/cards like the one from PLX. i m going to use spartan2 > fpga. again i m pretty an inexperienced person in this regard. hence i > have some doubts regarding the PCB developement that i will have to > undertake - > > will a two layer PCB suffice for this purpose? > > are plated through holes are necessory? any alternative? > > what will be the approximate cost for a PCB with plated through holes? > > can i hand solder the PQFP/TQFP packages to the board? > > any extra precautions to take while doind that? > > can you recommend me a good soldering gun assembly (of course low cost) > for that purpose? > > > any suggestions, recommendations regarding further references, books > that i should read for this kind of PCB developement, softwares that > can be useful, tools of the trade, and any other thing that may be > useful, will be greately appreciated; as they are you people whom i m > banking on for guidance, in this critical project. Seriously. > TIA, > Shreyas KulkarniArticle: 77083
Vasanth Asokan wrote: > >>1) EDK 6.3 seems to have introduced a new SW bug, if the "global >>pointer optimization" is checked irratic behaviour happens. This is >>what caused problems to Rudolf Usselman (at least I think so) >> > > Please try SP2 when its out. This is fixed in the service pack. Actually I think I use SP2 (EDK 6.3.1) and am still having the problem. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 77084
Altium have just released SP2 for Protel/Nexar. It can be downloaded from http://www.altium.com/downloads/2004SP2/ It includes more than 150 new features and enhancments such as the new TSK3000A 32-bit RISC Processor complete with Build Tools, and Verilog Support just to name some. Upgrade for board-level design system : http://www.ferret.com.au/articles/fc/0c029ffc.asp Protel 2004 Supercharged with over 150 New Features : http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20041216005547&newsLang=en New and Enhanced Features : http://www.altium.com/downloads/2004sp2/New_and_Enhanced_Features_in_SP2.pdfArticle: 77085
Leon Heller wrote: > > I have a supplier who can provide small quantities of Altera parts, but > I'd have to order about 100 GBP worth, about $200 with shipping and tax. Would you please quote the price for EPM1270? $200 could buy less than 10 pieces, I guess. So you (we) will have no problem to find enough people to split the cost. The problem might be the shipping from the UK to the US. vax, 9000 > > LeonArticle: 77086
Jim Lewis wrote: > The devil in all of the cost is the download cable. > Often the download cable costs as much as the > original kit price. So either you also need to build > your own download cable or you are better off buying > a development board that exceeds your needs. A download cable might not be too difficult to make. I made a xilinx cable and it worked fine. vax, 9000 > > Cheers, > JimArticle: 77087
Hi Symon, > > Hmm, that's very interesting. I wonder if the FPGA vendors have got their > > SLICEs back to front? I.e. the FFs should feed directly into the LUTs within > > the SLICEs, instead of the other way round that exists now. If it saved even > > 20% of the power, it'd be worth it. Instead of using all the FFs for > > pipelining, you use them to replicate signals within the SLICEs to prevent the > > glitchy power thing. Hmm, interesting indeed! Thanks Ray. You'd have to consider the cost of having 4 flops (if I understand correctly) vs. 1. How often will 4 flops be used? What if you instead spent that same silicon area on other things (other power reduction circuitry, etc.)? How much more wiring cap will there be due to increased size of a LE? How much more power are you burning by replicating clocks and other signals? One thing I should point is that you *can* put FF in front of the LUT in Stratix/Cyclone/Max II/Cyclone II/Stratix II. There is only one FF, but it can directly feed the LUT instead of the other way around. Regards, Paul Leventis Altera Corp.Article: 77088
Hi Jesse...... Ur tip did help me to start the SOPC builder. Since I am new to SOPC builder and Nios, I tried to follow the Nios HW tutorial. Everything went well. However, at the end SOPC Builder couldn't generate the system and gave errors. This despite my following the tutorial word-by-word. Is it related to the installation in a folder name with spaces. KVM.Article: 77089
> And it isn't just the core supply either. Note the start up power on > the other supplies as well (might need to consult the vendor's > spreadsheet tools on their websites). > > http://focus.ti.com/lit/ml/slyb113/slyb113.pdf The ICC values listed for Stratix II in the TI reference guide above are out-of-date. Altera has requested that TI update this document. EP2S180 users can expect from 1.8A to 5.3A of ICCint current during FPGA power-up, depending on the temperature and the silicon characteristics (typical vs. the process corner that leads to maximum power). Given the high-density and high-performance of the 2S180, these values are below the operating current for the vast majority of customers. While other FPGA vendors only specify values for typical silicon at 25C, Altera provides start-up currents and operating power values at various temperatures and for both typical and worst-case power process corners. For a power estimate specific to your design, use the PowerPlay Early Power Estimator, available at http://www.altera.com/support/devices/estimator/st2-estimator/st2-power-esti mator.html. If you have a completed design, you can use the Power Analyzer built into Quartus for even more accurate answers. See http://www.altera.com/literature/hb/qts/qts_qii53013.pdf for details. Vaughn Altera v b e t z (at) altera.com [Remove spaces and insert proper @ to reach me]Article: 77090
On Tue, 21 Dec 2004 18:36:06 -0600, hmurray@suespammers.org (Hal Murray) wrote: >>> I had to add large capacitors to the LDO >>> regulator outputs in order to meet the minimum ramp rates. >>> >>Hmm, nasty. Next time you may want to consider using a simple RC network in >>the feedback path to limit the ramp rate. > >That seems fishy. Won't that also screw up the transient response >when you are running normally? It's possible to add a diode or two so that the large scale ramp during turn on is slowed down, but the small scale perturbations (less than a diode drop) aren't affected. These days it's better to get one with built in soft start. A lot of linear regs have 'ref' pins, which can be used to slow the rise time without affecting the closed loop response. Regards, AllanArticle: 77091
"vax, 9000" <vax9000@gmail.com> wrote in message news:cqar8l$5u0$2@charm.magnus.acs.ohio-state.edu... > Jim Lewis wrote: > >> The devil in all of the cost is the download cable. >> Often the download cable costs as much as the >> original kit price. So either you also need to build >> your own download cable or you are better off buying >> a development board that exceeds your needs. > A download cable might not be too difficult to make. I made a xilinx cable > and it worked fine. I've got the artwork for one on my web site: http://www.geocities.com/leon_heller/blaster.zip I also sell a surface mount version: http://www.leonheller.com/ LeonArticle: 77092
JTW wrote: > If I have two or more sections of logic in my FPGA that need to read and write > to the same memory, what is the typical/standard approach to control who > writes/reads when? Is there an example somewhere that I > could look at? > Thanks, JTW It's a problem more general than just memory, ie. you could be sharing other devices. For the most general case you need some kind of interconnect structure and arbitration, like for example Avalon (offered by Altera) or WISHBONE (notably used by OpenCores, though I couldn't seem find a bus arbiter). Often however, you can use system specific knowledge to adopt a simpler solution, such as running the memory at twice the speed, using odd cycles for one device, and even for the other (rarely works for external memory though). TommyArticle: 77093
I forgot to mention it's a Xilinx Virtex2-Pro device ... RanArticle: 77094
I'm not really sure what I want to do with them - if anything. However, if I do need to use them what do I do ?? I see that the DSCNTL register can be used to set up clock ratios when the PPC and BRAM are being clocked at different speeds. If I need to do this how will I set this reg up if I cant see it ??? "Andi" <00andi@web.de> wrote in message news:ee8ac21.0@webx.sUN8CHnE... > You can connect the on port of the BRAM to the DSOCM interface of the ppc. That enables you to direcly read and write to the BRAM on one port. On the other port you can connect the BRAM to any other stuff µC or VHDL-process. I did not use the DCR registers. What do you plan to do with them?Article: 77095
question asked to arm on 22/12/2004 ----------------------------------- my questions are: 1) when the master on AHB bus is getting ready signal low from slave then is there any way the master start a new transaction on the bus. Also if slave give the error response after some predefined number of cycle to release the bus then is it a correct approach or is there any better approach to release the master and bus to do other operation. 2) when the slave give retry response to master then is it possible for the bus master to start a new transaction on the bus for same or different slave. Is it that the particular master is blocked on getting retry responseArticle: 77096
ran wrote: > I am trying to use the chipscope pro version 6.3 (tried also 6.2 but > results were the same). While mapping the design, I get the following > error messages: > > The structured logic could not be placed in the relative placement form required. > This is due to the fact that the component > i_ila/ila/i_no_d/u_ila/u_trig/u_tm/g_nmu/1/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_ > tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O is already contained in an rpm that will not > allow the logic to be placed in the legal form. > [...] > This situation can be resolved by fixing the following issue: > [...] > Pl_Group:: Id=3273 numComps=3 locked=FALSE active=FALSE > level=0 > > clientId=0 > > Comp = fifo_over_under_flow type = LUT numpins = 14 > > Comp = fifo_over_under_flow type = LUT numpins = 0 > > Comp = fifo_over_under_flow type = FF numpins = 0 > > ..................................... > > ERROR:Place:379 - Unable to place the following group for unknown > reason > > LUT i_ila/i_no_d/u_ila/idata_24 (0, 0) > > FF i_ila/i_no_d/u_ila/idata_24 (0, 1) > > ERROR:Place:379 - Unable to place the following group for unknown > reason > > LUT i_ila/i_no_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/cfg_data_4 > (0, 0) > > FF i_ila/i_no_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/cfg_data_4 > (0, 1) > > ERROR:Place:120 - There were not enough sites to place all selected > components [...] > ERROR:Pack:1499 - The timing-driven packing phase encountered an error. > [...] > > After which the mapper failes. If I remove the "-timing" option of > the MAP, the mapper succeeds but the PAR failes (unrouted signals). > Any suggestions ? Howdy Ran, Three things come to mind when looking over this log: 1. Is the device over-full? When you run with -timing, what is the LUT and FF utilization? 2. Is the RPM for the ILA/ICON core too tall for the device you are targetting? Any idea how tall your core is? You mentioned you were targetting a V2Pro, but which one? 3. I don't recall - for the ILA/ICON core, are you forced to use RPM's? I'm thinking you are, but if not, maybe try without? Good luck, MarcArticle: 77097
Austin Lesea wrote: > David, > > You must still beware of induced magnetic fields (which can not be > enitrely shielded by any means). > > A 1 turn transformer from your motor to the wiring of the pcb may be an > issue. > > Be sure to have someone look at how much induced voltage there is in the > loops present in your PCB from the motor fields. > > If the magnetic field can be held at 90 degrees to the PCB loops, then > it will not be an issue (no transfomer effect). > > Austin > > David Colson wrote: > >> Austin Lesea wrote: >> >>> David, >>> >>> This issue is at least as old as the static configuration latches >>> that are used to hold the configuration: >>> >>> what will cause config bits to change? >>> >>> In order to make FPGAs work (at all), one has to start with a very >>> robust memory cell design. NOT SRAM! >>> >>> We use specially engineered (for the myriad of requirements we have) >>> cross coupled CMOS latches. >>> >>> They can be slow. >>> >>> They can be heavily loaded (the more loads the better). >>> >>> They must run at the highest internal voltage we have to be used to >>> control the pass gates (also good for stability). >>> >>> They must be immune to read disturb (as we can readback while >>> operating). >>> >>> They must be easy to write. >>> >>> They must be very low leakage. >>> >>> They must meet our SEU (soft error upset) reliability criteria. >>> >>> If the power supply itself glitches, the POR (power on reset) circuit >>> uses dummy memory cells to detect if they can be upset (selected >>> sizes of loads to mimic the most sensitive memory cell). So, if >>> there is enough of a power supply glitch to flip a memory cell used >>> for configuration, the POR will trip, and the device will reconfigure >>> (as it lost it memory from the glitch). >>> >>> How else can you flip those bits? >>> >>> 1) Place in nuclear reactor >>> 2) Inject massive amounts of current into the substrate by excessive >>> undershoot (as in many many amperes from a bunch of IOs switching at >>> once -- exceeds the Latch up spec, but no latch up will occur, just >>> de-programming) >>> 3) exceeding the absolute maximum specifications in other ways we >>> haven't dreamed of (yet) >>> >>> Austin >> >> >> Thanks for the info. Now I fell better. We are using Spartan II, IIe >> and IIIs in out brusless motor drives. Which have large voltage and >> current swings up to 340 volts and 18 amps, and only inches away form >> the FPGA! >> >> >> Dave Colson Austin, No need to worry. The boys here have been designing drives since the early 80s. Most are MIT grads. Also we set up motors and drives and run them fairly hard and continuously for months. Dave ColsonArticle: 77098
"vax, 9000" <vax9000@gmail.com> wrote in message news:cqar69$5u0$1@charm.magnus.acs.ohio-state.edu... > Leon Heller wrote: > >> >> I have a supplier who can provide small quantities of Altera parts, but >> I'd have to order about 100 GBP worth, about $200 with shipping and tax. > Would you please quote the price for EPM1270? $200 could buy less than 10 > pieces, I guess. So you (we) will have no problem to find enough people to > split the cost. The problem might be the shipping from the UK to the US. I've just been quoted £20.67 ($39.57) each for 25 pcs of EPM1270T144C5ES! With VAT and carriage the total will be about $1200. I don't think it is viable. LeonArticle: 77099
Vaughn, Only 5.3 amperes surge? How do you test for it? Can you guarantee it? Do you throw away the ones that don't pass? Why was the initial surge set at 20 amperes, and then dropped to 16 amperes, and now down to 5.3 amperes for the 180? Did you fix the silicon, or figure out how to control the turn on of the power supplies, or measure it, and get a more agreeable number? Too bad, though. The LX200 is 3.3 amperes, worst case - leakage only, at 85C. Typical is 1.3 amperes at 85C. No start up surge to worry about. And the LX200 is a lot more memory, LUTs and FFs than the EP2S180... Why is it so much worse than Stratix 1? (both surge and leakage) Is Cyclone 2 just as bad as S2? Austin Vaughn Betz wrote: >>And it isn't just the core supply either. Note the start up power on >>the other supplies as well (might need to consult the vendor's >>spreadsheet tools on their websites). >> >>http://focus.ti.com/lit/ml/slyb113/slyb113.pdf > > > The ICC values listed for Stratix II in the TI reference guide above are > out-of-date. Altera has requested that TI update this document. > > EP2S180 users can expect from 1.8A to 5.3A of ICCint current during FPGA > power-up, depending on the temperature and the silicon characteristics > (typical vs. the process corner that leads to maximum power). Given the > high-density and high-performance of the 2S180, these values are below the > operating current for the vast majority of customers. > > While other FPGA vendors only specify values for typical silicon at 25C, > Altera provides start-up currents and operating power values at various > temperatures and for both typical and worst-case power process corners. > > For a power estimate specific to your design, use the PowerPlay Early Power > Estimator, available at > http://www.altera.com/support/devices/estimator/st2-estimator/st2-power-esti > mator.html. If you have a completed design, you can use the Power Analyzer > built into Quartus for even more accurate answers. See > http://www.altera.com/literature/hb/qts/qts_qii53013.pdf for details. > > Vaughn > Altera > v b e t z (at) altera.com [Remove spaces and insert proper @ to reach me] > > > >
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