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hi ng,
i get the following error-message during "Programming File Generation":
ERROR:Bitgen:145 - Pin M6 is a persistent pin, but a component exists in
it's
IOB. Please rerun par with the persistent pins prohibited from use.
ERROR:Bitgen:157 - Bitgen will terminate because of the above errors.
Error: bitgen failed
Reason:
Process "Programming File Generation Report" did not complete.
Here is the evil code fragment:
pIR : process (CLK, Reset)
begin
if Reset = '0' then
Pending <= '0';
elsif CLK'event and CLK = '1' then
if IRQ = '1' then
Pending <= '1';
elsif Clear = '1' then -- when i remove "elsif-clause" it
generates the bitstream without an error
Pending <= '0'; -- (synthesizing without errors with AND
without the "elsif-clause")
end if;
end if;
end process;
Anyone have an idea? We have ISE 6.2.03 (and currently only Spartan3) here
and i don't use an ucf-file
which assigns Pin M6 to the design. An i can't find this PAR Option in the
PAR-Contextmenu (even not in advanced mode). The Rest of the module is only
the entity-declaration, so it's not possible that the design gets too big
with this "elsif-clause".
thanks,
Stefan
Article: 77301Hi, For the system level functional verification, I need to initialize several BlockRAMs. From a setup with the ALdec Simulator there are existing *.mif files. In the online help form ModelSim describes the initialization procedure for Memory contents. But I can't found the array of the BlockRAM in my Workspace (the pipeline and the address counter registers are visible). Has anyone some experience with this initialization procedure? Regards, DavidArticle: 77302
Ulf Samuelsson <ulf@atmel.nospam.com> wrote: > > > And for just configuring - have a look at the FTDI chips and bit-bang > > > app-notes: > > > http://www.ftdichip.com > > > > > > The FT2232 has a dedicated serial engine to generate JTAG/SPI/I2C. However > I > > have not seen an open project for JTASG interface to use this chip. > > > If someone cares to do something... > The AT91SAM7S64 is nice for the job. > * USB Client > * ARM7 running at 48 MHz (will not handle 70'C at this temp though) > * Built in Flash and SRAM > * High speed synch interface for JTAG Master > This should be MUCH MUCH fatser than bitbanging. > There is of course the small matter of programming... Looks nice, but: - Digi has no chips on stock, and the other usual suspects don't have that chips at all... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 77303
Hi Swapnajit, Thank you so much for the inputs. You got it correctly i.e. I want only the last step of merge-sort. For sorting I am using parallel VHDL implementation of Insertion Sort for my application (I know it consumes lot of LEs on my FPGA, but I found it quite suitable for my application). In each clock cycle, I am required to sort two sequences (for which insertion sort suits best). I get the sorted sequences in the next clock cycle. I would like to merge these two sorted sequences now. And I do have a latency of one more clock cycle. So I want a similar implementation of merge-sort also, wherein single sorted sequence should be obtained in the next clock cyle itself. However I doubt if the hypercube implementation will help here. Ya, the compare-exchange method seems to be of some use in this case. vizziee.Article: 77304
Stefan Oedenkoven wrote: > hi ng, > i get the following error-message during "Programming File Generation": > > ERROR:Bitgen:145 - Pin M6 is a persistent pin, but a component exists in > it's IOB. Please rerun par with the persistent pins prohibited from use. > ERROR:Bitgen:157 - Bitgen will terminate because of the above errors. > Error: bitgen failed > Reason: > Process "Programming File Generation Report" did not complete. [...] > Anyone have an idea? We have ISE 6.2.03 (and currently only Spartan3) here > and i don't use an ucf-file > which assigns Pin M6 to the design. An i can't find this PAR Option in the > PAR-Contextmenu (even not in advanced mode). The Rest of the module is only > the entity-declaration, so it's not possible that the design gets too big > with this "elsif-clause". Howdy Stefan, Looks like this has been a problem in the past: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18837 >From the write-up, it appears the problem is caused by the persist option being set in BITGEN rather than PAR. Good luck, MarcArticle: 77305
Hi, How can I initialize the Xilinx BlockRAMs without changing the Cores in the CoreGenerator? The solution suggested by ModelSim does not work because the Memory array is not visible in the Workspace. Does anyone have solved the same problem before? Thanks for your suggestions. Regards, DavidArticle: 77306
David wrote:
> For the system level functional verification, I need to initialize
> several BlockRAMs. From a setup with the ALdec Simulator there are
> existing *.mif files. In the online help form ModelSim describes the
> initialization procedure for Memory contents. But I can't found the
> array of the BlockRAM in my Workspace (the pipeline and the address
> counter registers are visible).
For functional verification, consider using
a testbench process to write the blockrams
from an array of vector constants declared
in the testbench.
-- Mike Treseler
Article: 77307hi all, i have buy a development board spartan-3 fga based. http://www.silica.com/en/products/evaluationkits/SP3%20Development%20kit.html i heve read from a little time the LEON2 CORE. I have a question: Which thing you me councils for this board? uclinux on microblaze or LEON2 on uclinux? what different between LEON2 and microblaze? thanks lots. Regards R!SCArticle: 77308
Please take a look at: http://thankpoland.info/ for the latest news viz-a-vis "software patents in EU". (Related information on the sites http://www.nosoftwarepatents.com/ and http://ffii.org/ ). Questions: How much of this applies to FPGA-design? Is there any danger that here also this field would be mined with a lots of silly patents? Has that already happened in USA? Am I right that especially the Open Cores movement would be particularly vulnerable to that kind of "development" with regards to patent (silly or not) infringement lawsuits? I guess this is not so much problem for design houses using their own cores whose HDL- and other design-files are kept as undisclosed trade secrets. What has been and what WILL be the view of patent organizations on HDL-designs? (E.g. if the amendments proposed by FFII and related folks get some day through in the EU legislative process). I.e. is a Verilog or VHDL-source file just "a description for hardware device" or is it yet another (strange) form of software? Yours, Antti KarttunenArticle: 77309
There are low cost LDOs that are much better than the LM317. Most notably less voltage drop. Keep in mind that you need to get rid of all the heat that comes with a large voltage drop. Also note that you can use an LDO with 1.25V reference voltage (for example the lm1086) without any ressitors to power a spartan-3. Kolja Sulimma Eric Smith wrote: > Is there any reason why using an LM317S adjustable linear regulator with > 1% resistors wouldn't be satisfactory for the Spartan 3 power supplies, > particularly Vccint and Vccaux? > > I have a cost-sensitive application for which the LM317S looks to be > much less expensive than using fixed-output LDO regulators, e.g., > $0.58 for the LM317S vs. $4.45 for an LP3881ES-1.2 for Vccint. > > Thanks for any advice! > EricArticle: 77310
Antti Karttunen (remove .fo from the address) wrote: >Please take a look at: >http://thankpoland.info/ >for the latest news viz-a-vis >"software patents in EU". >(Related information on the sites >http://www.nosoftwarepatents.com/ >and http://ffii.org/ ). > How much of this applies to FPGA-design? Most of the software patent discussion does not apply to FPGA design because fpga designs are clearly covered by existing patent law. However algorithm patents could hurt in some places. (Thin Bresenham, think CORDIC) > Is there any danger that here also this field > would be mined with a lots of silly patents? Rememeber that a sigma/delta ADC is made from a DAC and a comparator? Austin Lesea has a patent on the idea that you could use the differential inputs of the fpga as the comparator. Xilinx also has an patent on implementing an 8-input AND in a single CLB. Hopefully your Microblaze clone does not use this feature, they could use that patent to come after you. (Peter Alfke stated in this newgroup that they wouldn't) Also, Xilinx has illegal european software patents since 1997: Patent EP000000951687B1 [EN] PROGRAMMABLE LOGIC DEVICE PLACEMENT METHOD UTILIZING WEIGHTING FUNCTION TO FACILITATE PIN LOCKING But the European Council still claims that software is not patentable in europe. > Has that already happened in USA? Yes. > Am I right that especially the Open Cores movement > would be particularly vulnerable to > that kind of "development" with regards > to patent (silly or not) infringement lawsuits? It is easier to identify patent infringing in open source software, but the damage is usually at least as large for small and medium sized companies. Only the large companies are safe because they achive a balance of power with patent exchange agreements. > What has been and what WILL be the view > of patent organizations on HDL-designs? > (E.g. if the amendments proposed by > FFII and related folks get some day > through in the EU legislative process). Well, they are proposed by the parliamt. It the council that ignored them. > I.e. is a Verilog or VHDL-source file just > "a description for hardware device" > or is it yet another (strange) form of software? The VHDL source is not patentable. It is covered by copyright. That is something entirely different and completely unrelated. Patents cover the ideas of the design. Ideas how to build a circuit are clearely patentable in europe, no matter if you use HDL, schematics or a mask layout program to describe the circuit. (Example: 8-input and-gate in a single CLB) Algorithms as such are currently officially not patentable int the EU, no matter if you use a uC, FPGA or specialized VLSI to implement it (Example:Bresenham Algorithm) The patent layers try to sneak through this by filing patents of the form "Bresenham algorithm implemented solely by NAND gates". But these patents are very weak because the amount of innovation is so low. (A synthesis tool could come up with the same idea) Kolja SulimmaArticle: 77311
Hi, We are doing a large V2P design with some blocks requiring very tight timings. Up to now we run the design through par and then used the ngc file to guide for the critical routed nets and placed components. This is not really convienient since it doesnt allow us to separate the different blocks easily. I wonder now which of the following flows might be the best solution for us: hardmacro, incremental or modular design. We need to have fixed routings and placement. Is this possible with all flows? Are those flows stable for large design (V2P70 which will get at least 60-70% of usage) Thanks for your help Best regards DanielArticle: 77312
On Wed, 29 Dec 2004 16:55:03 +0100, Sam <totalsam-n.o-s.p.a.m@hotmail.com> wrote: >Hi all ! > >I am trying to implement a filter in a spartan III. I have several >multipliers to put inside :-( > >Is it possible to tell the compiler to use the mult18x18 elements, and >then, when all are used, to implement multipliers using for example LUT >?? Or to choose what kind of multipliers to implement by hand ? > >Because I simply use y <= a*b and this implements mult18x18. But there >only are 16 in a 400k gates spartan ! So there's not enough mult18x18, >but I only use a few percent of the slices... > >Thank you in advance ! I don't know of a way you can do this as stated, but you CAN tag individual multipliers with a "mult_style" atttribute in VHDL, to select between "lut" and "block". attribute mult_style : string; attribute mult_style of product1: signal is "lut"; attribute mult_style of product2: signal is "block"; -- this tags the multiplier's output signal with the attribute This way you can choose which style is used to implement each multiplier, which may be good enough for your purpose. - BrianArticle: 77313
Michel Bieleveld wrote: > The problem is that i have two output signals, CE and WE, now i want > to "schedule" the rising of WE just after the rising of CE. You could make the CE signal bidirectional and use the fed back signal from the CE pin to gate the trailing edge of the WE signal. WE out: std_logic; CE inout: std_logic; CE <= internal_CE WE <= internal_WE and CE; -- assuming both are active high. You might need some other logic to disable this gating function at the leading edge if WE leading edge must come before CE leading edge. Also, you must make sure the internal WE signal lasts longer than the internal CE signal so that skew between the two signals does not cause the internal WE to negate before the fed back CE cuts it off. -JeffArticle: 77314
Hi Marc, > Howdy Stefan, > > Looks like this has been a problem in the past: > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18837 > > >From the write-up, it appears the problem is caused by the persist > option being set in BITGEN rather than PAR. > > Good luck, > > Marc > we already use ISE 6.2.03i but still have this problem... and i still don't find this persist-option.... thanks, StefanArticle: 77315
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> schrieb im Newsbeitrag news:crbkfu$uqi$1@lnx107.hrz.tu-darmstadt.de... > Peter Seng <NOSPAM@seng.de> wrote: > > There is a PCMCIA to Parallel-Port adapter available: > > QUATECH SPP-100, > > Single parallel port PCMCIA card for about 160,00 Euro, it worked well on > > several PC?s... > > > And for just configuring - have a look at the FTDI chips and bit-bang > > app-notes: > > http://www.ftdichip.com > > > The FT2232 has a dedicated serial engine to generate JTAG/SPI/I2C. However I > have not seen an open project for JTASG interface to use this chip. > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Hello, why JTAG??? For configuring CCLK, DATA and Done are all You need. - no special knowledge about JTAG (just a Xilinx/Altera/Xxx data sheet) - no special knowledge about USB and OS (comes from FTDI) If debug or CPLD´s come into discussion things may be different.... with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Goeppingen Germany tel +49 7161 75245 fax +49 7161 72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 77316
Hi newsgroup users,
I am trying to implement the following in my VHDL testbench:
Within a process (without sensitivity list) I call a procedure "wait_delay".
In the most test cases the signal 't_order_burst_data' gets high when
the procedure is left again.
But there are also some cases where it gets high while the loop
in the procedure is busy. I want the procedure to abort then.
But how can I make the signal 't_order_burst_data' visible for the procedure
all the time ?
I would be very thankful for any suggestions.
procedure wait_delay ( signal clock : std_logic;
signal order_burst_data_in : std_logic) is
variable i : natural;
begin
for i in 0 to 4 loop
exit when order_burst_data_in='1';
wait until rising_edge(clock);
end loop;
end wait_delay;
...
process
begin
wait until rising_edge(t_clk);
for m in 0 to 10 loop
wait until rising_edge(t_clk);
wait until t_order_burst_data='1';
wait_delay(t_clk,
t_order_burst_data);
end loop;
t_continue <= '1';
wait;
end process;
Article: 77317Not specifically an FPGA question, but does anyone know of any free JTAG testing software? I've got (or will have) lots of assembled boards to test, and I'm thinking about using JTAG. The problem is, the software needs to work out for itself what the netlist is from a known good board. I can buy software to do this, but it'll double the cost of the assembled board. Cheers RTArticle: 77318
ALuPin wrote:
> Hi newsgroup users,
>
> I am trying to implement the following in my VHDL testbench:
>
> Within a process (without sensitivity list) I call a procedure "wait_delay".
> In the most test cases the signal 't_order_burst_data' gets high when
> the procedure is left again.
> But there are also some cases where it gets high while the loop
> in the procedure is busy. I want the procedure to abort then.
> But how can I make the signal 't_order_burst_data' visible for the procedure
> all the time ?
>
> I would be very thankful for any suggestions.
>
>
> procedure wait_delay ( signal clock : std_logic;
> signal order_burst_data_in : std_logic) is
> variable i : natural;
> begin
> for i in 0 to 4 loop
> exit when order_burst_data_in='1';
> wait until rising_edge(clock);
> end loop;
> end wait_delay;
Have you tried:
wait until rising_edge(clock) or order_burst_data_in='1';
--
My real email is akamail.com@dclark (or something like that).
Article: 77319Hi > Just saw your message; Hotmail relegated your email to my Spam folder! > Anyway, I'm working away in the UK presently, I'll be back at my desk later > this week, when I can give you more detail. Thanks, I'd appreciate it. > I can say that the spacing > between layers 1 and 2 is small. It has to be for the laser drill to work. > IIRC, it's only 2 mil / 2 thousands of an inch. This means that layer 1's > 'reference plane' is of course layer 3, but it's not much further away from > layer 1 than layer 2. The consequences are, I suppose, that, for controlled > impedance traces, layer 1 tracks have to be a little thicker. I generally > keep my controlled impedance traces on layer2. Or very short so it doesn't > matter; remember the laser vias enable you to get ICs a lot closer togethe > than you would otherwise be able to do! Of course, if you're trying to build > accurate controlled impedance traces on layer 1, you don't want to be > putting a lot of layer 2 traces underneath these layer 1 traces. On the > other hand, occasional 90 degree crossings aren't gonna be a problem. > Mentor's Hyperlynx is a great tool for checking this sort of stuff out. I'm not working right now with dense bga ( just a small FT256 and PBGA272), nor a lot of layers ( 6 or 8 ). And I'm trying to find what would be the best for my application (cost and perf, ...) between either using 4 mil traces or microvias. Both allow to avoid lot's of vias in the "critical" zone under the bga where I need place to put bypass and big vias for power. It also reduces greatly the impact on SI. It's also interesting for me for future applications where I might have to use denser parts. Using 4 mil traces, I can escape most of the FPGA pins without via at all and connect them quickly to where they belong (one DDR chip using point to point connection for the critical nets). The downside is that they have a higher impedance (more like 105 ohm using 35µm copper). That's a little over the "recommended" for PCI (60-100 ohm) but still since my PCI bus is on an internal layer I could try to change the trace width before and after the vias (here I just want the vias out of the way). Wait a minute ... or I could use a thinner layer ... Using microvia, I can also escape de BGA without loosing my clean power planes and there I can escape and spread all the signals with 6 mil traces. I'll have to simulate some tests and discuss that with the board house as well. Anyway, great technique, Best regards, SylvainArticle: 77320
ALuPin@web.de (ALuPin) wrote: >Hi newsgroup users, <description of his problem> >I would be very thankful for any suggestions. Another post from a truly prolific information leech bought to you by Google.Article: 77321
Hi, I'm trying to implement a sinusoid extraction algorithm (see code below) on a SpartanIIE FPGA. I would appreciate if somebody could help me on starting to write the VHDL code from the matlab algorithm I have. I need a direction to start from, I dont have experience with DSP on FPGA before. f=30;T=1/f; fs=11025;Ts=1/fs; n=10;z=pi/4; u1=50; u2=500; t=0:Ts:n*T; x=length(t); u=sin(2*pi*f*t+z); A(1)=0; Phi(1)=0; for k=1:x y(k)=A(k)*sin(Phi(k)); e(k)=u(k)-y(k); A(k+1)=A(k)+2*u1*e(k)*sin(Phi(k))*Ts; Phi(k+1)=Phi(k)+(2*u2*e(k)*A(k)*cos(Phi(k))+2*pi*f)*Ts; end figure(1), subplot(211), plot(t*1000,u),subplot(212), plot(t*1000,y) I would need lookup tables for sine and cos implementation. Can I use the look uptable IP core available from Xilinx?? if yes is it free? I am using the ISE webpack which is available for free download. I would need a headstart how to start converting my algorithm to VHDL. Please advise. Thanks, SDArticle: 77322
I find it amazing and disturbing that people have the audacity to ask for help and favors from this newsgroup, without giving their name, their affiliation, or at least the reason for their question. How would you react if somebody you had never seen before just barged into your home or office and asked for a favor, without introducing himself or explaining the reason for his question ? Many of us love to help and explain, but I do not like to be taken advantage of in a totally impersonal way... Are newsgroups fostering the death of civility ? Peter AlfkeArticle: 77323
Peter, I couldn't agree more. I can understand a spoof email address to deter spam, but why would it hurt to use your real name, and explain the reasons behind the query. Oh wait, perhaps if I was a student trying to cheat my way to a qualification, I'd use a pseudonym, to avoid detection. I'm not sure that newsgroups are fostering the death of civility, maybe they're just festering in their own deaths. I noticed comp.dsp has just been through a bad patch too, I've given up reading most of it. Symon. (Although my real name is Luxury Yacht) "Peter Alfke" <peter@xilinx.com> wrote in message news:1104863148.865070.96790@f14g2000cwb.googlegroups.com... >I find it amazing and disturbing that people have the audacity to ask > for help and favors from this newsgroup, without giving their name, > their affiliation, or at least the reason for their question. > > How would you react if somebody you had never seen before just barged > into your home or office and asked for a favor, without introducing > himself or explaining the reason for his question ? > > Many of us love to help and explain, but I do not like to be taken > advantage of in a totally impersonal way... > Are newsgroups fostering the death of civility ? > Peter Alfke >Article: 77324
SD wrote: > I'm trying to implement a sinusoid extraction algorithm (see code > below) on a SpartanIIE FPGA. I would appreciate if somebody could help > me on starting to write the VHDL code from the matlab algorithm I have. > I need a direction to start from, I dont have experience with DSP on > FPGA before. To start, consider how it would be implemented in TTL chips, gates, flip-flops, counters, RAMs, etc. > f=30;T=1/f; > fs=11025;Ts=1/fs; Very convenient to divide in matlab, but it takes a lot of logic to do it in an FPGA. Much better to use T and Ts as constants. Most likely they should be scaled fixed point (the binary point not directly to the right of the LSB). How many bits do they need? > n=10;z=pi/4; > u1=50; u2=500; > t=0:Ts:n*T; x=length(t); > u=sin(2*pi*f*t+z); > A(1)=0; Phi(1)=0; > for k=1:x > y(k)=A(k)*sin(Phi(k)); > e(k)=u(k)-y(k); > A(k+1)=A(k)+2*u1*e(k)*sin(Phi(k))*Ts; > Phi(k+1)=Phi(k)+(2*u2*e(k)*A(k)*cos(Phi(k))+2*pi*f)*Ts; > end > figure(1), subplot(211), plot(t*1000,u),subplot(212), plot(t*1000,y) > I would need lookup tables for sine and cos implementation. Can I use > the look uptable IP core available from Xilinx?? if yes is it free? I > am using the ISE webpack which is available for free download. I would > need a headstart how to start converting my algorithm to VHDL. Please > advise. Xilinx provides for RAM and ROM (initialized RAM). You need to supply the data. There is no charge for initializing RAM, you supply the bits. This should be relatively easy if you generate one k value, one A and one Phi, per clock cycle. If you want more, it gets complicated fast. If you are doing it in floating point in matlab, I would try converting to fixed point in matlab before trying to convert to VHDL. -- glen
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