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Brian Drummond wrote: > On Thu, 06 Jan 2005 12:23:00 -0700, Bret Wade <bret.wade@xilinx.com> > wrote: > > >>Brian Drummond wrote: >> >>>On Wed, 05 Jan 2005 12:06:48 -0700, Bret Wade <bret.wade@xilinx.com> >>>wrote: > > >>>I am working with larger RPMs than this, with some degree of success >>>(cautiously expressed; the design is not yet complete) >>> >>>There *may* be problems with BRAMs and multipliers in RPMs. >>> >> >>There is a certain amount of complexity added when an RPM combines >>multiple component types (Heterogeneous RPM) due to the fact that for >>the default grid system, the various component types are on different >>grids. This is only a problem if your RPM requires normalization. >>http://www.xilinx.com/bvdocs/appnotes/xapp416.pdf > > > This is _very_ good information on RPMs including BRAMS or multipliers > or such (IOBs?) which live on different grids. > > I note S0 and S1 share the same RPM_GRID X value though (unless I > misunderstand the floorplanner) they appear in adjacent columns (x, x+1) > in floorplanning, e.g. You're correct that the two grid systems increment differently. The RPM Grid corresponds to the actual placement grid. The original grid system was created so that designers could easily specify column based RPMs such as carry chains using increments of one. This discrepancy between the original grid and the placement grid is what causes problems when an RPM is not placed in the correct slice type. There are inherent problems anyway wrt shifting logic across CLB boundaries in something other than full CLB increments. > > floorplanner and standard grid > S2 S3 > S0 S1 > > RPM_GRID > S3 > S2 > S1 > S0 > > The translation given from SLICE_X26Y40 to RPM Grid X42Y84 in the > appnote seems to bear this out. > > >>>There are problems using the floorplanner to create RPMs from smaller >>>ones, mostly associated with tools issues (the floorplanner alone has >>>two mutually incompatible understandings of RLOC_ORIGIN, the mapper >>>moves the origin left by 1 location under some (apparently undefined) >>>circumstances, the placer reports errors on some correct RLOC_ORIGIN >>>constraints and silently deletes others altogether, and so on. >> >>RLOC_ORIGIN values must take into account the normalization of the RPM. >>More on that in the appnote. > > > It's not clear to me quite how that relates to the testcase, which only > uses LUTS, SRL16s, and FFs, which are all on the same grid (Spartan-3 > restrictions on SRL16 notwithstanding). R0C0 is used, though some > elements have negative X values (the floorplanner doesn't give you any > choice about this if you don't use the lower left hand corner of the > bounding box surrounding the RPM). > > Is normalisation still an issue in this case? > It seems to me that the normalisation is onto the same grid since > RPM_GRID is not being used, so I don't see where the problem lies. Yes, normalization needs to be taken into account even when there is only one component grid involved if you are using RLOC_ORIGIN. If you don't calculate an offset to compensate for normalization, then the macro won't get placed where you expect it. > > And outside Xapp416 and this message, I haven't seen any mention of > normalisation. Is it described anywhere for the standard grid? > Aha! Searching on that word gives the useful looking TechXclusive > "Relationally Placed Macros 08/30/2002 " > http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iCountryID=1&iLanguageID=1&sTechX_ID=pgse_rpms&BV_SessionID=@@@@0242741689.1105050007@@@@&BV_EngineID=cccgadddhmijmghcflgcefldfhndfnf.0 > I was consulted on that section of the document, so you still have no evidence that I know what I'm talking about. :-) > >>The mapper converts RLOC_ORIGINs into MACRO >>LOCATE constraints in the PCF file, so strictly speaking it's not >>possible for the placer to ignore RLOC_ORIGIN constraints because it >>never sees them. > > > True! Strictly speaking the placer ignores the MACRO LOCATE constraints > instead. They are in the PCF file, I just checked - see comment above > regarding the mapper moving the origin, it does so in the same > constraint conversion. The placer doesn't often ignore LOCATE constraints. It's more likely that you are just getting unexpected results because of the normalization issue. Note the difference between your RLOC_ORIGIN and the resulting LOCATE constraint. That difference is due to normalization. > > >>A separate issue is that the RPM needs to be placed in the same "slice >>type" that it was created about. There are four slice types represented >>by the four slices in a CLB, S0-S3. For simplicitys sake, it is best to >>construct a macro about the X0Y0 slice and then always place it in an S0 >>slice type if possible. If the RPM is placed in a different slice type, >>the relative placement will be broken, which can lead to placement >>failures. > > > This may be the problem, but I don't see why the limitation exists. > Hand placement of the same components onto the other slice types (again, > excepting SRL16s in "odd X" locations) seems to work fine, though not > placement of RPMs. The best way to illustrate this is to manually place RPMs in FPGA Editor using different slice types. You'll quickly see how the relative position gets corrupted and if you crunch the grid numbers, you'll understand why. The importance of the relative position varies with the logic involved. It's critical for wide-gate structures that depend on dedicated routing resources between F5 and F6 muxes in different slices. It's relatively unimportant for generic LUT/FF slices. > > >>>Maybe FPGA editor is a more stable tool for floorplanning? I would try >>>it but only have WebPack in current software. >> >>FPGA Editor is not a floorplanner. It is an editor for displaying and >>modifying the physical design and applying some physical constraints. > > > I have used it (3.1 era) but don't have a current one. > > >>>Can you point me in the direction of a flow that would use guided >>>routing for a top level module composed of several pre-routed RPM >>>modules? Preferably where at least one of the RPMs has itself been >>>created in this way? > > >>Directed Routing is not incompatible with the guided flows. There's no >>reason why you can't combine them. You'll just need to get FPGA Editor >>and try it. >> > > > Interesting, but I think I have been warned off Directed Routing for the > size of macros I am using. You've been warned off using it for hundreds of nets. You could still consider using it for the most critical paths or in any case where there is only one suitable routing resource for a signal. > > Is there a way of using routed versions (NCDs?) of several RPMs as > (multiple) guide files for a design incorporating them? Your earlier > recommendation that "Guide should be used instead" seems to imply that > there is, but I can't see it. That's what Modular Design does. Separate guide files are used during the assembly phase to guide the overall design from the various module implementations. > > Many thanks for your answers and help, > > - Brian You're welcome. BretArticle: 77451
Hi George,
Please use mysupport to submit a problem request along with your design.
It will not be possible to track down this problem without the project and
the design files.
Subroto Datta
Altera Corp.
"GMM50" <george.martin@att.net> wrote in message
news:1105040930.216544.122370@c13g2000cwb.googlegroups.com...
> Hello:
>
> I'm entering a desing in to Altera's Quartus II 4.1 using block diagram
> files as the input mechanism.
>
> When I try to compile I get the following message......
> Internal Error: Sub-system: CDB_SGATE, File: cdb_sgate_wys_ygr.cpp,
> Line: 4111
> cdb_is_connected(b_iterm)
> Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version
> ...............
>
> The error is probably something I've done as I created the schematics.
> My question is how to track the error down?
>
> The design is heirarcail and I've tried deleting functional blocks.
> When I do I get different error messages because signals are now
> missing.
>
> What steps to take.
>
> Thanks
> George
>
Article: 77452On Thu, 06 Jan 2005 11:37:30 -0700, Kevin Neilson wrote: > vadim wrote: >> I have received a job offer from a company >> in San Jose, California. The position title is: Test Development >> Engineering. The salary offered is 67k/year with Relocation Assistance >> and a Benefits package. I already have a 60k/year job in Toronto, >> Canada as Applications Engineer. >> >> The San Jose job is closer to circuit-design which is an area I would >> like to get into. >> >> I was told that the housing prices of Bay Area will make this salary >> into a 50k equivalent of Toronto. So practically my "buying power" is >> reduced. >> >> I have a dillema whether: >> -Professional advantages of this position, closer to ciruit design. >> -Working in Silicon Valley, the Mecca of HighTech. >> >> outweigh the offered salary ? >> >> Thanks in advance. > > I would guess you'd be financially better off in Toronto. I don't know > how expensive Toronto is, but I know it will be fairly expensive to live > in San Jose. And while the position may be closer to design, it's not > terribly close. > > I'm surprised about the comments from the guy from Sweden. He must have > moved someplace very expensive, because Sweden isn't cheap. And their > tax rate is like 98%. I don't know about Sweden, but in Norway the tax rate isn't actually as bad as that - only about 40% or so. It varies widely according to your income (children's author Astrid Lingrid in Sweden once had a tax rate of 102%), and things like mortgages are tax-deductable. Your taxes also cover the national health care, saving you from health insurance. As for the cost of living here (in Norway - Sweden is similar), some things are relatively cheap (like housing, and electricity), and others expensive (like petrol). Salaries have much less spread here - high-paying jobs are lower-paying than the UK or the US, but low-paying jobs are better paid. And as an indication, my four-bedroom house cost about twice my salary, although admittedly that was an unusually good deal.Article: 77453
Hi everybody, is there some methodology supporting for synthesis of more FSMs included in one source file ? How to set constraints of each one FSM separately ? Something like: dc_shell:> set_fsm machine1 dc_shell:> set_encoding_style one_hot dc_shell:> set_fsm machine2 dc_shell:> set_encoding_style gray dc_shell:> compile dc_shell:> set_fsm machine1 dc_shell:> report_fsm dc_shell:> set_fsm machine2 dc_shell:> report_fsm Or is it really needed to write FSMs into separate files ? I was unable to find any synopsys/synthesis newsgroup :o( Thanks Marek -- Dipl.-Ing. Marek Ponca Institut of Circuit Technology and Electronics Faculty of Electrical Engineering and Information Technology Ilmenau Technical University P.O. BOX 10 05 65 98684 Ilmenau GermanyArticle: 77454
HI, If you have not wrriten any test bench yet .... then Start writing it for combinaitonal logic first ... ( Like nand gate, mux, decoder, Priority Encoder)... Then go for sequential logic ( Like Simple Fsm s for sequence detector and so on ).. You need a good guide or a good book to start with. Here are few web site where you can find some good stuff.. http://www.acc-eda.com/vhdlref/refguide/language_overview/test_benches/test_benches.htm http://members.aol.com/SGalaxyPub/useful_links_vhdl.htm Regards, Mohammed A Khader.Article: 77455
HI, Only one FSM design per entity is recommended. If a file has multiple FSMs for a single entity , only one is extracted each time you compile. It is not possible to predict which FSM will be extracted. Regards, Mohammed A khader.Article: 77456
On 2005-01-06, Marius Vollmer <mvo@zagadka.de> wrote: > very helpful). As expected, GOSPL is not even close to being Open > Source or Free Software. It is basically a free of charge, > semi-closed industry consortium controlled by STMicroelectronics. Because "open source" is a registered trademark (http://opensource.org/trademarks/) and there are restrictions what licenses are acceptable as open source, it looks then like GOSPL is in trademark violation. But then again, I haven't seen the license, nor am I a lawyer. This just makes me wonder the case. > But I believe them when they say that this is only intermittent and > the real goal is indeed to go Open Source in the future. This is very nice to hear. Many times companies have started with restricted license and then later opened up, e.g. Qt/Trolltech of the KDE fame. I'm awaiting with great interest what will happen with GOSPL.Article: 77457
On Thu, 06 Jan 2005 11:37:30 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: >I'm surprised about the comments from the guy from Sweden. He must have >moved someplace very expensive, because Sweden isn't cheap. And their >tax rate is like 98%. Hi Kevin, Interesting comment. It was actually the reaction I got from most of my American friends while I was working there. But the fact that the tax rate in Sweden is not much higher that the US, should come like a shock to most of people (it was for me deffinitely). I was living in New York, the federal tax was about 23%, then you have the social security tax at 6.5%, plus NY State tax (I think it is 3.7%) then you have the NY City tax, plus an addition to that was the "cleaning" tax! Ok, if you think this is nothing,then you have to compare to what I payed in Sweden. My tax rate in Sweden was 38.5%, it was slightly less because I choose not to pay tax to the Swedish Chirch. For that I was getting free education, free health care, excellent public service and a lot more. BR, /Farhad PS. I am living in Ireland right now and the tax system here is kind of messy, I still havn't figured out how the system really works!Article: 77458
Hat jemand erfahrung mit dem USB IP-CORE von Trenz-electronic? Ich brauch schützen hilfe! cu patrik kramerArticle: 77459
Peter Alfke wrote: > Bo wrote: > > [...] Interestingly, on large parts you can > > have trouble if you aren't using enough resources because the tools 'spread' > > the logic across the chip too far and cause timing errors [...] > > If you do not constrain the timing, the tools "are lazy" and make their > life easy, by spreading the logic around, so as to avoid congestion. > The proper solution is to constrain the timing and thus force the tools > to make more appropriate, more intelligent, and more demanding > decisions. Howdy Peter, I restored part of Bo's message above... he mentions timing errors, which I assume means he did have timing constraints. In the past, I have also seen MAP or PAR do what he describes - rather than spreading the logic across the chip, it groups it towards the edges, leaving a larger unused area in the middle. Adding a few pipeline stages corrected the timing problems. But in the grand scheme of things, I think I prefer this behavior because it implies to me that MAP or PAR attach a pretty high importance to putting the logic close to the IOBs, which turns it into an easy way to get (very basic) floorplanning if IOB locations are chosen wisely. > It's the tools' equivalent to Parkinson's Law: > "Every job grows to use up all the available resources in time, space, > and money". > It's up to you to delineate the available resources ! No doubt about either one of those statements! Have fun, MarcArticle: 77460
%l is for printing longs, not long longs. %ll is typically for long longs. Cheers, JonB.Article: 77461
Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid> writes:
> Because "open source" is a registered trademark
> (http://opensource.org/trademarks/) and there are restrictions what
> licenses are acceptable as open source, it looks then like GOSPL is
> in trademark violation.
Hmm no, they should be safe:
http://opensource.org/docs/certification_mark.php
The Open Source Definition spells out the essential qualities of
open source software. Unfortunately, the term "open source" itself
is subject to misuse, and because it's descriptive, it can't be
protected as a trademark (which would have been our first
choice). Since the community needs a reliable way of knowing
whether a piece of software really is open source, OSI is
registering a certification mark, OSI Certified, for this purpose.
Article: 77462Hello, I am running Xilinx ISE software to do a schematic based FPGA design. Are there any tools to show the differences between 2 version of a schematic? I can diff the .sch files and get hints as to what has changed, but I was looking for a graphical tool to see the schematics. Any suggestions? Thanks, Ben JArticle: 77463
On Thu, 06 Jan 2005 18:02:20 -0700, Bret Wade <bret.wade@xilinx.com> wrote: >Brian Drummond wrote: >> >> I note S0 and S1 share the same RPM_GRID X value though (unless I >> misunderstand the floorplanner) they appear in adjacent columns (x, x+1) >> in floorplanning, e.g. > >You're correct that the two grid systems increment differently. The RPM >Grid corresponds to the actual placement grid. The original grid system >was created so that designers could easily specify column based RPMs >such as carry chains using increments of one. ah! so in these generations (VII, S3) the carry increment is 2? Then I can see that reflecting the true organisation in the floorplanner would be problematic. >This discrepancy between >the original grid and the placement grid is what causes problems when an >RPM is not placed in the correct slice type. There are inherent problems >anyway wrt shifting logic across CLB boundaries in something other than >full CLB increments. That may be part of what my test case is exposing. Incidentally I DID find a recommmendation to place RPMs such that they began at R0C0 in the answers database ... but it went on to say "this problem will be fixed in 4.2"! >> Is normalisation still an issue in this case? >> It seems to me that the normalisation is onto the same grid since >> RPM_GRID is not being used, so I don't see where the problem lies. > >Yes, normalization needs to be taken into account even when there is >only one component grid involved if you are using RLOC_ORIGIN. If you >don't calculate an offset to compensate for normalization, then the >macro won't get placed where you expect it. Oh I calculate an offset. The problems are that the tools appear to modify that offset in undefined ways or ignore them. >I was consulted on that section of the document, so you still have no >evidence that I know what I'm talking about. :-) I'm pretty sure you do, but it can get pretty convoluted so I have no evidence I understand you :-) >> Strictly speaking the placer ignores the MACRO LOCATE constraints > >The placer doesn't often ignore LOCATE constraints. It's more likely >that you are just getting unexpected results because of the >normalization issue. Note the difference between your RLOC_ORIGIN and >the resulting LOCATE constraint. That difference is due to normalization. Possible, but I would expect the placer report (.par) file to contain "RESOLVED that <x> be placed at <y>" messages, but I only get 6 for 8 constraints (this file is included in the testcase), and the normalisation for the other two was X20Y22 and X18Y-12, for modules 6x9 in size. Seems unlikely that this is just normalisation. The other 6 were placed within a couple of CLBs of the expected location, I am trying to reconcile the differences with what you have told me about normalisation. >> This may be the problem, but I don't see why the limitation exists. >> Hand placement of the same components onto the other slice types (again, >> excepting SRL16s in "odd X" locations) seems to work fine, though not >> placement of RPMs. > >The best way to illustrate this is to manually place RPMs in FPGA Editor >using different slice types. part of this exercise has been to see how far I could get with the free tools and the S3/1500, but now I'm convinced it's time to upgrade. >> Is there a way of using routed versions (NCDs?) of several RPMs as >> (multiple) guide files for a design incorporating them? Your earlier >> recommendation that "Guide should be used instead" seems to imply that >> there is, but I can't see it. > >That's what Modular Design does. Separate guide files are used during >the assembly phase to guide the overall design from the various module >implementations. Again, thanks. Having the right term to search for makes all the difference! - BrianArticle: 77464
When we were developing the board we talked to a number of customers and their requirements were all over the map. Some wanted PC type ports (VGA, keyboard, mouse, etc.), others wanted ADCs, DACs, motor controllers, etc. Our decision was to provide a way so that the user could easily add their own circuitry. Phil "Ziggy" <Ziggy@TheCentre.com> wrote in message news:j4hDd.622149$wV.130898@attbi_s54... > > Looks interesting, but its a shame it does not have more 'standard' > ports.. > > I realize you can wire them up yourself, but the more that are on board > the less you have to dink around with.. > > Digiants boards look really good for development projects. Especially > with the 400k upgrade option. Waiting on my to arrive. > > PNowe wrote: >> If anyone is looking for a Spartan 3 board for hobbyists and students, >> that also includes a solderless breadboard for adding your own circuitry, >> have a look at www.dulseelectronics.com . An article about the board >> appeared in the Dec 2004 issue of Circuit Cellar Magazine. >> >> Phil >> Dulse Electronics >>Article: 77465
Thanks for your responses to my posting. I would like to ask you if you would know why are they interested in bringing me down from Canada ? The reason I am asking is, I am a recent graduate and have been working in Toronto only for couple of months. So I am not some expert they can't find in Silicon Valley.. This raises my suspicion abit and am afraid of being "lured" by the glorious image of Silicon Valley to exchange my current job for something that doesn't worth it. I know this is my decision and at the end of the day you have to take some chances to get anywhere, but I am just trying to gather some opinions from either edges of the spectrum to understand whats "cooking" down there and what people have experienced. Everyone of my US relatives and friends are saying: "Jump on it!" "Once there you will have lots of opportunities" and I realize that there are dozens of others in SV who would gladly take this position....so is it a genuine opportunity ? PS Toronto is not a cheap place. Yet is safe and very multi-cultural.Article: 77466
In article <81ust09aufitcab5e3pp55a4h95o8sb3n4@4ax.com>, Farhad A. <n e w s @ p a n j e r e . n e t> wrote: >I was living in New York, the federal tax was about 23%, then you have >the social security tax at 6.5%, plus NY State tax (I think it is >3.7%) then you have the NY City tax, plus an addition to that was the >"cleaning" tax! California is worse. Say a marginal fed of 25%, state of 9%, social security and medicare of ~8%, and the marginal tax rate is pretty high. Then add the >8% sales tax, the 1% property tax, and its quite amazing just how poor the state government is with taxes as high as they are. Note those 103% tax figures you see in some horror stories are for MARGINAL tax rate, you earn another dollar, how much tax do you pay on it... Well, I once had a case where because I made an extra $20, I was no longer eligible for a $60 california tax credit, making the marginal tax rate on that last $20 a whopping 300%! -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 77467
I did. Last time I used MySuppory it took 6 weeks for a reply and the reply was "Is this still a problem" and I answered Yes. That was last November. GeorgeArticle: 77468
"vadim" <vbishtei@hotmail.com> wrote in message news:2a613f5d.0501070727.3421ca8c@posting.google.com... > Toronto is not a cheap place. Yet is safe and very multi-cultural. All the engineers I know in San Jose always carry 9mm automatic weapons to rob immigrants to pay the rent. ;-) Seriously, San Jose is touted as the safest big city in America, and I've yet to find a place anywhere in the world with a bigger variation in nationalities. I say, take the position, if you don't like it, move back. What've you got to lose? Personally, I'm really enjoying it here; I've met loads of top blokes, with a wide range of specialties, you can't help be a better engineer for it. And the weather's better than the UK. (Except not this morning!) Good luck whatever you do, Syms.Article: 77469
"Marek Ponca" <name@office.com> schrieb im Newsbeitrag
news:41DE5FAD.F7E3A721@office.com...
> Hi everybody,
>
> is there some methodology supporting for synthesis of
> more FSMs included in one source file ?
>
> How to set constraints of each one FSM separately ?
>
> Something like:
>
> dc_shell:> set_fsm machine1
> dc_shell:> set_encoding_style one_hot
>
> dc_shell:> set_fsm machine2
> dc_shell:> set_encoding_style gray
>
> dc_shell:> compile
>
> dc_shell:> set_fsm machine1
> dc_shell:> report_fsm
>
> dc_shell:> set_fsm machine2
> dc_shell:> report_fsm
>
>
> Or is it really needed to write FSMs into separate files ?
Synthesis constraints for XST
VHDL
Before using FSM_ENCODING, declare it with the following syntax:
attribute fsm_encoding: string;
After FSM_ENCODING has been declared, specify the VHDL
constraint as follows:
attribute fsm_encoding of {entity_name|signal_name}:
{entity|signal} is "{auto|one-hot|
compact|gray|sequential|johnson|user}";
The default is AUTO.
Regards
Falk
Article: 77470GMM50 wrote: > I did. > > Last time I used MySuppory it took 6 weeks for a reply and the reply > was "Is this still a problem" and I answered Yes. That was last > November. > > George George, Please email me the Problem Report number and I will get the design form the supportfolks. Sincerely, Subroto Datta Altera Corp.Article: 77471
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> wrote in message news:crkcdf$irk$1@agate.berkeley.edu... > > Not to mention that the US dollar has further to drop, and Toronto is > not ruled by a President who believes it is more important to be loyal > than correct. > -- Sounds like you should move to Toronto, Nick.Article: 77472
No suggestions, except for the obvious one. Do it with a HDL instead? Why use schematics, even Verilog's better than that! ;-) Cheers, Syms. "Jansyn" <jansynf@worldnet.att.net> wrote in message news:h4xDd.76363$uM5.73317@bgtnsc05-news.ops.worldnet.att.net... > Hello, > I am running Xilinx ISE software to do a schematic > based FPGA design. Are there any tools to show the > differences between 2 version of a schematic? > I can diff the .sch files and get hints as to what > has changed, but I was looking for a graphical tool > to see the schematics. > > Any suggestions? > > Thanks, > Ben J > >Article: 77473
Hi, I am working max_sample_temp and min_sample_temp over several Clocks. Then at symbol_clk_edge I would like to assign most recent value of these signals to another signals (marked as _result) and load new value to _temp signals again. Is the next a good way to do it? I suspect that max_sample_result <= SAMPLE_IN can occur since all statements are executed AT THE SAME TIME. That's what I don't want. What should I do? if (clk'event and clk='1') then if (symbol_clk_edge='1') then -- Store results in another signal and reset temp signal -- to the first new sample max_sample_result <= max_sample_temp; min_sample_result <= min_sample_temp; max_sample_temp <= SAMPLE_IN; min_sample_temp <= SAMPLE_IN; end if; end if; ThanksArticle: 77474
Hi, It depends on exactly what you are trying to do. If you want to save the input SAMPLE_IN signal(s) on every rising edge of clk and then only transfer the results to the output (max_sample_result for eg.) when symbol_clk_edge is high, then you need to break the code into 2 processes as follows. process(clk) begin if (clk'event and clk='1') then -- Sample inputs and store in temp registers max_sample_temp <= SAMPLE_IN; min_sample_temp <= SAMPLE_IN; end if; end process; process(clk) begin if (clk'event and clk='1') then if (symbol_clk_edge='1') then -- copy temp register to output max_sample_result <= max_sample_temp; min_sample_result <= min_sample_temp; end if; end if; end process; Hope this helps Philip Nowe www.dulseelectronics.com "lomtik" <lomtik@gmail.com> wrote in message news:1105123142.316311.201010@f14g2000cwb.googlegroups.com... > Hi, > I am working max_sample_temp and min_sample_temp over several Clocks. > Then at symbol_clk_edge I would like to assign most recent value of > these signals to another signals (marked as _result) and load new value > to _temp signals again. > Is the next a good way to do it? > I suspect that max_sample_result <= SAMPLE_IN can occur since all > statements are executed AT THE SAME TIME. That's what I don't want. > What should I do? > > if (clk'event and clk='1') then > if (symbol_clk_edge='1') then > -- Store results in another signal and reset temp signal > -- to the first new sample > max_sample_result <= max_sample_temp; > min_sample_result <= min_sample_temp; > max_sample_temp <= SAMPLE_IN; > min_sample_temp <= SAMPLE_IN; > end if; > end if; > > > > Thanks >
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