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Can I program only one page of a EPC16 Altera configuration device via JTAG ? In particular, can I program only the page that I have selected with PGM(2:0) ? I have to use this for remote update. MatteoArticle: 77826
Thanks Falk and Nicolas, the NxN array seems like a good idea - I was just looking for some more elegant solution (like a special generate) for the code to be more readable.. But it looks like I have no choise. Nicolas, special thanks for the code example it is a very nice implementation. and BTW the right array reset syntax is -> reg <= (others => (others => '0' ) ) ;-) Thanks, Moti.Article: 77827
Hello, when having a look at the TIMING REQUIREMENTS & OPTIONS I see that there are DELAY REQUIREMENTS with Tsu, Tco, Tpd, Th and MINIMUM DELAY REQUIREMENTS with Tco, Tpd What is the difference when defining these constraints ? Does these constraints make sense when having a multiclock system ? When sampling an asynchronous signal coming into the FPGA how can I make the synthesis tool place the first flipflop of a synchronizing flip flop chain in a I/O register cell to improve Tsu ? Thanks in advance. Rgds AndréArticle: 77828
Moti a écrit : > and BTW the right array reset syntax is -> reg <= (others => (others > => '0' ) ) ;-) Thanks :o) I thought that was for arrays of vectors only, not 2D arrays... -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 77829
Before going into details I want to explain the background: I am using an FPGA to deal with signals coming from an external USB transceiver. This USB transceiver has an 16bit parallel interface. The data coming into the FPGA are synchronous to a clock which is generated by the USB transceiver. I use that transceiver clock to feed my PLL (input frequency 30MHz). Of course there is also the other direction that is I have to send data back to the USB transceiver. These data have to be synchronous to the transceiver clock. Now I ask myself which clock to use correctly to generate data to send back to the USB transceiver. When I use this input clock I would like to know what timing constraints I have to consider for the data I send back to the transceiver so that I do not violate Tsu, Th ... Or would it be more preferable to use a different clock (1:1) maybe coming out of the PLL ? Any ideas are highly appreciated. Rgds AndréArticle: 77830
How about: http://www.compxs.com/scafell_mod.htm If you don't want an 802.15.4 PHY, ask about their Bowfell board (which isn't listed on the web site). That uses a ml2724 for RF instead of a cc2420. Cheers, JonArticle: 77831
One more thing if you could help.. I am using Async memory in my logic..This memory is being automatically inferenced by the Quartus tool (alt_syncram function).I am just coding the async memory using VHDL. For Stratix EP1S10F780C5, the largest memory to memory delay is 9.7 ns while for EP1S10F780C6 the largest memory to memory delay is 10.809 ns. How can i reduce this????? vlsi_learner wrote: > hi > Yes i was not giving any constraints while running the design.Actually > i have Quartus version 4.0 which does not provide the facility of > Timing Optimization advisor.so could not use that facility. > Now when i am giving the constraints as Fmax =100 Mhz & tsu,tco > constraint as suggested by Ben,i get Timing violations.How do i remove > the Timing errors?? > > If i reduce the value of Fmax, again i get correct output for Stratix > EP1S10F780C5 but not for EP1S10F780C6. I have broken down the > combinational path by inserting FF's also?? > > Another thing i am using Asynchronous memory in my design (Look up > tables).Will that have a negative impact on the result when targeting > to Stratix device??Article: 77832
hi, Before giving a suggestion, i assume the following 1.USB transceiver has got separate tx and rx clocks. 2.USB transceiver gives out data w.r.t the tx clock to FPGA 3.USB transceiver receives data in w.r.t the rx clock from FPGA In that case I would suggest using a clock output of PLL. The advantage of using a PLL is that, it will filter out jitter, and also compensates for the skew through clock net(zero delay). But there will be an offset between clock input to PLL and clock output from PLL. That offset value should be used in giving Tsu, Th constraints to data input registers. since it's only 30MHz, there won't be much problem with this offset. But the delay on board from USB transceiver also need to be taken into account. So inside FPGA, only the clock out from PLL can be used. The same clock can be driven out as a rx_clock, or can be used for outputing data towards USB.Article: 77833
In sci.electronics.cad Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote: [. . . snip! . . . ] : Problems/complaints: : 1) I don't like to see LD_LIBRARY_PATH and PKG_CONFIG_PATH globally set. : They provide a capability for testing new versions of system libraries. : I don't believe they were intended to be used system wide. For that : you should add the path to the appropriate /etc/xxxx.conf file. It's : a shame there isn't one for pkg-config (AFAIK) : 2) The schematics in the examples are all composed of main pages with : the transistors and diodes being subpages. There is no obvious (to me : the new user) way of making the link so the transistors appear on the : schematic. Examples are presumably meant for new inexperienced users, : and as such should work flawlessly. : 3) There are no examples of projects for use with the gEDA project manager. : 4) I know it is easier for the developer to run ./configure at the root of : each package, but there ought to be a way to only do it once for the whole : system when you are using Stuart's installer program. : 5) There is really no good reason to rebuild and reinstall the symbols a : dozen or more times. It significantly adds to the build time. : Anyway, it seems to be running, and I will begin to explore the construction : of a project from start to finish. I'm sure that task will keep me quite : busy. : Thanks for the help, and inspite of the problems I had installing, please : know that I think you guys have done a magnificent jog thus far. Thanks! We take your bug reports seriously, and will soon do another CD release with at least some fixes to the problems you discovered. I will take a look at the examples today. Keep watching the project page: http://www.geda.seul.org/ StuartArticle: 77834
In sci.electronics.cad Chuck Harris <cf-NO-SPAM-harris@erols.com> wrote: : Problems/complaints: : 2) The schematics in the examples are all composed of main pages with : the transistors and diodes being subpages. There is no obvious (to me : the new user) way of making the link so the transistors appear on the : schematic. Examples are presumably meant for new inexperienced users, : and as such should work flawlessly. Please help me improve the linkage between these schematics. Is your point that you can't open the lower-level schematics from the top level schematic via "Hierarchy -> Down Schematic"? If so, it was a bug in the examples; I have just fixed it. If you want, try the fix. Edit your gafrc (living in the RF_Amp directory), and add the line (on a new line): (source-library ".") Then, open MSA-2643.sch, double click on Q1, and add the following attribute to it: Attrbute name: source Attribute value: Q1.sch Do the analogous thing for Q2. Then you should be able to use "Hierarchy -> Down Schematic" in the top menu bar to dive into the models for Q1 & Q2. Please let us know if this works for you. Thanks, StuartArticle: 77835
I am also interested in finding a USB2.0 host functionality--my requirements also include the need for vxWorks driver. The chosen chip will have to interface to PPC405 in V2P30 via some custom IP (I'm assuming). Anyone know of an off-the-shelf host controller with vxWorks drivers? Thanks, Paul "Ulf Samuelsson" <ulf@a-t-m-e-l.com> wrote in message news:352j7jF4if8qiU1@individual.net... >> Anyone know of a device that makes implementing USB Host mode as painless > as >> something like the FTDI chips? I need to hang a couple of USB Host ports > on >> a V2P. >> >> No, I don't want to implement the USB functionality within the FPGA, >> those >> logic resources are far too valuable. Ideally, I'd like a simple >> single-chip solution that requires almost zero work to get up and going. >> >> I do control what devices will plug into this, so it doesn't need to be >> as >> intelligent (and/or complex?) as a full-blown USB framework on a PC. >> > > > Atmel has the AT43USB380 OTG controller. > This runs the USB host stack on an embedded micrcontroller > and presents an API to the main processor > which runs a library with the device classes. > The library is delivered in object code only, so you will > have to use a known architecture, or convince the Atmel USB > group to support your choosen architecture. > The AT91M40800 or the AT91R40008 are good chips to run the > device classes on. > Another limitation is the supported device classes. > I think the most populoar classes are Mass Storage, HID and printer > which are supported. CDC has been discussed some time ago, > but I have no updated status. > > -- > Best Regards, > Ulf Samuelsson. > Ulf at atmel dot com > These comments are intended to be my own opinion and they > may, or may not be shared by my employer, Atmel Nordic AB. > >Article: 77836
MM wrote: > Hi all, > > I have a V2P design with data and clock coming from an A/D in LVDS format. > The clock of 210 MHz is an output from the A/D, so it is aligned with the > data with Data to Clock skew of 0.8 ns max according to the A/D datasheet. > Due to an error on the board, the clock polarity was reversed relative to > the data lines, so essentially I expect the "positive edge" to be in the > middle of the data phase at the FPGA pads. I have inserted a > wizard-generated DCM clk_deskew for fine tuning. Experimentally I found that > the design is most stable when the DCM is programmed to a fixed phase shift > of about 70 degrees (0.93 ns at 210 MHz). Below are the snippets from my > code and the timing constraints I am using as well as the related timing > report summary: > > CLK_DESKEW_INST: clk_deskew port map( > rst_in => clk_deskew_rst, > clkin_p_in => clk_dco_P, > clkin_n_in => clk_dco_N, > locked_out => dcm_locked, > clkdv_out => open, > CLK180_OUT => clk_dco_180, -- I tried using this output, but it > didn't work well... > clkin_ibufgds_out => clk_dco_ibufgds, > clk0_out => clk_dco > ); > > > G_1 : > for I in 0 to 11 generate > ADATBUF_INST: IBUFDS_LVDS_25 > port map (adat_P(I), adat_N(I), adat(I)); > ADAT_CLKIN_P: > process(clk_dco) > begin > if rising_edge(clk_dco) then > ll_adat(I) <= adat(I); > end if; > end process; > end generate; > > > NET "clk_dco" TNM_NET = "clk_dco"; > TIMESPEC "TS_clk_dco" = PERIOD "clk_dco" 4.55 ns HIGH 50 %; > > #INST "adat_N<*>" TNM = "TNM_ADAT_PADS" -- ISE doesn't like to see negative > side pads mentioned in constraints > INST "adat_P<*>" TNM = "TNM_ADAT_PADS"; > TIMEGRP "TNM_ADAT_PADS" OFFSET = IN 2 ns BEFORE "clk_dco_P"; > > ---------------------------------------------------------------------------- > ---- > Constraint | Requested | Actual | > Logic > | | | > Levels > ---------------------------------------------------------------------------- > ---- > TS_clk_dco = PERIOD TIMEGRP "clk_dco" 4. | 4.550ns | 4.476ns | 7 > 550 nS HIGH 50.000000 % | | | > ---------------------------------------------------------------------------- > ---- > TIMEGRP "TNM_ADAT_PADS" OFFSET = IN 2 nS | 2.000ns | 1.598ns | 1 > BEFORE COMP "clk_dco_P" | | | > ---------------------------------------------------------------------------- > ---- > > > > While the design seems to be mostly working, I am not quite satisified for > the following reasons: > 1. I am not sure why the numbers I use work the best; It may be that the DCM output at phase "0" is not really aligned with the input pin after the differential receiver. DCM's have a built-in fudge factor to make up for the routing delay from the global input pins to the DCM input. This would tend to make the actual relationship of the DCM phase 0 output somewhat negative wih respect to the DCM clock input pin. I'm not convinced the tools do this right with a differential input clock. I have found in similar designes in Virtex2 (not pro) that my phase shift to work well is larger than I waould have expected. > 2. According to my timing simulation the phase shift between the clk_dco_P > (positive side pad) and clk_dco (DCM output net) turns out to be 4.662 ns. > In functional mode I see it to be precisely 0.93 ns, i.e. equal to the > programmed fixed phase shift in the DCM. I am using Active HDL 6.3 and the > post-PAR model with the *.svf file generated by ISE6.3 for the timing > simulation. I'm not sure where 4.662 nS comes from, but it looks like the timing simulation is looking at your defined period of 4.550 (not 4.762) for clk_dco and simulating the full period of delay actually used in the DCM to lock to the input clock. You might try setting the period constraint to the exact period used in the simulation to see if this is the cause. > 3. The design is not rock solid. Despite the constraints are met, one build > might work, while another with a small irrelevant change in logic might not. > Perhaps the problem is somewhere else, but since tweaking the DCM > immediately makes the difference I tend to think that it is here. Almost always this occurs due to unconstrained paths, often for signals crossing from one related clock to another, where the tools are not smart enough to infer the required constraints from the input clock period. I have seen this in designs passing signals between 1x and 2x clock outputs from the DCM. I would turn on the "Report Uncovered Paths" option and look at the static post place-and-route timing. > 4. I have tried to read all the Xilinx guides and appnotes realted to timing > constraints under different scenarios and I get confused every time I need > to apply my knowledge. It seems especially confusing for differential > signalling... > > So, could someone please show me how this scenario should be properly dealt > with in terms of DCM settings and timing constraints and why? > Theoretically you should be able to treat the positive side of a differential input the same as a single-ended input for timing constraints. You may see that the timing report shows a difference in the datasheet numbers for setup and hold to the plus and minus inputs (by a few picoseconds), but you can't do anything to control this. > > Thanks, > /MikhailArticle: 77837
Moti wrote:
> Thanks Falk and Nicolas,
>
> the NxN array seems like a good idea - I was just looking for some
more
> elegant
> solution (like a special generate) for the code to be more readable..
> But it looks like I have no choise.
You always have a choice. For recursive hardware structures, choose
confluence:
- component pyramid +count +in -out is
- if width in == 0
- out = ''
- else
- out = {pyramid (count + 1) ('msbs' in) $} '++'
- {regs 1 count ('lsb' in) $}
- end
- end
http://www.confluent.org/
-Tom
Article: 77838"Gabor" <gabor@alacron.com> wrote in message news:1106057281.986352.279040@z14g2000cwz.googlegroups.com... > > I'm not sure where 4.662 nS comes from, but it looks like the timing > simulation is looking at your defined period of 4.550 (not 4.762) for > clk_dco and simulating the full period of delay actually used in the > DCM to lock to the input clock. You might try setting the period > constraint to the exact period used in the simulation to see if this > is the cause. I am looking well after the DCM has locked. It actually takes more than one clock cycle to lock... I don't think requested period has anything to do with this, but I will do some experiments... /MikhailArticle: 77839
> You always have a choice. For recursive hardware structures, choose
> confluence:
>
> - component pyramid +count +in -out is
> - if width in == 0
> - out = ''
> - else
> - out = {pyramid (count + 1) ('msbs' in) $} '++'
> - {regs 1 count ('lsb' in) $}
> - end
> - end
>
> http://www.confluent.org/
>
> -Tom
It's never too late to learn a new language :)
Thanks for the tip, but I think that VHDL will have to do (for now)..
Moti.
Article: 77840Has anybody tried to use the "cyclone_jtag" module in his design? So I could access registers through JTAG in my design... I know that I can use opencores jtag module but I want to use the existing JTAG port. rickArticle: 77841
Hello, i was playing a bit with bitgen, especially with bitgen -g PartialMaskXX. After examining the resulting bitstream i found a lot of writes to the FDRI-Register (followed after a write tom the FAR-Register ) with an irritating wordcount. Normally, for my V2P7 i'm writing a frame consisting of 424 bytes/106 words. The FDRI command would then look like 30 00 40 6a. But in the bitstream i was examing i saw things like 30 00 40 d4 or 30 00 40 02, indicating that 212 (2*106 ?) or only 2 words would be written. My understanding is that there must always be written a complete frame (= 106 words with my device). I'm somewhat confused about those odd numbers. Maybe one of the readers has a further understanding of the wordcount and can explain me the resulting behaviour? regards Patrick SiegelArticle: 77842
Moti wrote:
>>You always have a choice. For recursive hardware structures, choose
>>confluence:
>>
>>- component pyramid +count +in -out is
>>- if width in == 0
>>- out = ''
>>- else
>>- out = {pyramid (count + 1) ('msbs' in) $} '++'
>>- {regs 1 count ('lsb' in) $}
>>- end
>>- end
>>
>>http://www.confluent.org/
>>
>>-Tom
>
>
> It's never too late to learn a new language :)
> Thanks for the tip, but I think that VHDL will have to do (for now)..
> Moti.
>
You can also do recursive hardware in VHDL.
Although it's not as small as confluence.
Göran
Article: 77843Thanks for everyone's contributions. I've been looking on the Altera web site and found from putting figures into a cost calculator that the NRE is $195,000 with a cut in the unit cost of up to 80%. That's how I read it anyway. Rog. "Roger" <rogerwilson@hotmail.com> wrote in message news:HkzGd.179$wy.34@newsfe5-gui.ntli.net... > Does anyone know what the basic costs are of doing an Altera HardCopy > cycle? If, say I had a Stratix EP1S40 design that I wanted to make using > HardCopy, would there be an initial set cost then a low cost per device? > If so what would the costs be? > > TIA, > > Roger. >Article: 77844
\Mikhail OK, try sampling the input clock with a IOB INFF clocked from the output from the DCM. As you change the DCM shift you should see the output of the FF change polarity with the phase difference. From this you can work out the phase relationship between the input clock and output of the DCM and hence set the DCM to sample the incoming data at the right place. You probably want to use the DCM's 'dynamic change of phase input' (PSINC?) thingys, unless you like doing P&R. Cheers, Syms. p.s. Here're some more hints http://direct.xilinx.com/bvdocs/appnotes/xapp268.pdf "MM" <mbmsv@yahoo.com> wrote in message news:35357eF30ulerU1@individual.net... > "Symon" <symon_brewer@hotmail.com> wrote in message > news:352uobF4gtlijU1@individual.net... > > > > Make sure the design is using the INFFs in the IOBs. Use FPGA editor to > check. > > Yes, I have checked this.... > > > your clock is on a global resource, right? > > Sure it is. > > /Mikhail > >Article: 77845
"Symon" <symon_brewer@hotmail.com> wrote in message news:354utrF4hus7kU1@individual.net... > > OK, try sampling the input clock with a IOB INFF clocked from the output > from the DCM. As you change the DCM shift you should see the output of the > FF change polarity with the phase difference. From this you can work out the > phase relationship between the input clock and output of the DCM and hence > set the DCM to sample the incoming data at the right place. You probably > want to use the DCM's 'dynamic change of phase input' (PSINC?) thingys, > unless you like doing P&R. Symon, Do you mean to try it in simulation or in real hardware? /MikhailArticle: 77846
> > Atmel has the AT43USB380 OTG controller. > > This runs the USB host stack on an embedded micrcontroller > > and presents an API to the main processor > > which runs a library with the device classes. > > The library is delivered in object code only, so you will > > have to use a known architecture, or convince the Atmel USB > > group to support your choosen architecture. > > The AT91M40800 or the AT91R40008 are good chips to run the > > device classes on. > > Another limitation is the supported device classes. > > I think the most populoar classes are Mass Storage, HID and printer > > which are supported. CDC has been discussed some time ago, > > but I have no updated status. > > > > -- > I am also interested in finding a USB2.0 host functionality--my requirements > also include the need for vxWorks driver. The chosen chip will have to > interface to PPC405 in V2P30 via some custom IP (I'm assuming). Anyone know > of an off-the-shelf host controller with vxWorks drivers? I think that there is a PowerPC library for the AT43USB380, but I am not 100% sure. Maybe you could try mailing usb ath atmel doht com. The library will work with or without an OS so VxWorks should be fine for this chip if the PowerPC support is there. Obviously the compiler chain you use may be another parameter. I connected the team to Green Hills, so this should be one alternative. -- Best Regards, Ulf Samuelsson. Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Nordic AB.Article: 77847
> >Don't bother wasting the board space or design space on this. If you > >actually are paranoid enough that the threat of a $1M-100M lawsuit > >against someone who pirates your design is insufficient security, use > >a Cyclone II, Virtex II/IIPro, or Virtex 4, with their encrypted > >bitfile loading options. > > I just need to sell a fair security to my boss. The copyright is the > best protection IMHO, but he wants something more. Well, that's > something more and it sounds strong enough for me. The cost is minimal > compared to switching to a new device. > > Nick You can get some decent security by using FPGAs with a built in configruator, like the Secure FPSLIC, but it won't stop the three letter organisations. You have to open the package and probe the die to get to the bit stream. -- Best Regards, Ulf Samuelsson. Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Nordic AB.Article: 77848
michel leconte wrote: (snip) > My design has been P&R for two frequencies : 50 MHz and 80MHz. > In this two cases, the timing report indicates no errors > and all the timing constraints were achieved. (snip) > But at timing simulation, some differences appear. > At the lower frequency, the design responds well to the stimuli and > they were no warnings. > At 80 MHz, after my reset phasis, I see two kinds of warnings : > 1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK > 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK (snip) Setup time is how long the signal must be stable before the CLK edge, hold time is how long it must be stable after. Either can be negative but the sum must be positive. Setup violations can occur from running a design at too high a clock rate, but normally not hold violations. (That is, for a synchronous design with one clock.) As others have indicated, it is likely that you are violating the constraints on the input. If your logic family doesn't have zero hold time, you can't change the logic inputs on the clock edge. Easiest is to change them on the opposite clock edge to the one used by the FFs. -- glenArticle: 77849
Mikhail, My suspicion is that, because the design never works 100%, there's a jitter problem somewhere. So use the real hardware! Things such as an inadequately filtered Vccaux can cause this. Good luck, Syms. "MM" <mbmsv@yahoo.com> wrote in message news:354vncF4hef03U1@individual.net... > > Symon, > > Do you mean to try it in simulation or in real hardware? > > /Mikhail > >
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