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logjam wrote: > Any suggestions? I would be shaving the top off of some 16R8/4 chips. > Would heating them to around 250-300F for a while help? Shaving the > tops down while hot? I have access to 48 micron resolution digital > x-ray equipment, but no microfocus x-ray tubes at the moment, so I > don't think I would get good enough resolution by X-raying the chips. > I could try just for fun, These old PALs just might have large enough > internals. I never tried it, however it might be possible to determine the location of the fuse by a focused UV laser that is scanned over an identical part. Scan the laser and read out until the fuse is gone. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 78001
One good book that I can recomend is U. Meyer-Baese "Digital Signal Processing with Field Programmable Gate Arrays" which has an example of an ADPLL at the end of the book. Cheers, R.N.Article: 78002
Thanks Paul, Is the die shrink that's mentioned with HardCopy devices by virtue of the configuration cells being removed? I presume the feature size of the logic remains the same though so the characteristics of the logic are unchanged? Is the speed up by virtue of the logic now being hardwired? Regards, Rog. "Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:DuOdnbPTQatsxG3cRVn-rA@rogers.com... > Hi Roger, > >> Compared with a normal Stratix, is a HardCopy version immune to SEUs? > > The short answer to your question is that yes, a HardCopy device will have > no susceptability to SEUs affecting the "programming" of the device. > Configuration memory cells are replaced with hard-wired connections, thus > eliminating any possibility that the programming of the device is upset by > a > particle collision. Memory storage cells are still present in the block > memories, so I imagine that some SEU is possible in the *state* of the > chip, > as it is with any ASIC. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 78003
One other question: Am I right in thinking that the NRE for a HardCopy design is $200K? Is this fixed regardless of what the device or logic complexity of the design is? TIA, Rog. "Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:DuOdnbPTQatsxG3cRVn-rA@rogers.com... > Hi Roger, > >> Compared with a normal Stratix, is a HardCopy version immune to SEUs? > > The short answer to your question is that yes, a HardCopy device will have > no susceptability to SEUs affecting the "programming" of the device. > Configuration memory cells are replaced with hard-wired connections, thus > eliminating any possibility that the programming of the device is upset by > a > particle collision. Memory storage cells are still present in the block > memories, so I imagine that some SEU is possible in the *state* of the > chip, > as it is with any ASIC. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 78004
I reverse engineered a lot of the custom chips by Namco used in early arcade games. From the circuit diagram I had a good first guess at the logic inside, and programmed that into a cpld mounted on a 28 pin dil module with the same pinout as the asic. I then ran the game as normal with my chip in parallel with the asic (all my outputs isolated from the game) and compared the two on a logic analyser. It was then fairly simple to tweak mine to match. I also manually waggled some pins to increase the test coverage. Perhaps the same trick would work ? I really don't think they will be that complex. You can see the dev board on www.fpgaarcade.com. /Mike "logjam" <grant@cmosxray.com> wrote in message news:1106249347.233017.138400@f14g2000cwb.googlegroups.com... > I am trying reproduce a Macintosh 128k using CMOS parts. It has some > 16R4, 16R8, and 16L8 PALs. If you could give me any advice about how I > should "learn" the logic in these that would be GREAT! Maybe a method > of bit twiddling all the inputs to see what happens? The 16L8 should > be simple, but that is only one of the 6. I have signal names and a > schematic, but the internal design of the 'R' chips scares me. :) > > Is there any programmer that can use a brute force technique of trying > all possible logic combinations? > > I want to do this to learn another aspect of old computers, and because > I'd like to replace all the chips with new CMOS and see if I can't get > overclock the thing. ;) > > > Thanks for your time, > Grant >Article: 78005
I'm having some problems in simulating the power consumption of a design I worked on for university. I'm using Xilinx EDK 6.3, Xilinx ISE 6.3, Modeltech Modelsim 6.0 SE and a Spartan 3 Starter Kit. The design uses just the MicroBlaze and the controller for the SRAM on the board, it synthetizes without problems and it does what it should do, but I'm having troubles in making the results of XPower 'accurate'. Here is how I proceed: 1) creating a timing simulation from Platform Studio, 2) running ModelSim from Platform Studio 3) typing the following do system.do vsim -sdftyp system.sdf system vcd file system.vcd vcd add system/* run 2usquit -f 4) importing the generated .vcd file together with the desing .ncd file and the physical constraints .pcf file in XPower. After that XPower tells me that only 88% of the signals have been set and only 67% of the signals toggle and that the results are 'inaccurate'. I would like to have at least 'reasonable' results, is anybody able to give me a hint on how to improve the accuracy? Am I omitting something? Thanks in advance for any advice. kl31nArticle: 78006
On 21 Jan 2005 11:30:40 -0800, clehobey@orange.fr (cedric) wrote: >hi, >I'm working with ISE6.3.03i >I want to run my design at 160MHZ. So I put this contraints on my .ucf >file : >Clk = 6.25ns >Offset in = 6.25 ns; >Offset out = 6.25 ns >In my place end route report, I have 'All constraints are met". But >when I run my design wih ModelSim some Hold and Setup error occur. So >I watch the timing report (Post Place And Route). I have something >like that : > > setup hold >ARST 4.683 3.136 >ENI -0.455 3.489 >SRST 3.786 3.514 >WRCFG 1.424 4.196 >.... ... ... > >Why setup or hold could be negative? The setup time is the time the input must be stable before the clock edge. If there was a large logic delay between the signal pin and the register, the input to the part could change before the clock edge, and the delay in the logic would keep the input to the register stable until after the clock edge. The hold time should almost always be negative. If external logic changes inputs to the part right after the clock edge, and the worst case hold time is positive, then what data will be seen by the part? The data before the clock edge? Or the data after the clock edge? >How could I have a better control to my design? Design. Make all inputs registered before any logic. Make all outputs registered after any logic. If this can't be done, more care is needed. Constraints. If external logic outputs a signal after a clock edge by some delay, and the board trace delays the signal by ~80 ps/cm, and the clock to the external logic might be after the clock to the part, then the input constraint must be less than the clock period. How much less? Work it out on a signal by signal basis. Do the same for output signals. -- Phil Hays Phil-hays at posting domain (- .net + .com) should work for emailArticle: 78007
"Jecel" <jecel@merlintec.com> wrote in message news:1106269932.965110.285140@f14g2000cwb.googlegroups.com... > > Kryten wrote: >>Is the circuit diagram online? > > http://www.digibarn.org/collections/diagrams/mac-512klogicboard/index.html Is there a more legible copy available? I'm trying to sketch the logic in Orcad, and having a hard time reading some characters (like RG and RQ).Article: 78008
On Thu, 20 Jan 2005 11:29:07 -0800, logjam wrote: > I am trying reproduce a Macintosh 128k using CMOS parts. It has some > 16R4, 16R8, and 16L8 PALs. If you could give me any advice about how I > should "learn" the logic in these that would be GREAT! Maybe a method > of bit twiddling all the inputs to see what happens? The 16L8 should > be simple, but that is only one of the 6. I have signal names and a > schematic, but the internal design of the 'R' chips scares me. :) > > Is there any programmer that can use a brute force technique of trying > all possible logic combinations? > > I want to do this to learn another aspect of old computers, and because > I'd like to replace all the chips with new CMOS and see if I can't get > overclock the thing. ;) > > > Thanks for your time, > Grant Try to find an old Data IO PAL programmer. You can read out the fuse pattern from a PAL. I don't remember there being any copy protection available in PALs of that vintage.Article: 78009
Hello I'm using a Spartan-3. I'm wondering if there is an easy way to fabricate a clock with 1.8432 MHz from a 24 MHz input clock? Could I use a DCM to get this exact clock frequency? Or should I make a frequency that over a period of time has an average of 1.8432 MHz?Article: 78010
On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote: >Hello > >I'm using a Spartan-3. I'm wondering if there is an easy way to >fabricate a clock with 1.8432 MHz from a 24 MHz input clock? > >Could I use a DCM to get this exact clock frequency? > >Or should I make a frequency that over a period of time has an average >of 1.8432 MHz? Is divide by 13 not close enough...? 1.8461 would be close enough for RS232 commsArticle: 78011
Elektro wrote: > Hello > > I'm using a Spartan-3. I'm wondering if there is an easy way to > fabricate a clock with 1.8432 MHz from a 24 MHz input clock? > > Could I use a DCM to get this exact clock frequency? > > Or should I make a frequency that over a period of time has an average > of 1.8432 MHz? The answer is that you don't need 1.8432MHz. I assume you use that clock speed for your UART. Just adjust the register of divider in your UART, and it should be able to run with other clock speeds that can be easily derived from the 24MHz crystal. vax, 9000Article: 78012
"Mike Harrison" <mike@whitewing.co.uk> wrote in message news:jke5v0h4o2vfurfsv9allhdo8ir9cm3g0n@4ax.com... > On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote: > >>Hello >> >>I'm using a Spartan-3. I'm wondering if there is an easy way to >>fabricate a clock with 1.8432 MHz from a 24 MHz input clock? >> >>Could I use a DCM to get this exact clock frequency? >> >>Or should I make a frequency that over a period of time has an average >>of 1.8432 MHz? > > Is divide by 13 not close enough...? 1.8461 would be close enough for > RS232 comms 240000 / 18432 = 625 / 48 How about a 10-bit register that decrements by 48 every clock tick. Whenever it goes negative, add 625 as well and output a UART clock pulse. Alternatively, if the last clock tick sent it negative, add (625-48)= 577 on the next. I think this should give the exact average frequency, with a little jitter (edges may vary by one 24MHz clock period.Article: 78013
I've got two PALs out of an AST computer in the toaster oven upstairs. ;) Maybe these things can be cracked open to easily see the fuse patterns. I was only able to find one picture of a PAL on the internet and it looked like it was organized in a 32x64 pattern. One interesting thing I've found so far is that the my hotwired 512k actually turned out to be a 128k. I'll post some pictures in a few minutes. Its a 128k motherboard from 1983 with 4MB and a SCSI port hotwired onto pin locations on the board. This is the early 128, not the one with the 128/512 option. Since I have a 128k and 512k motherboard sitting right next to me I will trace some of the pins for you. Tell me every pin you can't see. Use the designation, like 9F, etc.Article: 78014
Jon Elson wrote: > As long as it responds correctly to the INIT/ and serial clock signals, > producing the > correct bit on the first clock pulse, etc. then anyone's SPROM will work. > There are several standards for the control of serial PROMS, so not all > of them > are compatible. The PROM has to be voltage compatible with the FPGA, as > well. > > Jon The bit order is important, the starting bit is not so important. The Xilinx devices look for a message header sequence, usually preceded in the bitstream by a bunch of 1's, to locate the beginning of the actual configuration data. Don't worry too much about missing or adding one or two bits in the beginning of the loading process.Article: 78015
These pictures may help you. Please download them to your hard drive. (Instead of downloading theme verytime.) They are full resolution images from a cheap 4 mega pixel camera. This image is the top of my 128k ONLY board modified to 4MB+SCSI. This is with the card lifted out of the sockets. http://media.diywelder.com/images3/012205-hotwired-cardlifted-top_IMGP0647.jpg This image is the top of the 128k ONLY board modified to 4MB+SCSI. You can see the NCR SCSI chip and the SIMMs. http://media.diywelder.com/images3/012205-hotwiredboardinplace_IMGP0643.jpg Here is the main difference between a 128k ONLY board and a 128k/512k board. I'll try to get some pictures of the 128k/512k board in a few minutes. You can't see the difference yet, but there will be a 128k jumper, and then a spot for the 512k with an extra 253 and some resistors. The schematic you have is for the 512k version. http://media.diywelder.com/images3/012205-sectiondifferentfrom128-512_IMGP0648.jpg Here is an interesting picture that shows the "quality" of the upgrade. ;) Look for the pal in the middle... http://media.diywelder.com/images3/012205-weirdsolderedPAL_IMGP0650.jpg More later... Are you looking at this through google groups?Article: 78016
logjam wrote: > I'm probably going to attempt a distructive test on a PLD to determine > its function. I'm wondering if anyone has tried this, and with what > success? I hope you have more than one :) > > I found this: > > "An important architectural feature that is found on virtually all PLDs > is not shown on logic diagrams. This feature is the security fuse. > Normally, the fuse pattern programmed into a PLD can, like a PROM, be > read and displayed or copied by programming hardware. Devices with a > security fuse, however, provide the ability to disable this read > function. This allows the design to be somewhat secure from attempts to > copy or reverse engineer it. > > In reality, it's relatively easy to shave the top off of a bipolar PLD > and examine the programmed fuses with a microscope. For bipolar PLDs, > then, would be copiers are merely inconvenienced. Erasable CMOS PLDs > are considerably more secure, since it's very difficult, if not > impossible, to determine their function from examination." > > From > http://www.ee.cooper.edu/courses/course_pages/past_courses/EE151/PLD1/ > > Anyone here ever "shave" a chip for examination? I have access to a > video microscope at the university. I also have a DV camcorder with DV > in, so I could take the pictures, post them, and then beg for more > help. ;) > > Any suggestions? I would be shaving the top off of some 16R8/4 chips. > Would heating them to around 250-300F for a while help? Shaving the > tops down while hot? I have access to 48 micron resolution digital > x-ray equipment, but no microfocus x-ray tubes at the moment, so I > don't think I would get good enough resolution by X-raying the chips. > I could try just for fun, These old PALs just might have large enough > internals. > > Here is a shot of a PCMCIA card, about 50% full resolution. If I did > some gemoetric magnification and used a different LUT, I might be able > to see something, but I seriously doubt it. > http://www.cmosxray.com/X-rays/newX-rays/4x4/4x4x-rays%20extra/board.JPG > > Now I'm a little more curious about the x-rays. I think I;ll go rip > apart a 286 motherboard for a PAL and do some tests this weekend. :) > > I eventually want to rewrite all of the equations for speed, but > getting a 100% copy of the OEM work was the goal. If that is the goal, why not simply reverse engineer the logic ? 16R8/4 devices are not complex, and if you also have the product circuit diagram [or application circuits of the devices], you can greatly reduce the vector-search complexity. All you need is pencil, paper, text editor, and a PLD programmer that can run test vectors (most can). -jgArticle: 78017
I just tried to log into WebCase. After clicking the "login" button, and waiting a long time, I got this message: Server Error This server has encountered an internal error which prevents it from fulfilling your request. The most likely cause is a misconfiguration. Please ask the administrator to look for messages in the server's error log. OK, so I just tried again, and this time it logged me in. I haven't used WebCase in a while, but the Xilinx web site in general seems to have been very fragile for the last six months or so. I routinely see an error page proclaiming that the web problems have been fixed, which is obviously incorrect if I get that page instead of the page I've requested. Generally repeated requests for the same URL will eventually succeed in retrieving it, so it's not due to a bad link. Are the Xilinx web servers running on inadequate hardware or something?Article: 78018
"logjam" <grant@cmosxray.com> writes:
> Anyone here ever "shave" a chip for examination?
Two friends and I read a bipolar PROM optically. It was interesting
to view it under the microscope. I'd heard that there was a long-term
problem with regrowth of the fuses, but we were actually able to see it.
Also, Peter Monta optically extracted the contents of three 2560-bit
PMOS masked ROM chips circa 1973, in order to run the code on my
simulator:
http://www.pmonta.com/calculators/hp-35/
Article: 78019How would you suggest I split my chips? I plucked 5 off of an AST motherboard and put two in the toaster oven for an hour at 300. Who knows why I did that. ;) Even if I can learn the logic, it would still be fun to see if I can see it. :) This stupid project has forced me to learn a ton of stuff in the past few days. Thats what I love, learning new useless things. ;) Can you suggest an innexpensive PAL programmer that can run a test vector?Article: 78020
It sounds like you have a (physically) working design. Why bother with a power simulation? Just measure the current, multiply by the supply voltage, and you have the real power! Peter Alfke ==================== kl31n wrote: > I'm having some problems in simulating the power consumption of a design I > worked on for university. I'm using Xilinx EDK 6.3, Xilinx ISE 6.3, > Modeltech Modelsim 6.0 SE and a Spartan 3 Starter Kit. > > The design uses just the MicroBlaze and the controller for the SRAM on the > board, it synthetizes without problems and it does what it should do, but > I'm having troubles in making the results of XPower 'accurate'. > > Here is how I proceed: > > 1) creating a timing simulation from Platform Studio, > 2) running ModelSim from Platform Studio > 3) typing the following > > do system.do > vsim -sdftyp system.sdf system > vcd file system.vcd > vcd add system/* > run 2usquit -f > > 4) importing the generated .vcd file together with the desing .ncd file and > the physical constraints .pcf file in XPower. > > After that XPower tells me that only 88% of the signals have been set and > only 67% of the signals toggle and that the results are 'inaccurate'. > > I would like to have at least 'reasonable' results, is anybody able to give > me a hint on how to improve the accuracy? Am I omitting something? > > Thanks in advance for any advice. > > kl31nArticle: 78021
Herewith the current top 10 papers in citation order, as indexed on Google scholar search. Any suggestions for a more authoritative list of key papers? Good to see a c.a.f. regular at number 2. And having a 4-letter surname seems to help, though for #3 Alberto must have enjoyed the contrast with his co-author's name length ;-) ------------------------------------- 1. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA. J Cong, Y Ding 2. VPR: A New Packing, Placement and Routing Tool for FPGA Research. V Betz, J Rose 3. Defining platform-based design. A Sangiovanni-Vincentelli, F An 4. OneChip: An FPGA Processor with Reconfigurable Logic. RD Wittig, P Chow 5. A Time-Multiplexed FPGA. S Trimberger, D Carberry, A Johnson, J Wong 6. FPGA Technology. SM Trimberger 7. NAPA C: Compiling for a Hybrid RISC/FPGA Architecture. MB Gokhale, JM Stone 8. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. KC Chen, J Cong, Y Ding, AB Kahng, P Trajmar 9. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulation. J Babb, R Tessier, A Agarwal 10. On area/depth trade-off in LUT-based FPGA technology mapping. J Cong, Y DingArticle: 78022
Cypress, TI and others have USB microcontrollers that power up with enough smarts to connect to a USB driver that would download it's application code. The microcontroller then disconnects and reconnects to the USB host which then uses another driver to talk to the final application code. These little microcontrollers are only a couple of bucks so I was thinking for FPGA applications that are always on a USB bus I could forego the serial prom and just use the USB for configuration and to talk to the fpga application through the microcontroller. I hope this makes some sense. Martin wrote: > Anyone know of a device that makes implementing USB Host mode as painless as > something like the FTDI chips? I need to hang a couple of USB Host ports on > a V2P. > > No, I don't want to implement the USB functionality within the FPGA, those > logic resources are far too valuable. Ideally, I'd like a simple > single-chip solution that requires almost zero work to get up and going. > > I do control what devices will plug into this, so it doesn't need to be as > intelligent (and/or complex?) as a full-blown USB framework on a PC. > > Thanks > > -Martin > >Article: 78023
Anyone here's got experience with xst's ERROR: cmain.c 3082:1.127.4.1. ? Answer Database is of not much help as I get it without using COREGen... lukaszArticle: 78024
I shaved an IC down with my dremel tool, ripped all the legs off, then chipped away at the remaining material, decided to shave a little more off, and finally hit the silicon, with the dremel, and further chipped on it until the IC broke in half. I didn't have a good light source, but at 400x I thought I could see some traces. Is there a substance that will break down the IC potting material but not the electronics? I noticed that the back of the silicon was coated with metal. Next I might try comming in from the back, carving around the back plane, and lifting the guy out. Forget that x-ray stuff. My in-head math was off by a few decimal places. ;)
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