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On Sat, 15 Jan 2005 00:39:43 GMT, LaesQ <laesq@nocando.com> wrote: >Hi, > >I am needing about 30 GAL22v10's for a small project I'm working on. >I've looked on most UK suppliers sites (RS, Farnell, etc.) but they want >to charge the earth (round £3 to £5) each for them. > >So I was wondering if anyone knows of a cheaper uk source. I'm looking >to pay around £1 each for them at the most. But all suggestions are >welcomed. > The atmel equivalents seem to be the cheapest. ATF22V10C-10PI at EBV at GBP 1.35 each. http://www.ebv.com The lattice GAL22V10 seems to be at least 3 to 5 times the price. EBV has got 4 sales offices in the UK. Regards Anton ErasmusArticle: 78351
Weddick wrote: > The only thing that I had put in the UCF file was the clock period. I > will > admit I don't know much about this file and what should be set. I > attached > the UCF file and help in additional settings would be appreciated. > Actually > the UCF file that I created was for the higher level project. So maybe > the settings never got flowed down? Your problem is that the inputs(rst, data_valid, ack) are not synchronized. Also I don't understand why "write" should be 'Z' some times. Also you'd better synchronize your outputs too. vax, 9000Article: 78352
Joel, I added the ucf file and added offset in of 4 ns for grins. When I went into the dreaded gate level simulation debug. I noticed that write_device_tb/uut/current_state_ffd2_94/rst write_device_tb/uut/current_state_ffd2_94/srst did not have the same delay values. I increased the testbench delay rst value to 125 ns, and it appeared to help. There may be some active reset minimum in the gate level simulation for some type of reset on configuration thingy. -Newman "Weddick" <weddick@comcast.net> wrote in message news:IaOdnWe-DuutgGDcRVn-ig@comcast.com... > The only thing that I had put in the UCF file was the clock period. I > will admit I don't know much about this file and what should be set. I > attached the UCF file and help in additional settings would be > appreciated. Actually the UCF file that I created was for the higher > level project. So maybe the settings never got flowed down? > > Joel > > > "newman5382" <newman5382@yahoo.com> wrote in message > news:rE%Kd.8455$JO2.6607@tornado.tampabay.rr.com... >> >> "Weddick" <weddick@comcast.net> wrote in message >> news:ZZOdnWsnGoUBzGHcRVn-gw@comcast.com... >>>I am just starting with VHDL and have been doing software for the last 20 >>>years. My project that I am trying to get working is part of a memory >>>controller which will allow different processes to request access to the >>>memory. >>> >>> The portion of the code that I posted works great when I do the >>> Behavioral >>> Model Simulation. When I do the post-Place & Route VHDL Model >>> Simulation >>> the first write cycle does not work. You can see that it processes >>> through the states but the data out and address lines don't change as >>> expected. >>> >>> I would appreciate any help with this problem. Hopefully it's just >>> something stupid. That always makes me feel better. >>> >>> Joel >>> >>> >> >> Joel, >> When I compiled the source to gates, and ran the simulation, I got a lot >> of timing violations. >> >> In the testbench, how do you control the set up and hold of the inputs >> to >> the uut with respect to clk? (especially data_valid, rst, ack) Do you >> constrain tbe implementation with timing constraints from a UCF file? >> >> -Newman >> >> > > >Article: 78353
On 03 Jan 2005 19:49:41 -0800, Eric Smith <eric@brouhaha.com> wrote: >Is there any reason why using an LM317S adjustable linear regulator with >1% resistors wouldn't be satisfactory for the Spartan 3 power supplies, >particularly Vccint and Vccaux? > >I have a cost-sensitive application for which the LM317S looks to be >much less expensive than using fixed-output LDO regulators, e.g., >$0.58 for the LM317S vs. $4.45 for an LP3881ES-1.2 for Vccint. > >Thanks for any advice! >Eric Have you looked at the ON Semiconductor offerings ? They have quite a few regulators, at very good prices. I use the LM1117 Series quite often. It does not have a fixed 1.2V version, but it does have an adjustable one as well. Regards Anton ErasmusArticle: 78354
Which version of Xilinx Foundation has contained PCI LogiCore for XC4000E (= version 1.2)? I have installed Foundation 4.1i, but there is PCI 32b/33MHz support for Virtex only. Thank You very very much for answere.Article: 78355
Yes Petter, I meant the Windows platform, in my initial reply. - Subroto Datta Altera Corp. <newsmailcomp5@gustad.com> wrote in message news:kjupszmu4ql.fsf@shardlow.dolphinics.no... > "Subroto Datta" <sdatta@altera.com> writes: > >> Quartus II 4.2 allows for multiple installations to co-exist on a >> computer. Prior versions of Quartus II i.e 4.1 and earlier allowed only a >> single installation to exist on a computer at any one time. When you >> install > > That must be under Windows. I have all the following versions > installed under Linux: > > quartus2-2.1 > quartus2-2.1sp1 > quartus2-2.2 > quartus2-2.2sp1 > quartus2-2.2sp2 > quartus2-3.0 > quartus2-3.0sp1 > quartus2-3.0sp2 > quartus2-4.0 > quartus2-4.0sp1 > quartus2-4.1 > quartus2-4.1sp2 > quartus2-4.2 > > I guess the problem under Windows is the global registry. > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 78356
Hi All,
I'm developing a system which will work in the irradiated area.
One of the components is the triple redundant register with asynchronous
loading from the control bus. Additionally the register's should be
refreshed
with the system clock. The control bus is asynchronous.
My implementation uses the asynchronous Clear and Preset to implement
the asynchronous loading, while Data input is used for synchronous refresh
of the register's contents.
The implementation (of single bit) for Xilinx is shown below:
======================== XILINX IMPLEMENTATION ===========================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity tripsigas is
port (
input : in std_logic;
output : out std_logic;
init : in std_logic; -- State after reset
awe : in std_logic; -- asynchronous loading
arst : in std_logic; -- aynchronous resets, prevent
-- optimizing out redundant FFs
rst : in std_logic_vector(2 downto 0); -- synchronous
resets
clk : in std_logic
);
end tripsigas;
architecture tripsig1 of tripsigas is
type my_data is array(2 downto 0) of std_logic;
signal d : my_data;
signal fclr,fset, s_output : std_logic;
signal din : my_data;
component FDCP
generic (
INIT : bit := '1');
port (
Q : out STD_ULOGIC;
C : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D : in STD_ULOGIC;
PRE : in STD_ULOGIC
); end component;
begin -- trip1
fclr <= '1' when (arst='0' and init='0') or (awe='1' and input='0') else '0';
fset <= '1' when (arst='0' and init='1') or (awe='1' and input='1') else '0';
output <= s_output;
s_output <= (d(2) and d(1)) or
(d(1) and d(0)) or
(d(2) and d(0));
g2: for j1 in 2 downto 0 generate
ff1 : FDCP
port map (
Q => d(j1), -- Data output
C => clk, -- Clock input
CLR => fclr, -- Asynchronous clear input
D => din(j1), -- Data input
PRE => fset -- Asynchronous set input
);
din(j1) <= init when rst(j1)='0' else s_output;
end generate g2;
end tripsig1;
======================== END OF XILINX IMPLEMENTATION ===============
The above implementation works perfectly.
However I also need a Actel implementation, which is shown below:
======================== ACTEL IMPLEMENTATION ===========================
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library work;
entity tripsigas is
port (
input : in std_logic;
output : out std_logic;
init : in std_logic; -- Initial state
awe : in std_logic; -- asynchronous write
arst : in std_logic; -- aynchronous resets, prevent
-- optimizing out reduntant FF
rst : in std_logic_vector(2 downto 0); -- synchronous resets
clk : in std_logic
);
end tripsigas;
architecture tripsig1 of tripsigas is
type my_data is array(2 downto 0) of std_logic;
signal d : my_data;
signal fclr,fset, s_output : std_logic;
signal din : my_data;
begin -- trip1
fclr <= '0' when (arst='0' and init='0') or (awe='1' and input='0') else '1';
fset <= '0' when (arst='0' and init='1') or (awe='1' and input='1') else '1';
output <= s_output;
s_output <= (d(2) and d(1)) or
(d(1) and d(0)) or
(d(2) and d(0));
g2: for j1 in 2 downto 0 generate
din(j1) <= init when rst(j1)='0' else s_output;
process (clk, fclr, fset)
begin -- process d
if fclr = '0' then
d(j1) <= '0';
elsif fset = '0' then
d(j1) <= '1';
elsif clk'event and clk = '1' then -- rising clock edge
d(j1) <= din(j1);
end if;
end process;
end generate g2;
end tripsig1;
===================== END OF ACTEL IMPLEMENTATION =========================
The synthesis tool (FPGA Advantage) correctly recognizes the flip/flops,
however it implements them using the C-cells, so finally the device
utilization is ca. 170% ;-).
I don't know why it is impossible to implement my redundant FF using
the R-cell, similarly to the Xilinx LPM implementation above...
According to the diagram: http://www.actel.com/documents/A54SXADS.pdf
figure 1-2, the FF's in SXA architecture features independent Preset
and Clear inputs. So why the synthesis is not able to make use of them?
Maybe I should use a special LPM-like blocks to obtain it?
--
Any help is appreciated,
best regards,
Wojtek Zabolotny
wzab@ise.pw.edu.pl
Article: 78357Is there a question in there somewhere? -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "Wojciech Zabolotny" <wzab@ipebio15.ise.pw.edu.pl> wrote in message news:Pine.LNX.4.21.0501310002210.29179-100000@ipebio15.ise.pw.edu.pl... > Hi All, > > I'm developing a system which will work in the irradiated area. > One of the components is the triple redundant register with asynchronous > loading from the control bus. Additionally the register's should be > refreshed > with the system clock. The control bus is asynchronous. > > My implementation uses the asynchronous Clear and Preset to implement > the asynchronous loading, while Data input is used for synchronous refresh > of the register's contents. > > The implementation (of single bit) for Xilinx is shown below: > > ======================== XILINX IMPLEMENTATION =========================== > library ieee; > use ieee.std_logic_1164.all; > use ieee.numeric_std.all; > library work; > > entity tripsigas is > port ( > input : in std_logic; > output : out std_logic; > init : in std_logic; -- State after reset > awe : in std_logic; -- asynchronous loading > arst : in std_logic; -- aynchronous resets, prevent > -- optimizing out redundant FFs > rst : in std_logic_vector(2 downto 0); -- synchronous > resets > clk : in std_logic > ); > > end tripsigas; > > architecture tripsig1 of tripsigas is > type my_data is array(2 downto 0) of std_logic; > signal d : my_data; > signal fclr,fset, s_output : std_logic; > signal din : my_data; > component FDCP > generic ( > INIT : bit := '1'); > port ( > Q : out STD_ULOGIC; > C : in STD_ULOGIC; > CLR : in STD_ULOGIC; > D : in STD_ULOGIC; > PRE : in STD_ULOGIC > ); end component; > >Article: 78358
Lately I've been wondering about what companies might do for design security. The question/concern has to do with team-based design work within the context of today's world where the Internet, wired and wireless networks, recordable DVD/CDR, portable hard-drives and even keychain memory sticks make it possible to move and/or have access to huge amounts of information with significant ease. The issue doesn't even have to assume maliciousness. A typical scenario might include an engineer wanting to bring work home to put in a few more hours into a difficult problem. This is not malicious, but it does move company IP out of a "secure" environment. Of course, if you assume ill intent, the scenarios abound. In general, are there simple approaches that are effective in controlling the potential exodous/migration of valuable project sources and data? This, of course, does not apply to FPGA's alone, but rather a wide range of documents and files in a development group's systems. What do companies that outsource to far-and-away places do about this? Thanks, -MartinArticle: 78359
Analysis of the Texas Instruments DST RFID http://rfidanalysis.org/ "... Our next step was to recover the secret key from a deployed DST device, using a brute-force key search. Unfortunately, it would have taken more than 2 weeks for our software implementation to find a key when running on 10 very fast PCs. We therefore implemented our key-search on a field programmable gate array (FPGA). The FPGA evaluation board we used is available online for under $200 in single quantities with all of the neccesary development software and cabling. Our implementation cracks 32 keys in parallel on a single FPGA running at 100MHz. At this rate, a single FPGA is expected to crack a key in just over 10 hours. To decrease this key-cracking time even furthur, we connected 16 FPGAs together at a total cost of under $3,500. Texas Instruments provided us with 5 DST tags whose keys we did not know. The 16-way parallel cracker was able to recover all 5 keys in well under 2 hours. ..."Article: 78360
Paul Hartke <phartke@Stanford.EDU> wrote : > The FPGA evaluation board we used is > available online for under $200 in single quantities with all of > the neccesary development software and cabling. those are XSA-3S1000 :) looks almost as cool as SaarCOR http://graphics.cs.uni-sb.de/~jofis/SaarCOR/DynRT/DynRT.html This project looks dead for a year now :( Pozdrawiam. -- RusH // http://randki.o2.pl/profil.php?id_r=352019 Like ninjas, true hackers are shrouded in secrecy and mystery. You may never know -- UNTIL IT'S TOO LATE.Article: 78361
"DJ" <reconfigurablecomputing@gmail.com> wrote in message news:1107033515.069539.84000@z14g2000cwz.googlegroups.com... > hi all > does anyone have a cracked copy of xilinx edk.... > can you help me getting it..? > Go buy a xilinx spartan3 starter kit and get the eval versionArticle: 78362
http://www.xilinx.com/products/spartan3/s3boards.htm#edk Is there any where to download the eval version of the edk if you already have a spartan3 starter kit ? AlexArticle: 78363
The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) only. The max VOH is usually not provided. Could I drive the CPLD i/o pins directly, with the LSTTL outputs? I will try to use some LVTTL to interface the CPLD, if LSTTL are not qualified. Thank you. vax, 9000Article: 78364
Andre, I assume you're inquiring about a design targeted to an FPGA. In that case usually, you don't have to do anything special to utilize I/O flip flops. You can write a general RTL sequential statement in your source code, and the synthesizer will assign an I/O flip flop if possible. Another way to do it is to explicity include a hardware instantiation of an I/O flip flop in your source code. But I hate to do that. The only time that I have run into trouble is if I have multiple clock domains, and nearly all pins are utilized. In this case, the mapper has restrictions on clock routing between neighboring I/Os. I forget the rule exactly, and it changes depending on the FPGA family you're using. But it is something like -- every 8 neigboring I/Os must share the same clock source (check your data sheet for the true relationship). Once you've synthesize your design, you can look at the summary report to see if it used I/O flip flops. Here is an example using Synplicity. -------------------- Resource Usage Report Part: lfec20e-3 Register bits: 25 of 9728 (0%) I/O cells: 19 Details: CU2: 4 FD1P3AX: 8 GSR: 1 IB: 11 IFS1P3DX: 9 OB: 8 OFS1P3DX: 8 ORCALUT4: 8 VHI: 1 VLO: 1 Found clock MY_COUNTER|clk with period 10.00ns ------------------------------ The component "IFS1P3DX" is an input flip flop. The component "OFS1P3DX" is an output flip flop. Another way to tell is to look at the results of the mapper report. Here's an example: Design Summary -------------- Number of warnings: 0 Number of errors: 0 Number of registers: 25 PFU registers: 8 PIO registers: 17 Number of SLICEs: 8 out of 9856 (0%) SLICEs(logic): 8 out of 7392 (0%) SLICEs(logic/RAM): 0 out of 2464 (0%) As RAM: 0 As Logic: 0 ----------------------------------------------------- This example shows that 17 Primary I/O registers are utilized. Hope this helps. If you need more explicit help. Send me your email, and I can mail you the complete example, including source code, synthesis results, and mapper results. Regards GaryArticle: 78365
Hi, The v1.2 PCI LogiCORE was shipped on CD-ROM, and for a time was available for download (but no longer). The Xilinx PCI cores have not traditionally been part of the implementation tools until just recently when they were made available through Core Generator. The specific version you are looking for will only work with XACT6, which is substantially older than Foundation 4.1i. I'm assuming you asked this question because you have some XC4000E hardware sitting around and want to use it. My advice would be to sell it on eBay and use the money to buy one of the inexpensive boards from a Xilinx distributor or the FPGA4FUN website. You'll then need to install ISE6 (WebPack will do...) and get an eval copy of the v3.0 PCI LogiCORE. Or maybe just post again, asking for a cracked copy. :) Good luck, Eric SimonX wrote: > > Which version of Xilinx Foundation has contained PCI > LogiCore for XC4000E (= version 1.2)? I have installed > Foundation 4.1i, but there is PCI 32b/33MHz support > for Virtex only. Thank You very very much for answer.Article: 78366
Hi, Wojciech Zabolotny wrote: > I'm developing a system which will work in the irradiated area. > One of the components is the triple redundant register with asynchronous > loading from the control bus. Additionally the register's should be > refreshed > with the system clock. The control bus is asynchronous. Why not using a RT54SX (Of course its a big difference in price)? It has the FF already TMR, and you got also a protected reset and clock path. When using the A54SX you will have trouble protecting Reset and Clock. If you need a specific element, why not instanciating it by hand? bye Thomas -- Emailantworten bitte an thomas[at]obige_domain. Usenet_10 ist für Viren und Spam reserviertArticle: 78367
Brian Davis wrote: > If driving a Xilinx 2.5V LVPECL input from an external > 3.3V LVPECL driver, there's a good chance the driver output > swings will exceed the specified Xilinx input common mode range- > I'd either AC couple with a bias network (for a continuous clock) > or use a resistive level shifter. > > Besides XAPP696, see also: > - Answer Record 16830 > - http://www.onsemi.com/pub/Collateral/AN1568-D.PDF Thanks a bundle for this. Really handy to have it all in one document. And thanks for clearing up some of my doubts. :) cu, SeanArticle: 78368
I am getting the below error when i perform a post layout simulation from Xilinx using Modelsim. I am sure the $width problem has been discussed in this forum before. But i was wondering why Modelsim looks for the X_LATCHE in the C directory when I have installed them in D. I was wondering where and how to change it. # ** Error: C:/XILINX/verilog/src/simprims/X_LATCHE.v(48): $width( posedge SET:211374 ps, :211864 ps, 1570 ps ); # Time: 211864 ps Iteration: 2 Instance: /tb/dpackt/correlator_packet_detected_5242 Thank you in advance.Article: 78369
I have been trying for some time to get an IP I wrote hooked to the MicroBlaze. I am not immensely proficient with vhdl. I do most with schematics. Does any one know where one could get an example of interfacing a simple IP to user register opb ipif using schematics? I have all the signals generated and the IP works, but when I try to combine it with the files generated by the wizard I am getting errors I can't resolve. fas3Article: 78370
My approach to this problem where I do carry my current projects around on a usb flash memory stick is to encrypt all the files with pgp which basically means that if I do loose the thing or have it stolen at anytime no data falls into the wrong hands and I simply use my back-up data and carry on from before.Article: 78371
Hi , I have general question regarding the Master Serial Programming mode . In the Master Serial Programming mode , FPGA drives the clock . But ,how will the FPGA know that there is relevant and complete data present on the PROM . Is there any mechanism to tell the FPGA that the configurable data is present on the PROM and FPGA to initiate the clock. Thanks in Advance , SowjanyaArticle: 78372
I think Nick Weaver recently suggested the best method. Sue anyone who steals your stuff. It's illegal. Cheers, Syms.Article: 78373
>> in the end I should just add all my values to the sensitivity list, so >> that the synthese tool is happy? > > Consider using synchronous processes. The reason being I belive that then you can just have the clock in the sensitivity list (and reset if asynch reset). As long as all logic statements are wrapped in a "if (clk'event and clk=1)" then simulation and synthesis results (in terms of logic) should be the same and any "missing signals from sensitivity list" warnings can be safely ignored (as far as I am aware...) Cheers, KenArticle: 78374
"Alex Gibson" <me@privacy.net> wrote in message news:365ps8F4sc51gU3@individual.net... > http://www.xilinx.com/products/spartan3/s3boards.htm#edk > > Is there any where to download the eval version of the edk > if you already have a spartan3 starter kit ? > > Alex > or to get an evaluation cd ?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z