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I would like to share the following, Lattice made available for me a new fixed version of the ISC BSDL file. With it it's possible to program and re-program the Lattice CPLD via the Xilinx parallel cable and WebPack (iMPACT). Burkhard "Burkhard Schermer" <bschermer@addcom.de> schrieb im Newsbeitrag news:ckmnp5$4h6$03$1@news.t-online.com... > Hi all, > I tried to program a Lattice CPLD LC5512MB via the Xilinx parallel cable > by using Xilinx iMPACT in batch mode with an ISC-file. The programming > perfectly worked with an empty CPLD but if the CPLD already was programmed > , strange things was happened - all Bits was programmed with zeros. It > looks like as the ERASE OpCode in the LATTICE 1532-BSDL-file would not > work. > Does somebody know a solution? > > Thanks and regards > Burkhard >Article: 74976
Rakesh Sharma wrote: >Hi, > > I am getting the following error in Xilinx:- > >Annotating constraints to design from file "musicmp3.ucf" ... >ERROR:NgdBuild:755 - Line 2 in 'musicmp3.ucf': Could not find net(s) 'rxd' in > the design. To suppress this error use the -aul switch, specify the correct > net name or remove the constraint. >ERROR:NgdBuild:755 - Line 4 in 'musicmp3.ucf': Could not find net(s) 'clk' in > the design. To suppress this error use the -aul switch, specify the correct > net name or remove the constraint. >ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. >ERROR:NgdBuild:19 - Errors found while parsing constraint file "musicmp3.ucf". > >Writing NGDBUILD log file "musicmp3.bld"... > > >The UCF file looks like :- > >#PACE: Start of Constraints extracted by PACE from the Design >NET "rxd" LOC = "P202" ; >NET "pwm_output" LOC = "P110" ; >NET "clk" LOC = "P80" ; > > >The code goes like this :- > >library IEEE; >use IEEE.STD_LOGIC_1164.all; >use IEEE.std_logic_arith.all; >use IEEE.std_logic_misc.all; >use work.functions.all; > > >ENTITY musicmp3 IS > PORT ( > clk : IN std_logic; > RxD : IN bit; > PWM_output : OUT bit); >END musicmp3; > >ARCHITECTURE translated OF musicmp3 IS > > COMPONENT async_receiver > PORT ( > clk : IN std_logic; > RxD : IN bit; > RxD_data_ready : OUT bit; > RxD_data : OUT bit_vector(7 DOWNTO 0); > RxD_endofpacket : OUT bit; > RxD_idle : OUT bit); > END COMPONENT; > > > SIGNAL RxD_data_ready : bit; > SIGNAL RxD_data : bit_vector(7 DOWNTO 0); > SIGNAL RxD_data_reg : bit_vector(7 DOWNTO 0); > SIGNAL tmp : bit_vector(7 DOWNTO 0); > SIGNAL PWM_accumulator : bit_vector(8 DOWNTO 0); > SIGNAL PWM_output_xhdl1 : bit; > > >BEGIN > PWM_output <= PWM_output_xhdl1; > deserialer : async_receiver > PORT MAP ( > clk => clk, > RxD => RxD, > RxD_data_ready => RxD_data_ready, > RxD_data => RxD_data); > > > PROCESS > BEGIN > WAIT UNTIL (clk'EVENT AND clk = '1'); > IF (RxD_data_ready = '1') THEN > RxD_data_reg <= RxD_data; > END IF; > END PROCESS; > > > PROCESS > VARIABLE s : BIT_VECTOR(7 downto 0); > VARIABLE DInt : INTEGER := 0; > VARIABLE EInt : INTEGER := 0; > BEGIN > WAIT UNTIL (clk'EVENT AND clk = '1'); > -- PWM_accumulator <= "0" & PWM_accumulator(7 DOWNTO 0) + RxD_data_reg; > > s := PWM_accumulator(7 DOWNTO 0); > DInt := to_integer(s); > EInt := to_integer(RxD_data_reg); > > DInt := DInt + EInt; > > PWM_accumulator <= to_bit(9, DInt); > > END PROCESS; > PWM_output_xhdl1 <= PWM_accumulator(8) ; > >END translated; > > >What can be wrong? Thanks in advance > > Assign a signal to the output and the optimizer won't remove your logic. You must have an error saying your FPGA is empty. Regards ThomasArticle: 74977
Hi,
I am trying to port the NIOS2 flash programmer to a new development board,
but have the following problems:
1-if i add EPCS serial flash controller to the SOPC builder, it generates an
error, " chip designator not right" and exits with error.
with the "mk-target-board" utilty i have however entered a chip designator
("U2")????
If i put the ASMI ctrl in instead of the EPCS controller i can generate a
new custom board.!!!!!
Also if i run the EPCS serial ctrl wizard i cannot edit the chip designator
, it keeps the one i entered with the "mk_target_board" utilty.
2- Once i have generated the new custom board and i compile my project (SOPC
builder set to the new custom board) i can generate the project witout
problems. When i setup the flash programmer in the "NIOS2 IDE" everything
goes smooth, but when i start programming the onboard flash, i get the
following error message :
make: *** No rule to make target `programflash'. Stop.????
Can somebody help me out.
Regards
Ron Proveniers
www.info-trade.nl
Article: 74978Moti Cohen wrote: >Hi all, >firstly I would like to thank all of you guys for answering.. > >here are some more facts, before posting my questions I've made the following.. >(with no sucsess). > >Multi clocks - my design is indeed using few clock sources but each of them is >driving a speperate block (i.e. only one clock is driving the data in/out of a >single FSM). > >Async reset: >before I've encountered the problem I used an async reset such as > >process (resetn,clk) >begin > if resetn ='0' then > ... > elsif rising_edge(clk) then > ... > >but when the unstabilty problem has rised I immidiatly changed all my design to > >work on a sync reset such as > >process (resetn ,clk) >begin > if rising_edge(clk) then > if resetn ='0' then > .... > else > ... > >but it did not helped me .. > >undesired Latch inferences: >I also searched my entire design for warnings about latch inferences or some >other warning that might indicate regarding an un-intentioned logic >implementation (I found one warning regarding a latch, fixed it but the problem >didnt "died"). > >Gated clocks - I dont think that I'm using them but I would be very happy if >someone will give me a VHDL code example that will cause a gated clock. so I >can be sure what you guys ment by "gated clock". > >Simulation - I'm not fimiliar with the term "sky-wire" (mentioned by chris) >maybe someone can explain what's the meaning of it. > >FSM encoding: I also changed my FSMs encoding to GRAY instead of "one hot" >beacuse from ny past experinse in some cases it helps (but it didnt help). > >synthesis - Chris mentioned that even the same code could be synthesized >differntly on each synthesis. In my case it's no so! I use Source safe for >version control and save a version of every "good" synthesis and I saw that >whenever I synthesize a code that has worked before it's always continuing to >work. > >In the past when I encounterd such problems I used the ChipScope LA to find & >debug them but now the problem is moving from block to block and the chipscope >itself when used is also changing the logic (using the device LUTs and RAM >resources) so I can't realy use it. > >I didnt tried yet to run the entire design on a lower frequency rate, that was >a good sugesstion and I will try it. I will also try to "play" a little with >power supply and with the temperature.. > >I was wondering if something in my syntheis/MAP/P&R configuration is wrong >maybe you can throw me few tips on this subject too (I'm using Xilinx project >navigator 6.1 with XST). > >again, lots of thanks. >Regards, Moti. > > Do not know if this was addressed before. Do you use a four layer PCB carefully decoupled with capacitors? Is your ground bounce ok? Do you have contentions on your board? Did you try to put the outputs into slow smooth switching mode? It looks to me like you switch off a bank by switching and the result depends on what is fitted into this bank. Regards ThomasArticle: 74979
I am targetting an S3 and need a VCXO. This can be done by permanently rotating the delay in the DLL. Unfortunately the DLLs in S3 do not wrap (IIRC). Is there another option than interleaving two DLLs and spool the second towards the oposite end and switch on the overflow on the first. Example: The first one goes towards the max delay end. The second one is spooled to minimum. On overflow the clock will be swittched to the second one. (uh, it's frighting me!). Thanks ThomasArticle: 74980
Hello, I want know if it is possible co-simulate with hardware-in-loop the xtremedsp kit II, if I use ADC and DAC. Always that I try genarate, the program make error. TonnyArticle: 74981
Thomas, We did this to prove a point (that we could do clock and data recovery by such a scheme). So while you advance one DLL phase, the other is waiting at its minimum (or maximum) until you are about to (undeflow) overflow. Then you switch DLLs (using a BUFGMUX) and trade roles for the DCM's (one is now the source of the clock, and the other is set to max or min based on the direction you wish to move the phase). It gave a number of folks a headache here as well, but it did work, and was able to act as CDR to recover data from a 270 Mbs data stream. My thought was to always have one DLL be a mirror of the other (if one advances, the other goes back) so that when you reach 0, the other is at max, and if you reach 255, the other is at 0, and use the BUFGMUX to switch between them when you need to. They ended up not doing it that way, but I saw no reason why not. Maybe they hit on a simpler control scheme their way. This does not make a VCXO however (always get the same frequency out). Austin Thomas Rudloff wrote: > I am targetting an S3 and need a VCXO. This can be done by permanently > rotating the delay in the DLL. > Unfortunately the DLLs in S3 do not wrap (IIRC). > > Is there another option than interleaving two DLLs and spool the second > towards the oposite end and switch on the > overflow on the first. > > Example: > The first one goes towards the max delay end. The second one is spooled > to minimum. On overflow the clock > will be swittched to the second one. (uh, it's frighting me!). > > Thanks > ThomasArticle: 74982
Hy! I would like to make board with Spartan2 (exactly XC2S50-5PQ208), and that FPGA must be configured in master serial mode using serial EPROM, exactly M25P10. Does anybody know how to use serial EPROM M25P10 for configuring my FPGA without using microcontroller or CPLD?? Problem is when I cleared configuration memory in FPGA, and configuration pins are set in master serial mode, is there any way how to explain to FPGA from which address in PROM, FPGA must start reading configuration memory?? Thanks Ivan KoprivnicArticle: 74983
When will the design sources for the ML401 demo projects be available? ThanksArticle: 74984
searchfordesignservices@hotmail.com (Anom) wrote : > Hi, > > For a quite large project dealing with Virtex 4, DDR2, gigabit > ethernet and digital signal processing, I'm looking for a top of the > bill design house in a far east country like india. > > All tips are welcome. tip one - avoid India and China Pozdrawiam. -- RusH // http://randki.o2.pl/profil.php?id_r=352019 Like ninjas, true hackers are shrouded in secrecy and mystery. You may never know -- UNTIL IT'S TOO LATE.Article: 74985
Austin Lesea wrote: > Thomas, > > We did this to prove a point (that we could do clock and data recovery > by such a scheme). > > So while you advance one DLL phase, the other is waiting at its > minimum (or maximum) until you are about to (undeflow) overflow. Then > you switch DLLs (using a BUFGMUX) and trade roles for the DCM's (one > is now the source of the clock, and the other is set to max or min > based on the direction you wish to move the phase). Exactly! > > It gave a number of folks a headache here as well, but it did work, > and was able to act as CDR to recover data from a 270 Mbs data stream. You will have to spend a lot of time to find a save switching point in either case. > > My thought was to always have one DLL be a mirror of the other (if one > advances, the other goes back) so that when you reach 0, the other is > at max, and if you reach 255, the other is at 0, and use the BUFGMUX > to switch between them when you need to. They ended up not doing it > that way, but I saw no reason why not. Maybe they hit on a simpler > control scheme their way. > That's a good idea. It takes less resources to do that. > This does not make a VCXO however (always get the same frequency out). Of course, you need to permanently increase/decrease phase. Thanks a lot. And please tell your developers that a wrap option can be very useful in new devices. ThomasArticle: 74986
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:fX5ed.30157$z77.27796@news.chello.at... > <is about Anttis NIOS clone> > >> So, either it's available, or it's not. What's it to be? > >> > >> John > > http://ipcores.openchip.org > > > > Hi Antti, > > isn't 'Please ask for pricing' on a website with 'openchip' in the domain name a little bit > controversial ;-) > I know, providing the source code of a processor for free download to be 'open-source' > AND trying to sell the design is an unusual and problematic (or better no) business model. > > Martin Hi Martin, "open" doesnt have to mean that everything is free. For all designs and ip cores copyrighted to openchip - the sources are available, but not necessarily for free. Also in my opinion several "open source licenses" are in many ways more restrictive then commercial licenses. So as example if I would make NIOX GPL it would prevent you using it in commercial products without re-releasing the modified source and possible your own ip as well. If you OTOH "buy" NIOX source code you are not bound to such restrictions and can make profit anyway you like. One of most problem with www.opencores.com is that the regulations there make it real hard for the developers to benefit. So openchip licensing is more flexible - make money and what more important allow others to make money too. So the others will have more time to play with their children (or have fun the way the like it). Yes I have put "ask for pricing" - but did you ask? Maybe the price is $1 for you? Notice I might sell it for $1 to Martin - but under specially taylored license. All you have to do is ask :) Buying (if that option is available) is in many cases better and cheaper than "getting for free". If you pay for something you are entitled to some supprot (or money back) - getting for free means usually no support (and nobody pays for your time you wasted because of lack of support). Also selling something "enforce" more feedback then giving away for free. And without feedback its really hard to find bugs and improve a product. As example my MicroBlaze/uCLinux free version has been available for downloads for several weeks, and there is ZERO feedback yet. Nothing. AnttiArticle: 74987
"Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message news:9-CdnbnwkbUxZuXcRVn-oA@rogers.com... > Hi Leon, > > > This would make a nice toy for the desktop: > > > http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools > > Yes, it does. It makes a great clock or stock ticker when not being used to > try out a design. Very snazzy. > > Paul Leventis > Altera Corp. Any documentation about this thing available without buying it ?? Antti PS I have NIOS II working in APEX 1K30 (using my own NIOS II compatible IP Core)Article: 74988
Jan Gray wrote: > In Virtex-derived architectures, you can implement > o = add ? (a + b) : c; > or > o = sel ? (a + b) : (a + c); > or even > o = addsub ? (addand ? a+b : a-b) : (addand ? a&b : a^b); > in one LUT per bit. > > The trick is to use a MULT_AND to kill the carry propagation when add=0. > See http://www.fpgacpu.org/log/nov00.html#001112. > > But as Philip points out, you'd need five input signals to do > o = sel ? (add ? a + b : a - b) : c; > and I don't think that can be done in one LUT per bit. After rechecking more closely, I better understand. More generaly : o = addsub ? (add_aux ? a+b : a-b) : ( F(a,b,add_aux) ) with F(a,b,add_aux) any function ... Solutions would be to either not load from a third bus but implement a load operand A or load operand B (even both, selecting which to load via add_aux). Also, depending on where the the load operand comes : If it comes from a mux and that mux has a 'spare' input, connect that spare input to every time the add or sub selector. Then send the load via add_aux signals. When add_sub is used, on your mux, use the add or sub signal. SylvainArticle: 74989
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> writes: > I think you will find that you need to do a web install at present to get > all the devices. That wasn't the question. The OP was referring to the fact that the downloadable WebPACK 6.3i is stated to support Spartan 3 up to XC3S1500, yet he says that the pull down menu included the 2000 and 4000 as well. The ISE 6.3i evaluation and BaseX installations from CD apparently only suuport Spartan 3 up to XC3S400. I haven't confirmed any of this personally. I'm using the downloaded WebPACK 6.3i for XC3S200 designs (using the Spartan 3 Starter Board), and it works fine for that.Article: 74990
Antti Lukats wrote: > > Antti > www.openchip.org/bootx > configuration from MMC card, uses 21 PLD cells !:) I've noticed that your posts here always seem to show a time a few hours ahead of when I am reading them. I checked the source in the post and your time zone is set to -7 hours, which is west coast US (Microsoft HQ). I am pretty sure you told me you are in Europe somewhere. I guess your time zone needs to be set to your local time? I belive the same is true for Mike Harding... :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74991
Sylvain Munaut wrote: > Hello, > > > In another topic, I discovered that there was no internal 3-state buffer. > So, how should I do it if I have let's say 1 master and n slaves on a bus. > The master puts an address, and then can either read or write from the > slave. > > 1 bi-dir bus don't seem like a good choice ... > So with a din & dout from the master : No problem for dout, only the > masters drivers it. But for din, multiples slaves would like to drive it > ... > > I could use a multiplexer for din but it mayu grow quickly ... > > > What's the common way of doing this ? > > The context is a PCI target core that translates single IO request to > request to that internal bus, then different cores expose theirs regs thru > it. > > > > Sylvain Look at teh wishbone bus spec on www.opencores.org That is the internal bus standard my company uses. EricArticle: 74992
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4179B9F4.881AF358@yahoo.com... > Antti Lukats wrote: >> >> Antti >> www.openchip.org/bootx >> configuration from MMC card, uses 21 PLD cells !:) > > I've noticed that your posts here always seem to show a time a few hours > ahead of when I am reading them. I checked the source in the post and > your time zone is set to -7 hours, which is west coast US (Microsoft > HQ). I am pretty sure you told me you are in Europe somewhere. I guess > your time zone needs to be set to your local time? > > I belive the same is true for Mike Harding... :) > I thought Mike was somewhere here in Australia which should be +10 UTC (For Sydney / NSW and Vic) According to whois on graphord.com or openchip.org Antti is in Clausthal-Zellerfeld , Lower Saxony You forget how much info a whois search gives. AlexArticle: 74993
Alex Gibson wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:4179B9F4.881AF358@yahoo.com... > > Antti Lukats wrote: > >> > >> Antti > >> www.openchip.org/bootx > >> configuration from MMC card, uses 21 PLD cells !:) > > > > I've noticed that your posts here always seem to show a time a few hours > > ahead of when I am reading them. I checked the source in the post and > > your time zone is set to -7 hours, which is west coast US (Microsoft > > HQ). I am pretty sure you told me you are in Europe somewhere. I guess > > your time zone needs to be set to your local time? > > > > I belive the same is true for Mike Harding... :) > > > > I thought Mike was somewhere here in Australia > which should be +10 UTC (For Sydney / NSW and Vic) > > According to whois on graphord.com or openchip.org > Antti is in Clausthal-Zellerfeld , Lower Saxony > > You forget how much info a whois search gives. I wasn't talking about where he was (except I was pretty sure it was not Redmond WA). I am talking about having his time zone set wrong... I notice you have yours set right. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 74994
"kopriva" <ivan.koprivnic@mail.inet.hr> wrote in message news:clbt9i$dkt$1@sunce.iskon.hr... > Hy! > I would like to make board with Spartan2 (exactly XC2S50-5PQ208), and that > FPGA must be configured in master serial mode using serial EPROM, exactly > M25P10. Does anybody know how to use serial EPROM M25P10 for configuring my > FPGA without using microcontroller or CPLD?? > Problem is when I cleared configuration memory in FPGA, and configuration > pins are set in master serial mode, is there any way how to explain to FPGA > from which address in PROM, FPGA must start reading configuration memory?? NO WAY! only Altera Cyclone I/II, Stratix-II and Lattice EC can load itself from 25P10 style memories without the use of microcontroller or PLD. Antti www.openchip.org/bootx configuration from MMC card, uses 21 PLD cells !:)Article: 74995
Hi Andrea Oh Silly Me! Thanks a million for your help. Denis "Andrea Sabatini" <andrea@dapdesign_N_O_S_P_A_M_.com> wrote in message news:<4178e4ce$0$10528$e4fe514c@news.xs4all.nl>... > denis, > > i think there is an error in the instantiation of the module called > comisn1_Top at the following line: > > > comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk); > > infact the port called Read_Trigger_Address_Clk is assigned to TOP_Main_clk > that is the same clock used for the register called > Int_Read_Trigger_Address_Clk. in this case the clock will sample itself and > it will always be 1. > > andrea > > > "Denis Gleeson" <dgleeson-2@utvinternet.com> wrote in message > news:184c35f9.0410220130.5de8185@posting.google.com... > > Hello All > > > > I have a problem with my simulation. > > Can some one tell me whats wrong. It may be in my test bench as Im no > > expert. > > I have reduced the verilog so that its at its simplest. > > > > What I find is that a signal which should be toggling in sequence with > > the clock in my test bench is just not doing so. > > > > Its the signal Int_Read_Trigger_Address_Clk in the module code. Its > > just going high when the clear line goes low. > > > > Its so simple I cant believe its not working. > > > > Please have a look below. > > > > ------------------------- This is the test bench > > -------------------------- > > > > `timescale 10ns/10ns > > > > module Comisn_24_tst; > > // Set up local variables for passing parameters to the device under > > test. > > // INPUTS > > reg TOP_Main_clk; > > reg TOP_clear; > > reg TOP_Read_Trigger_Address_Clk; > > > > comisn1_Top DUT ( TOP_Main_clk, TOP_clear, TOP_Main_clk); > > > > initial // Test stimulus > > begin > > // Set initial values for all module inputs. > > TOP_Main_clk = 0; > > TOP_clear = 1; > > TOP_Read_Trigger_Address_Clk = 0; > > // Set clear line low . > > #50 TOP_clear = 0; > > #50000 $stop; > > end > > > > initial // Clock generator > > begin > > TOP_Main_clk = 0; > > forever #10 TOP_Main_clk = !TOP_Main_clk; > > end > > > > always begin > > #10 TOP_Read_Trigger_Address_Clk = !TOP_Read_Trigger_Address_Clk; > > end > > > > initial > > $monitor($stime,,, TOP_clear,,, > > TOP_Main_clk,,,TOP_Read_Trigger_Address_Clk); > > endmodule > > > > ------------------------- This is the module > > ----------------------------- > > > > module comisn1_Top (Main_clk, clear, Read_Trigger_Address_Clk ); > > > > input Main_clk; > > input clear; > > input Read_Trigger_Address_Clk; > > > > reg Int_Read_Trigger_Address_Clk; > > > > ///////////////////////////////////////////////////// > > // First Off Synchronise all external signals to > > // the main clock for the system. > > ///////////////////////////////////////////////////// > > always @ (posedge Main_clk or posedge clear) > > begin > > if(clear) > > begin > > Int_Read_Trigger_Address_Clk <= 1'b0; > > end > > else > > begin > > Int_Read_Trigger_Address_Clk <= Read_Trigger_Address_Clk; > > end > > > > end > > > > endmodule > > ---------------------------------------------------------------------- > > > > Many thanks for any help in advance. > > > > Regards > > DenisArticle: 74996
On 22 Oct 2004 08:39:39 -0700, searchfordesignservices@hotmail.com (Anom) wrote: >For a quite large project dealing with Virtex 4, DDR2, gigabit >ethernet and digital signal processing, I'm looking for a top of the >bill design house in a far east country like india. > >All tips are welcome. Following recent (second hand) experience of designs done in India my tip is; try Australia then Europe or the USA, in that order :) Mike HardingArticle: 74997
> > > > > Do not know if this was addressed before. Do you use a four layer PCB > carefully decoupled with capacitors? > Is your ground bounce ok? Do you have contentions on your board? Did you > try to put the outputs into slow > smooth switching mode? - I'm using a 10 layers PCB and I believe that I decoupled the voltage supply inputs as needed ( three levels of capcitors values). - I dont have any contentions on the board (I tested it on several boards) - and the current consumption is o.k. + the chip does not warm up + the same pin assignment file is used in cases when the chip does works. - I guess that by "smooth switching mode" you mean "Slow slew rate" so at the begining I did tried to set the outputs to slow slew rate but without any success. I didnt checked for ground bounces - but my design does not contains many outputs that change on the same time and along with using slow slew rate outputs I hope that I should not worry about ground/VCC bouncing problems. > It looks to me like you switch off a bank by switching and the result > depends on what is fitted into this bank. I'm not sure what you meant by "switching off a bank" I will be glad if you explain it.. Thanks again, Moti.Article: 74998
Paul Leventis (at home) wrote: > Hi Leon, > > >>This would make a nice toy for the desktop: >> > > http://www.shopaltera.com/category.asp?catalog%5Fname=ALC&category%5Fname=Demo+Tools > > Yes, it does. It makes a great clock or stock ticker when not being used to > try out a design. Very snazzy. > > Paul Leventis > Altera Corp. I may be slow today, but the web site doesn't seem to have any details about this thing or a large picture. I assume it has some IO other than a USB cable? Does it light up? Can you shake it and watch the snow fall?Article: 74999
Pete, To what are you referring? If you can detail what you are looking for, maybe we can help you? Austin Pete Fraser wrote: > When will the design sources for the ML401 > demo projects be available? > > Thanks > >
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