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I am working on synthesizing some legacy code, and Synplify (correctly)
finds a combinatorial loop in the logic. My gut reaction was to modify the
function to use a latch instead of a feedback path because I've always been
told that combinatorial loops are bad practice for ASICs / FPGAs. After
completing the redesign, the new circuit takes up at least twice as much
space as the old one and it is difficult to exhaustively verify that the
re-implementation preserves the functionality.
The combinatorial loop implementation is in a product, and has been working
without problems (presumably) for years. So the question I would like to
present for discussion is:
Why is it so bad to use combinatorial loops? What are the potential
pitfalls?
I would be interested in hearing this issue addressed from an ASIC design
point of view as well.
For reference, I am including below a testbench I created to test the
various implementations. The first two process represent the original
implementation and create the OutA output. The 3rd and 4th processes
represent the latch based implementation. The 5th process is an (almost)
exhaustive testbench to verify that the two implementations behave the same
way.
Thanks
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test IS
END ENTITY test;
ARCHITECTURE test_arch OF test IS
SIGNAL Latch : STD_ULOGIC;
SIGNAL In0 : STD_ULOGIC;
SIGNAL In1 : STD_ULOGIC;
SIGNAL In2 : STD_ULOGIC;
SIGNAL In3 : STD_ULOGIC;
SIGNAL InternalSig : STD_ULOGIC;
SIGNAL OutA : STD_ULOGIC;
SIGNAL OutB : STD_ULOGIC;
SIGNAL TestVector : UNSIGNED(3 DOWNTO 0);
BEGIN
proc1 : PROCESS (In1, In2, OutA) IS
BEGIN
IF (In1 = '1' OR
(In2 = '1' AND OutA = '1')) THEN
InternalSig <= '1';
ELSE
InternalSig <= '0';
END IF;
END PROCESS proc1;
proc2 : PROCESS (In0, In3, InternalSig) IS
BEGIN
IF (In0 = '1' AND
(In3 = '1' OR InternalSig = '1')) THEN
OutA <= '1';
ELSE
OutA <= '0';
END IF;
END PROCESS proc2;
proc3 : PROCESS (In0, In3, In1, In2, Latch) IS
BEGIN
IF (In0 = '0') THEN
OutB <= '0';
ELSE -- IF (In0 = '1') THEN
IF (In2 = '0') THEN
OutB <= In3 OR In1;
ELSE -- IF (In2 = '1') THEN
OutB <= Latch;
END IF;
END IF;
END PROCESS proc3;
proc4 : PROCESS (In0, In3, In1) IS
BEGIN
IF (In0 = '0') THEN
Latch <= '0';
ELSIF (In3 = '1' OR In1 = '1') THEN
Latch <= '1';
ELSIF (In2 = '0' AND In1 = '0') THEN
Latch <= '0';
END IF; -- note that there is no else statement here, thereby inferring
a latch
END PROCESS proc4;
stim : PROCESS IS
BEGIN
FOR i IN 0 TO 15 LOOP
TestVector <= to_unsigned(i, 4);
WAIT FOR 1 ns;
ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error;
FOR j IN 0 TO 3 LOOP
TestVector(j) <= NOT TestVector(j);
WAIT FOR 1 ns;
ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error;
END LOOP;
END LOOP;
WAIT;
END PROCESS stim;
In0 <= TestVector(0);
In1 <= TestVector(1);
In2 <= TestVector(2);
In3 <= TestVector(3);
END ARCHITECTURE test_arch;
Article: 73426Hang on a minute! Legal redress? I'm not by any means defending FUD or marketing crap on CAF, but let's get things in perspective. He was on topic, he said who he was, he said what his job is (was?!). It's not as if he's been doing it day in, day out for months. Looks like he posts via Google Groups, so he won't have seen the responses this morning yet. Maybe he should have some right of reply/opportunity to explain before he gets the Spanish Inquisition! Remind me, what was the first amendment? ;-) Cheers, Syms. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:cipsa0$m5b$1@gnus01.u.washington.edu... > > Luc wrote: > > > Get rid of the spammer! Pls leave this ng to the technician and his > > daily issues. > > Figure out how to get rid of spammers, and the whole world will > love you. I get hundreds of spam e-mails a day, mostly real junk > although one today wants to sell me a Virtex 4 kit. > > In this case we know where he works, and probably where he lives, > so we could do something about it. (Legal, that is.) > > > -- glen >Article: 73427
All, I'm building a prototype board and I've the opportunity to try out a few things. One idea I've toyed with is being able to communicate with an FPGA using Ethernet. I've looked at Jean P. Nicolle's site, www.fpga4fun.com , and he's done some interesting stuff. Anyway, I've not got much time for research, my plan is to layout an RJ45 with integrated magnetics, bias the Virtex2P FPGA side to about 1.2V and try to communicate using the LVDSEXT I/Os. I'll put a balanced termination resistor network between the RJ45 and the FPGA. I notice you can get RJ45's with USB connectivity. JW0-0009 from www.pulseeng.com so I'll wire the USB up to the FPGA as well, in the hope that I might be able to drive a USB pen drive at some point. I'll connect 5V to the USB power pins, and two 3.3V Vcco FPGA pins to the USB signal pins with the appropriate 15k pull down resistors Anyway, as I said, time is short, anybody done this before and willing to share any ideas and gotchas? Remember, I'm not trying to meet exact specs, just get something working so I can concentrate on the logic design. TIA, Syms.Article: 73428
Symon wrote: > Hang on a minute! Legal redress? I'm not by any means defending FUD or > marketing crap on CAF, but let's get things in perspective. > He was on topic, > he said who he was, he said what his job is (was?!). I was trying to defend myself against a claim that could be interpreted as condoning spam. I was not trying to do that. I suppose it might have been nice if he said who he was at the top, but we all know by now. The ones I read I found fairly factual, though maybe a little excessive. Better than I have seen from many marketing people, though. Oh, the comment at the end? It wasn't legal redress I was asking for, but disavowing illegal methods. -- glenArticle: 73429
Mr Greenfield was not an anonymous spammer, he posted properly under his Altera address, and he was on-topic. Very much so, too much ! He just made a bunch of unsubstantiated, opinionated, inflammatory and wrong statements, and he violated the spirit and the unwritten rules of this newsgroup. And I hope he and his ilk will never do that again. Peter Alfke > From: "Symon" <symon_brewer@hotmail.com> > Newsgroups: comp.arch.fpga > Date: Tue, 21 Sep 2004 12:34:15 -0700 > Subject: Re: Mr. Greenfield, spare us the propaganda ! > > Hang on a minute! Legal redress? I'm not by any means defending FUD or > marketing crap on CAF, but let's get things in perspective. He was on topic, > he said who he was, he said what his job is (was?!). It's not as if he's > been doing it day in, day out for months. Looks like he posts via Google > Groups, so he won't have seen the responses this morning yet. Maybe he > should have some right of reply/opportunity to explain before he gets the > Spanish Inquisition! Remind me, what was the first amendment? ;-) > Cheers, Syms. > "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message > news:cipsa0$m5b$1@gnus01.u.washington.edu... >> >> Luc wrote: >> >>> Get rid of the spammer! Pls leave this ng to the technician and his >>> daily issues. >> >> Figure out how to get rid of spammers, and the whole world will >> love you. I get hundreds of spam e-mails a day, mostly real junk >> although one today wants to sell me a Virtex 4 kit. >> >> In this case we know where he works, and probably where he lives, >> so we could do something about it. (Legal, that is.) >> >> >> -- glen >> > >Article: 73430
Sorry Glen, bloody Usenet! One day I'll learn to read properly, and reply to the right person! Best, Syms. "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:ciq1pa$pcu$1@gnus01.u.washington.edu... > Oh, the comment at the end? It wasn't legal redress I was asking > for, but disavowing illegal methods. > > -- glenArticle: 73431
>Why is it so bad to use combinatorial loops? What are the potential >pitfalls? One of the main problems is that software doesn't support it. That may be partly a chicken/egg problem. If you have normal clean clocked logic, it's reasonably simple to see how to check setup/hold times. People know how to design that type of logic. What would it take to get a simplar level of maturity that used combinational loops? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73432
Also, check out the section "Level-sensitive Latches Using Concurrent Signal Assignments" in the Synplify reference manual. Cheers, Syms.Article: 73433
Hi, the data sheet tells 330MHz for CLKOUT_FREQ_2X_LF what yields into 660MBit/s while 620MBit/s are mentioned. ISE 6.2 compiles a small test with 200MHz clock (1x) constrains yielding into 800MBit/s. Will this work? The device is a XC3S200-4FT256. Thanks ThomasArticle: 73434
"H. Peter Anvin" <hpa@terminus.zytor.com> wrote in message news:ciprog$b7n$1@terminus.zytor.com... > Hi all, > > I just noticed yesterday that according to the schematic there is no > configuration EEPROM for the NIC on the Altera Nios development kit > (Cyclone edition.) Yet my board has a MAC which looks relatively > random (00:07:ed:0b:06:81). 00:07:ed is a prefix assigned to Altera. > > So... where is this number stored or derived from, if there is no > EEPROM? I'd like my own design to be compatible with the backup image > on the board, preferrably across multiple boards. > > -hpa I think it's stored in Flash, and then programmed into the Ethernet chip at startup. I believe you can change the MAC address using the serial port and the terminal, the same way the IP address etc is setup. JeroenArticle: 73435
On July 30 I posted: > Hello Bart, > > We've run your code and there is indeed a map packing problem. The MSB > is simply a FF driven by COUT of the previous slice. I see two related > problems with the packing: > > 1. FF "tmp1_16" should be packed into a slice utilizing the CIN pin > through the XORCY BEL as an extension of the carry chain but is not. > > 2. Instead, FF "tmp1_16" is being packed into the FFY BEL of the carry > chain slice that is driving it, displacing "tmp1_15" from its correct > packing location. > > I've logged CR 192265 for these issues. Meanwhile, I don't see a work > around for first issue except to extend the carry chain by one bit as > you mentioned or possibly by instantiating an XORCY and FF to > terminate > the carry chain. The second issue can be controlled with a map packing > constraint such as: > > INST "tmp1_16" XBLKNM = XLNX_WA ; > > I'll post again when we have a fix date scheduled. > > Regards, > Bret Wade > Xilinx Product Applications Just to follow up on this issue, it has been fixed for the next service pack, 6.3i SP2 which will become available in mid October. BretArticle: 73436
"Peter Alfke" <peter@xilinx.com> wrote in message news:BD75DB01.8C1C%peter@xilinx.com... > Mr Greenfield was not an anonymous spammer, he posted properly under his > Altera address, and he was on-topic. Very much so, too much ! > He just made a bunch of unsubstantiated, opinionated, inflammatory and wrong > statements, and he violated the spirit and the unwritten rules of this > newsgroup. And I hope he and his ilk will never do that again. > Peter Alfke Let's not forget that Austin got things going with the following: > Tim, > > There is no comparison. Seriously. Just go to the websites and compare > the features. > > V4 - triple oxide, low leakage, no power on surge in the core, faster, > over 100 new technical features (like SSIO, DSP48 MAC's, BRAM/FIFO, > 256AES, etc.) 4VLX25ES shipping now, development pcbs order entry open > and shipping ... > > Stratix II - ... (I'll let them play marketing) > > Austin Mr Greenfield certainly escalated things, but with Austin's "Bring 'em on" invitation, it's not surprising.Article: 73437
On Tue, 21 Sep 2004 07:06:54 -0700, Pepper Orlando wrote: > Though I will be using the webpack that ships with the Spartan-3 > intially, I am somewhat interested in the Linux version of BaseX or > Linux that I've been reading about. With version 6.3, is the Linux > version now native (not WINE)? Also, does it provide all of the > features of the Windows version? ISE has been Linux native since 6.1. The reason that webpack isn't offered in a Linux native version has to do with the licensing of package used to port the Windoze GUI to Linux. There was a thread, in this newsgroup, on this topic a few weeks ago, supposedly Xilinx is moving to a new toolkit in 7.1 which hopefully won't have the same licensing problems as the current toolkit.Article: 73438
Uwe Bonnes wrote: > Stephen Williams <spamtrap@icarus.com> wrote: > : Steven K. Knapp wrote: > > : > You may be able to remove the user reset completely. Is your user reset > : > only to guarantee the initial state of the design (a common ASIC practice)? > : > If so, you can eliminate this reset signal, which will potentially make you > r > : > design significantly smaller. > : > > : > Xilinx FPGAs have an internal Global Set/Reset signal that is asserted at > : > the end of the configuration process, guaranteeing the initial conditions. > > : This can't be good advice. I have a co-worker who does that often, > : and I get to write drivers for the resulting chips. It bugs me a lot. > > : Using the configuration process to initialize things to a safe > : startup state is nice and all (especially for "roms" and the like) > : but RESET is *not* the same thing. > > Stephen, > > is there a way to tell iverilog ( or other verilog simulators) to use > registers with a default initial value, so no "initial" assignment would be > needed. Only registers with a non default values would be needed to be set > explicitly. Yes, the Verilog-2001 declaration assignment syntax works. For example "reg foo = 1;" gets you a foo with an initial value of 1. What's more, xst seems to know what to do with this as well. I was at first reluctant to use it in my designs, doubting the xst support, but I found it works, so I use it, now. However, that really only simulates the power-on case. If you have resets at times other then power on, or soft resets for subsystems, this feature is obviously no help. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 73439
Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want to protect my own PCI core before delivering the complet VHDL project. My question: Is this possible to do a VHDL gate level Netlist from XST. Then to remap it in my VHDL project. Then to do a concatenated VHDL file of by project . Then do a new synthesis and P&R with webpack from my concatenate VHDL file. If yes, how is the best way ? Regards, Larry www.amontec.comArticle: 73440
Madhura,
What version of EDK are you using ? ISE doesn't allow you to add
more than 1 EDK subsystem, so I'm not sure how you were able to have 2
EDK modules to begin with.
Amit.
Madhura wrote:
>Hi,
>
>In my ISE project I have a microblaze processor. I can synthesise it,
>but get error when I implement it. The error is "You havemore than one
>instance of EDK module. This will not implement correctly."
>
>I am not sure how to fix this. Any suggestion will be helpful.
>
>Thanks,
>Madhura
>
>
Article: 73441
rickman wrote:
> Actually, what you are describing is a VHDL coding issue, not a MAP
> issue. If you want a 21 bit result from a VHDL add (I don't know
> Verilog well enough to say) you have to have at least one 21 bit input.
> VHDL won't assume that you expect a 21 bit result.
I am not sure about verilog. If I assign to a variable
the same width as the operands of +, I get warnings
about truncated bits.
One book says that {cout, sum} = in1 + in2 + cin;
will generate a full adder.
Another book says that the width for + is maximum of the width
of the two operands.
cross posted to comp.lang.verilog, to see if anyone there can say.
-- glen
Article: 73442Followup to: <4150a058$0$78279$e4fe514c@news.xs4all.nl> By author: "Jeroen" <jayjay.1974@xs4all.nl> In newsgroup: comp.arch.fpga > > I think it's stored in Flash, and then programmed into the Ethernet chip at > startup. I believe you can change the MAC address using the serial port and > the terminal, the same way the IP address etc is setup. > Interesting... is it unique to each board (and if so does it mean that the flash image on the CD isn't the "real" flash image)? -hpaArticle: 73443
Hi Stifler, Well, at least David included his affiliation/credentials. But let's take a quick (admittly fun) poke at your message. > How hard is it to tape out a product family that has no new innovation > from the previous family? It wasn't hard at all. I took a two-year vacation and watched my curser blink between table tennis matches. When time was up, I just copy and pasted my Stratix code and schematics, did a search and replace for the word "Stratix", and I was finished. Same goes for the other hundreds of engineers working on the product. But when transferring the masks to TSMC by our patented Carrier Pigeon technique, the high altitude and resulting exposure to radiation resulted in random mutations. The unfortunate outcome was a product 50% faster and 25% more dense than Stratix. Don't worry -- our rad-hard pigeon survived. > Except for the ALM which is still only a partial copy of the > Xilinx CLB. Most engineers should be able to examine a block diagram of a CLB and ALM and see that they are fundamentally different logic structures -- perhaps the location of your head is obscuring your vision? If you care to learn more, please refer to my previous posting on the subject (see http://groups.google.com/groups?selm=j2B0c.53313%24ah.15341%40twister01.bloor.is.net.cable.rogers.com&output=gplain). > If your new ALM is so gosh darn awesome, why didn't you > put it into Cyclone II? Different markets, different performance/area trade-offs. > Spartan 3 yield issues are solved and Spartan 3 is simply dominating > out there. Yield issues -- I thought there was just too much demand ;-)? And are you referring to the enormous performance deficit vs. Cyclone, or the 1M cumulative units of S-3 sold as of today compared to 2M for Cyclone back in March? But that's enough marketing blather from me. I hope your fingers recover so that you may continue to contribute to this newsgroup; I'm sure we'd all miss you otherwise. Warmest regards, Paul Leventis Chief Carrier Pigeon Officer Altera Corp.Article: 73444
In article <BD75A7BA.8B02%peter@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Yesterday, Altera rolled out its Sr. Marketing Attack Dog to poison this >newsgroup with his marketing messages. But you have to admit that it is FUN to taunt the VP Senior Marketing Attack Poodle who somehow thinks that static RAM offers significant security advantages over an SRAM-based approach for storing bitfile encryption keys. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 73445
Hi Austin, > Look at your own leakage data. Why folks are just plain > angry and upset when they see those leakage numbers I look at this data fairly frequently, and am not angry or upset. As the process has matured and our process control has tightened, we have seen a significant improvement in worst-case leakage; the latest numbers are really quite good. And while leakage has become a non-trivial contributor to overall power at 90 nm, dynamic power still dominates for most designs. Since I have no data on Virtex-4, I have nothing to compare our power (dynamic or static) with. We've achieved farily significant reductions in I/O and core dynamic power in Stratix II vs. Stratix (which was no power hog either), due partly to architectural and circuit changes, and of course partly due to Vcc reductions, process shrink and low-k dielectric (sadly, not available on V-4). So I can't wait to see how V-4 compares (or if there is "no comparison"). > You, and we, do not need every transistor to be as fast as possible. > For example, the configuration memory need not be fast. In fact, making > the config memory with 130 nm transistors in V4 makes it more immune to > single event upsets AND gives us low leakage! How is that for a direct > user benefit? (that you do not offer) Once you've used non-minimum gate length (for example, 130 nm on a 90 nm process) and higher Vt, why bother beating on the leakage of configuration memory further? Everyone knows that sub-threshold leakage is exponentially related to these two knobs, and since (as you point out) configuration RAMs can be made dog-slow, there's no penalty to extensively using these two techniques on those circuits. Config RAM makes up less than 5% of our leakage power. So I do not find your triple-gate oxide message particularly compelling -- where's the 50% leakage reduction coming from? Compared to what? Does 130 nm give you better SEU protection? You have previously argued that smaller transistors improve SEU; if I recall correctly the reasoning was that the smaller cross-section helps more than the lower cap, or something like that (I am no SEU expert). In one of your posts, you write "Oh, and yes, the 90nm technology is now 30% better than the 150 nm technology (15% better than the 130 nm technology) as proven by our tests (as presented to the MAPLD conference last month)." > No comparison, no contest. An overly strong statement you've made a few times. I think the jury is still out on V-4 vs. Stratix II, since the former was only just announced (well, not counting the previous two announcements...). If in a few years, after the market's finished its analysis, you turn out to be right, I'll buy you a beer next time I'm in San Jose. I think my pocket change is safe. > If all you have is FUD, you'd better go back and find something else to > talk about on this board. I for one can't wait until we can start throwing around some data. It stinks less than the current projectile material. While we will still be accusing each other of cooking the numbers, at least there will be numbers. Regards, Paul Leventis Altera Corp.Article: 73446
We have just started writing a small application on the NIOS IDE II
(version 1.0.0, build 316). I want to develop it in C++, but it won't
recognise C++ syntax, (class, new etc), so clearly I need to do
something to enable C++, but I can't find anything. I have found
similar problems on the forums/groups, but none with any answers. The
closest one was to use "extern "C"{...} around the #includes, but this
made no difference.
Any help would be appreciated.
Article: 73447> > For many years, I have teased Altera about their absence from this ng, and > later I have welcomed Paul Laventis for his positive contributions. But I > will have nothing in common with Dave Greenfield. > I don't feel this is true. Some of the questions I have posed about Altera and their devices I have gotten response from individials from Altera. Their responses have 'right on the ball' and very helpful. Now if they only offered a NIOS II Development Kit with EP2S60... Derek SimmonsArticle: 73448
Hello io, Since my email to you bounced, please send me your email address so that a fix can be provided for the ISME problem that you have encountered. If you have created a SR with Atera, the SR number will be helpful. Subroto Datta Altera Corp.Article: 73449
Victor, Cool problem. My analysis starts with the original code. > proc1 : PROCESS (In1, In2, OutA) IS > BEGIN > IF (In1 = '1' OR > (In2 = '1' AND OutA = '1')) THEN > InternalSig <= '1'; > ELSE > InternalSig <= '0'; > END IF; > END PROCESS proc1; > > proc2 : PROCESS (In0, In3, InternalSig) IS > BEGIN > IF (In0 = '1' AND > (In3 = '1' OR InternalSig = '1')) THEN > OutA <= '1'; > ELSE > OutA <= '0'; > END IF; > END PROCESS proc2; Rewriting this as assignments: InternalSig <= In1 or (In2 and OutA) ; OutA <= In0 and (In3 or InternalSig) ; Rewriting the assignment as a single assignment to OutA: OutA <= (In0 and In3) or (In0 and In1) or (In0 and In2 and OutA) ; My biggest concern is with the feedback term = (In0 and In2 and OutA) effect the output? "In0 and In2" cannot set the output, but "In0 and In2" can extend it once it has already been set. Already been set includes a glitch that sets In3 briefly when In2 is also set. Would I leave this in my circuit? It depends on where it is and why I need it in there. Is it at one of the primary inputs operating on signals that you have no control over? What are the other timing paths? I would be working to understand these before I left it in the circuit. It could be ok under certain conditions, but I would make sure I understand them. > I would be interested in hearing this issue addressed from an ASIC design > point of view as well. From an ASIC point of view, combinational logic feedback on the inside of a design can lead to a test issue. Again if it is at the IO of a design, you may be ok. Even if detailed analysis says it is ok, my first instinct is to remove something like this if at all possible. Is there something in the actual behavior of the inputs In0, In1, In2, or In3 that would allow you to eliminate some of the possible states of the circuit? My preference when working with history/state information is to use registers if at all possible. This may cost you more hardware resources, but would be worth it if it resulted in a circuit that is more stable than what you have now. Since there are order dependencies in the circuit, simply simulating an algorithmic sequence is not enough to prove they are the same. You will need to run particular sequences. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Victor Hannak wrote: > I am working on synthesizing some legacy code, and Synplify (correctly) > finds a combinatorial loop in the logic. My gut reaction was to modify the > function to use a latch instead of a feedback path because I've always been > told that combinatorial loops are bad practice for ASICs / FPGAs. After > completing the redesign, the new circuit takes up at least twice as much > space as the old one and it is difficult to exhaustively verify that the > re-implementation preserves the functionality. > > The combinatorial loop implementation is in a product, and has been working > without problems (presumably) for years. So the question I would like to > present for discussion is: > > Why is it so bad to use combinatorial loops? What are the potential > pitfalls? > > I would be interested in hearing this issue addressed from an ASIC design > point of view as well. > > For reference, I am including below a testbench I created to test the > various implementations. The first two process represent the original > implementation and create the OutA output. The 3rd and 4th processes > represent the latch based implementation. The 5th process is an (almost) > exhaustive testbench to verify that the two implementations behave the same > way. > > Thanks > > > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.numeric_std.ALL; > > > ENTITY test IS > END ENTITY test; > > ARCHITECTURE test_arch OF test IS > > SIGNAL Latch : STD_ULOGIC; > SIGNAL In0 : STD_ULOGIC; > SIGNAL In1 : STD_ULOGIC; > SIGNAL In2 : STD_ULOGIC; > SIGNAL In3 : STD_ULOGIC; > SIGNAL InternalSig : STD_ULOGIC; > SIGNAL OutA : STD_ULOGIC; > SIGNAL OutB : STD_ULOGIC; > SIGNAL TestVector : UNSIGNED(3 DOWNTO 0); > > BEGIN > > proc1 : PROCESS (In1, In2, OutA) IS > BEGIN > IF (In1 = '1' OR > (In2 = '1' AND OutA = '1')) THEN > InternalSig <= '1'; > ELSE > InternalSig <= '0'; > END IF; > END PROCESS proc1; > > proc2 : PROCESS (In0, In3, InternalSig) IS > BEGIN > IF (In0 = '1' AND > (In3 = '1' OR InternalSig = '1')) THEN > OutA <= '1'; > ELSE > OutA <= '0'; > END IF; > END PROCESS proc2; > > > proc3 : PROCESS (In0, In3, In1, In2, Latch) IS > BEGIN > > IF (In0 = '0') THEN > OutB <= '0'; > ELSE -- IF (In0 = '1') THEN > IF (In2 = '0') THEN > OutB <= In3 OR In1; > ELSE -- IF (In2 = '1') THEN > OutB <= Latch; > END IF; > END IF; > > END PROCESS proc3; > > proc4 : PROCESS (In0, In3, In1) IS > BEGIN > > IF (In0 = '0') THEN > Latch <= '0'; > ELSIF (In3 = '1' OR In1 = '1') THEN > Latch <= '1'; > ELSIF (In2 = '0' AND In1 = '0') THEN > Latch <= '0'; > END IF; -- note that there is no else statement here, thereby inferring > a latch > > END PROCESS proc4; > > > stim : PROCESS IS > BEGIN > > FOR i IN 0 TO 15 LOOP > > TestVector <= to_unsigned(i, 4); > WAIT FOR 1 ns; > ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error; > > FOR j IN 0 TO 3 LOOP > TestVector(j) <= NOT TestVector(j); > WAIT FOR 1 ns; > ASSERT (OutA = OutB) REPORT "Error found" SEVERITY error; > END LOOP; > > END LOOP; > > WAIT; > > END PROCESS stim; > > In0 <= TestVector(0); > In1 <= TestVector(1); > In2 <= TestVector(2); > In3 <= TestVector(3); > > > END ARCHITECTURE test_arch; > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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