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Tommy Thorn wrote: > > austin wrote: > > Pete, > > > > Got it. > > > > Will take it from here. > > > > Thanks. > .... > >> The ML401 is a cool looking Virtex 4 development board made > >> and sold by Xilinx. I should have one on Monday or Tuesday. > > While we're waiting for the sources, could someone fill me in on the > details on the "Evaluation versions of Xilinx tools" mentioned at the > button of > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sSecondaryNavPick=Design+Tools&iLanguageID=1&category=&key=HW-V4-ML401-USA&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@1661231197.1098759200@@@@&BV_EngineID=cccfadcmlffdfmfcflgcefldfhndfnf.0 > Ie., what can I do with that and how does it differ from the > non-evaluation tools (and from the free WebPACK)? > > The ML401 is a very impressive kit - IMO it sets a new bar for > development kits. I don't remember the details, but the webpack tools only cover the low end parts, but do not expire. The eval version is one of the full ISE packages, but is only licenced for 30 days. Webpack also has some features missing such as chip editor, etc. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75076
Symon wrote: > > All, > > After reading and contributing to a few interesting threads recently about > PCBs for FPGA designs, I thought I'd post about the technology I've been > using for the past 3-4 years. My job involves getting a lot of high density > circuitry into a small space, and so awhile back I decided to use microvias > (laser drilled vias) to pack more stuff onto my boards. The surprising thing > was that the boards worked out cheaper for my application than if I hadn't > used this method. When you say it was cheaper, you ended up with a 10 layer board with micro-vias, what was the alternative? I have a 10 layer board that I want to reduce to save money. How many layers can be saved by using micro-vias with BGAs? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75077
Hi Rick, rickman wrote: > WOW! That is one small CPU. I didn't realize that the pB was that > small. I will have to take a look to see why it is so much smaller than > a stack machine. Does it include interrupts? It has a single interrupt pin, when asserted it vectors to the top of program memory - you place a jump there to branch to your actual interrupt routine. If you need more than one interrupt channel you can easily craft a simple interrupt controller and hang it off one of picoblaze's IO ports, the IRQ handler queries the controller for the actual IRQ number, and vectors accordingly. As Ken Chapman (Picoblaze creator) so insightfully says - what's most interesting about Picoblaze is not the processor itself, but the context that you embed it in. > I notice that the PacoB uses less FFs, but more LUTs and runs slower > than the pB. Have you analyzed it to see how they differ? I belive the > source is available on the pB vs. the uB which must be bought, no? That's correct - Picoblaze is distributed in source form, Microblaze is encrypted VHDL unless you buy the source for extra (see recent discussions). Regards, JohnArticle: 75078
Hi, Recently I am doing P&R for my FPGA Design. Unfortunately, whenever I using the auto P&R provided in the software, I wont find a satisfactory result since some internal flip-flops alway have timing violations due to the routing, i.e. D-flipflop with setup time violation with respect to CLK, etc. So I doubt that whether a manual P&R is possible under this circumstance. If yes, what are the golden rules to do this manual P&R without any tool like floorplanning ? I will assign the gate/cells one by one into the FPGA.Article: 75079
Rick, I typically save about 4 to 6 layers by using microvias. My boards go into hand-held portable equipment so board space is at a premium, which is why the boards are so dense. To answer your question, in my experience, you would certainly be able to convert a ten layer conventional board to eight layer microvia board. 1) signal 2) signal 3) ground 4) signal 5) signal 6) ground 7) signal 8) signal Microvias between layers 1 and 2. Power routed with localised split planes. To suggest anything further, it depends on what size FPGAs/BGAs you're using. Are you willing and able to swap a lot of pins around on the FPGA to route to the other devices on your board? How many of the 10 layers you currently use are power/ground planes? Cheers, Syms. "rickman" <spamgoeshere4@yahoo.com> wrote in message news:417DE628.2A36D8BF@yahoo.com... > > When you say it was cheaper, you ended up with a 10 layer board with > micro-vias, what was the alternative? I have a 10 layer board that I > want to reduce to save money. How many layers can be saved by using > micro-vias with BGAs? >Article: 75080
Thanks to all. i'm using a win2000 system. but guess the same serial port code should work for all Win based systems. Martin,i've actualy written similar code after posting here last. Thanks for your code(your's much neater :) ) i figured serial communication to be the easiet of all PC-FPGA communication ,I could implement hence the choice.I intend to "graduate" to others in due course of time. rgds. srinivas.Article: 75081
How can we extract clock from bi-phase encoded data (3.072Mbps - AES/EBU Data) using CLKDLL of Xilinx FPGA. The clock should be able to adjust itself to any slight drifting of the bi-phase data.Article: 75082
My ModelSim Xilinx library, unisim and simprim and some other built in libraries have their directory referred to C:\Xilinx. I want it to refer to another directory, such as C:\Engineer\Xilinx, which is the directory where I installed Webpack. Is there anyway to do that? HendraArticle: 75083
"Rene Tschaggelar" <none@none.net> wrote in message news:417d4fca$0$28024$5402220f@news.sunrise.ch... > Jock wrote: > > > Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - > > i.e. what is the maximum rise time on the edge of the PLL clock input? > > What is wrong with a line receiver to meet the AC voltage > specifications ? > The 1.5V-IO requires 0.35 and 0.65 times 1.5V as levels. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net We don't have a lot of real estate and I was looking at ways of reducing component count.Article: 75084
Jason Berringer wrote: > A question to all who have written a bus interface. Is a finite state > machine the best way to implement a bus interface (e.g. ISA, PCI, > uController) or does it matter. I have examined a few and almost everyo= ne is > a FSM. I haven't written any FSMs to date and was curious if there was = a > benefit to using an FSM. Does it reduce the logic needed in the design,= or > does it allow for a faster design? Any comments are appreciated. >=20 > I have done a few bus interfaces myself, but due to my lack of experien= ce > with a FSM I have not their use in the applications. >=20 > Jason >=20 >=20 Well, when I wrote an OPB->ISA bus bridge I used FSMs for both bus=20 interfaces. A FSM makes it quite simple to achieve operation according=20 to the bus specs due to its sequential nature. I didn't look into other=20 methods though so I can't say a FSM is the best solution. Any basic book = on VHDL/Verilog, or the Xilinx docs for that matter, should give you=20 hints on how to code a state machine. Johan --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Research engineer, embedded systems Totalf=F6rsvarets forskningsinstitut Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 75085
Hi all, When synthesizing my design with Quartus v4.0, I noticed that a critical time path (after optimizations for timing) was in the following process: process (clk, reset) begin if (reset = 1) data_reg <= (others => '0'); elsif (rising_edge(clk)) for i in 0 to 24 loop if (byte_cnt = i) then data_reg <= frame(i * 8 + 7 downto i * 8); end loop; end if; end process; The assignment to data_reg ran too slow. It figures that this is slow because it contains a large mux. A colleague suggested to replace the "for" with an explicit if..elsif of 25 clauses. I said "no way" - it's the same, and Quartus should be smart enough to figure it out. Surprise ! Quartus isn't. When I indeed changed to a full if..elsif list (unrolled the for loop), the path shortened by a few ns. Dire dissapointment, because the "for" code is nicer, maintainable and extensible... The 25 clause if...elsif is clinky, big and prone to bugs. Has anyone run into a similar problem and/or has some insights how to handle this ? Why isn't it trivial for Quartus to figure out ? TIA EliArticle: 75086
>How can we extract clock from bi-phase encoded data (3.072Mbps - >AES/EBU Data) using CLKDLL of Xilinx FPGA. The clock should be able to >adjust itself to any slight drifting of the bi-phase data. 3 MHz is slow. Just build a FSM that parses the data stream. Say with a 10x or 16x clock. Experiment a bit with some graph paper if you haven't done it before. It will be obvious when you see it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75087
On Tue, 26 Oct 2004 03:21:05 -0500, hmurray@suespammers.org (Hal Murray) wrote: >>How can we extract clock from bi-phase encoded data (3.072Mbps - >>AES/EBU Data) using CLKDLL of Xilinx FPGA. The clock should be able to >>adjust itself to any slight drifting of the bi-phase data. > >3 MHz is slow. Just build a FSM that parses the data stream. >Say with a 10x or 16x clock. > >Experiment a bit with some graph paper if you haven't done it before. >It will be obvious when you see it. This works for pure data extraction, but no good for audio apps where you need to produce a jitter-free clock for an output stream locked to the input rate.Article: 75088
Symon, What are the speeds of your clocks and signals both within your FPGA and external? Are you getting and passing EMI compliance testing? Have you tried or considered using thin layers between power (also signal in your case) and ground planes instead of or in addition to bypass caps? Do you do SI/EMI simulations or just build these boards? :) Thanks for sharing this! Awesome stuff! Thanks, KenArticle: 75089
"Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote > A question to all who have written a bus interface. Is a finite state > machine the best way to implement a bus interface (e.g. ISA, PCI, > uController) or does it matter. I have examined a few and almost everyone is > a FSM. I haven't written any FSMs to date and was curious if there was a > benefit to using an FSM. Does it reduce the logic needed in the design, or > does it allow for a faster design? Any comments are appreciated. First of all: what doi you consider to ba e FSM and what to be no FSM? You won't be able to implement a bus interface without any kind of statemachine if you consider a counter to be a statemachine. I would use a dedicated FSM to get a reusable structure with easy debugging abbilities (if your timing and area needs allow you to use one). bye ThomasArticle: 75090
Symon wrote: > All, > > After reading and contributing to a few interesting threads recently about > PCBs for FPGA designs, I thought I'd post about the technology I've been > using for the past 3-4 years. My job involves getting a lot of high density > circuitry into a small space, and so awhile back I decided to use microvias > (laser drilled vias) to pack more stuff onto my boards. The surprising thing > was that the boards worked out cheaper for my application than if I hadn't > used this method. What's the diameter/restring of micro vias ? I don't see them in the 'capabilities' of the pcb supplier I'd like to use. They however have blind vias with hole diameter down to 50µm. I guess that would work. > The upshot is, for a lot of my applications this saves me 4-6 layers over a > conventional board. (For others, it simply makes the job possible!) This > more than compensates for the cost of using the laser vias. Also, I don't > want to hear about warpage! Although the stack looks asymetrical wrt ground > planes, the stack up *is* symmetrical wrt cores and prepreg layers. I've had > no problems whatsoever with warpage on 1.6 mm boards of up to 8x6 inches. What is warpage btw ? SylvainArticle: 75091
On Tue, 26 Oct 2004 08:47:35 GMT, Mike Harrison <mike@whitewing.co.uk> wrote: >On Tue, 26 Oct 2004 03:21:05 -0500, hmurray@suespammers.org (Hal Murray) wrote: > >>>How can we extract clock from bi-phase encoded data (3.072Mbps - >>>AES/EBU Data) using CLKDLL of Xilinx FPGA. The clock should be able to >>>adjust itself to any slight drifting of the bi-phase data. >> >>3 MHz is slow. Just build a FSM that parses the data stream. >>Say with a 10x or 16x clock. >> >>Experiment a bit with some graph paper if you haven't done it before. >>It will be obvious when you see it. >This works for pure data extraction, but no good for audio apps where you need to produce a >jitter-free clock for an output stream locked to the input rate. Jitter from the clock recovery process doesn't necessarily imply excessive jitter in the output stream. There are ways of removing or reducing said jitter, however pretty much all of them involve a low noise oscillator of some sort. BTW, Please avoid using the term "jitter-free" because such a thing is not possible. Regards, AllanArticle: 75092
Forget a V2PRO... unless you need a power PC... there are far cheaper options to get a processor. I also never suggested using bleeding edge... if you pick an 'older part' you will find the static current better... it just won't have the same capability as the modern 90 nm parts.. although cyclone (cough cough) seem to have a lower quiescent current 12mA - 80 mA.. but they probably cheated to get that. And even tho A or X seems good what about Q ? Quicklogic Eclipse is a low power (not so) FPGA .. so they might be via OTP... so you prototype with RAM based... but you can't beat the 22 - 250 uA quiescent current... and only 100mA at 100Mhz. Don't forget the option of powering down when not in use, use a coolrunner to turn the FPGA off if necessary / possible just don't forget to shut down I/O too.. or the saving will be killed by protection diodes. Older FPGA's have smaller configurations and can be programmed fast if you externally clock them. And yea.. design to typical.. select of test even :-) unless your running at -20 or +60C .. but at 0C you NiMH battery life will be half that at 20C too.. Then pick a better battery... heard of lithium ion? :-) You might also want to watch the D cells.. often the are a 'C' cell in side a cardboard wrapper. There are also special 'radio modeller' NiCAD's that have rather nice mAH ratings... designed for electric cars and planes. I have a battery pack here good for 600mA hours @ 8.4V... not much bigger than a D cell. Simon "Symon" <symon_brewer@hotmail.com> wrote in message news:2u4nrqF26i2edU1@uni-berlin.de... > Simon, > I guess it's been a while since you checked out the quiescent supply > currents for the latest parts? For example, worst case Iccintq for the > smallest V2PRO (XC2VP2) is 300mA. That's about 20 hours on a NiMH D cell. > Typical is 20mA, but no-one would design with typical figures, would they? > BTW, anyone know why there's such a big difference from 'typical' to 'max' > figures? Does it depend on the configuration used in the part? > Cheers, Syms. > > "Simon Peacock" <nowhere@to.be.found> wrote in message > news:417cd164@news.actrix.gen.nz... > > FPGA's by their very nature are low power.. provided you don't clock them > > fast. > > > > >Article: 75093
Xavier <> wrote in message news:<ee89b29.-1@webx.sUN8CHnE>... > Hi everyone, > > I had a question in regards to the Xilinx ISE. I have a design in which i use synopsys for synthesis. Then, I import the edif file into XILINX ISE. Next, I go to "Create Timing Constraints." > > What i find here is a list of values that the Xilinx ISE assumes to be clocks. The problem is, these values do not contain some of the clock signals. Why is this? Is there a way i can force it to put some of my signals in this clock constraint section? > > It has a lot of signals in this section that aren't even clock signals, is there a way to define this section better? > > Thanks, > > Xavier Hi Xavier, the Xilinx ISE constraints editor usually relates signals as clocks if they are connected to the clock input of a FF/register/counter.. sometimes when you code your design (i assume that you are using HDL) you connect signals such as FF outputs to a FF clock input (intetionaly or not) when you do so the constraints editor infers that you meant for a clock and add it to the clocks constraints list. I suggest you to check all the un-desired clocks in the constraints editor list and make sure that it is what you ment. using the output of a FF as a clock or placing logic before a clock input is usually no a good practice (async deisgn). after you will re-sync your design the "un-wanted" clocks will be removed from the constraints editor clocks list. Tip - I'm not fimiliar with the synopsis synthisizer but in the synplify synthisizer you can view the RTL view of your design and there you can see the "clock tree" branch, if it contains un-wnated nets it could give you a good hint... Hope that its helpfull... Moti.Article: 75094
Hi @ all,
it is one possibility to
synchronize an asynchronous reset so that all flip flops in
the FPGA are resetted within the same clock period.
Using this synchronized reset
can I still write the process like that:
process(Sync_reset, Clk)
begin
if Sync_reset='1' then
...
elsif rising_edge(Clk) then
...
end if;
end process;
or does it make more sense to write it like that:
process(Sync_reset, CLk)
begin
if rising_edge(Clk) then
if Sync_reset='1' then
...
else
...
end if;
end if;
end process;
I would be very thankful for your opinion.
Rgds
André
Article: 75095
Hi Eliben,
> When synthesizing my design with Quartus v4.0, I noticed that a
> critical time path (after optimizations for timing) was in the
> following process:
>
> process (clk, reset)
> begin
> if (reset = 1)
> data_reg <= (others => '0');
> elsif (rising_edge(clk))
> for i in 0 to 24 loop
> if (byte_cnt = i) then
> data_reg <= frame(i * 8 + 7 downto i * 8);
> end loop;
> end if;
> end process;
>
> The assignment to data_reg ran too slow. It figures that this is
> slow because it contains a large mux. A colleague suggested to replace
> the "for" with an explicit if..elsif of 25 clauses. I said
> "no way" - it's the same, and Quartus should be smart enough to figure
> it out. Surprise ! Quartus isn't. When I indeed changed
> to a full if..elsif list (unrolled the for loop), the path shortened by
> a few ns. Dire dissapointment, because the "for" code
> is nicer, maintainable and extensible... The 25 clause if...elsif is
> clinky, big and prone to bugs.
The constructs are NOT the same. In the loop example you infer a latch
situation in case byte_cnt is not between 0 and 24, which Quartus will
cater for. In the unrolled version you made I am 99.9999% sure that it ends
with
elsif byte_cnt = 23 then
data_reg <= blablabla;
else -- Note: no elsif!!!
data_reg <= hohohoho;
Thus, you also define a value for data_reg for values of byte_cnt for values
25 and up, which is not what you do in the loop. A simple solution would be
to add a default assignment for data_reg, as such:
process (clk, reset)
begin
if (reset = 1)
data_reg <= (others => '0');
elsif (rising_edge(clk))
data_reg <= frame(7 downto 0); -- not the same but saves a lot of typing
for i in 0 to 24 loop
if (byte_cnt = i) then
data_reg <= frame(i * 8 + 7 downto i * 8);
end if;
end loop;
end if;
end process;
In the meantime, Quartus synthesis is still under very active development.
Quartus II 4.1 has had a mux optimization overhaul, so I suggest that you
try both alternatives again using 4.1 and see what comes out.
Best regards,
Ben
Article: 75096
>
> 3 MHz is slow. Just build a FSM that parses the data stream.
> Say with a 10x or 16x clock.
>
So, out of curiosity, how would you do it if the BiPhase clock was around
80MHz ? (ideally Spartan 2 based)
Dave
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Article: 75097
Faster and smaller generally comes out a little ahead of larger slower in my
experience. The trade off between clock speed and area is more or less a wash
because power is proportional to clock frequency, however there are second
order effects to consider. First, a smaller design means the routing can be
more localized. Routing distance is roughly proportional to the square root of
the area. Secondly, a parallel design, at least for arithmetic has extra
routing orthogonal to the signal path and extra gating to handle the carry
functions. This extra logic and associated routing makes the v-F curve
non-linear.
Austin Lesea wrote:
> Hal,
>
> Let's see....P= CV^2F, and so for each node switching, the power scales
> with frequency.
>
> One node at F is equal to two nodes at 1/2F? Yes, it sure looks that way.
>
> I suppose the reason to run slower is to run cooler.
>
> But, you are right, run the smallest part as fast as needed to do the work.
>
> No reason to run it any faster than needed, however.
>
> One reason for the very low power for the DSP48 is that the capacitive
> loads are very small.
>
> Good catch.
>
> Thanks,
>
> Austin
>
> Hal Murray wrote:
>
> >>FPGAs are very efficient for doing the work (dynamic power), but high
> >>clock speeds means lots of power. Better to make the algorithm highly
> >>parallel, and lower the clock rate as much as possible.
> >
> >
> > What's going on here? Classic reasoning says that 2 FFs at half
> > speed will take the same power as 1 FF at full speed. (assuming
> > same cap load...)
> >
> > Why not run faster so you can use a smaller part and get lower
> > static power?
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 75098Hi, Did anyone know what is the Xilinx recommended pull-up register value for the JTAG configuration pins (TCK, TMS, TDI, TDO and M0-M2) for Virtex4? Thanks, IvanArticle: 75099
Thanks Nathan, I have put the epcs controller component in the custom board (removed the asmi) with new the custom board as target. This seems to work, do not get the refdes error anymore in the SOPC builder. However i donot understand why we have to design a custom board, the flash programmer has all the info it needs from the system.ptf file, isn't it??? Also i found out that the NIOS2 IDE flash programmer can only program "CFI" compatible flash, i replaced lv800 flash with lv160d flash!!! Is there a software utility we can use to mimic "CFI" compatible flash while using "old style flash" ??? regards Ron Proveniers www.info-trade.nl "Nathan Knight" <nknight@altera.com> schreef in bericht news:46037103.0410251524.227e2aab@posting.google.com... > Hi Ron, > > First, when you run mk_target_board, with the --epcs parameter, an > ASMI component is automatically added to the resulting system. This > is the component that should be used in the resulting flash programmer > design. If you try to replace it with an EPCS controller component, > as it sounds like you have, it may not work. Stick with the ASMI > component. > > Second, when you create your actual design in SOPC Builder and pick > your target board up at the top, the EPCS controller in that design > will be hard-coded to have the same refdes as the ASMI in the flash > programmer design. The refdes is how the tools keep track of flash > devices (both CFI and EPCS) between the target board and the actual > design. You may give them different base addresses in the two > designs, or even name them differently, so the refdes is the one thing > that always has to be common. And since a system can have only one > EPCS (or ASMI), it forces you to use the same refdes for the one in > your real system the one in the target board. > > Re-generate and recompile your target board this way, then do the same > with your actual design after selecting the new target board up at the > top. Flash programming should work after that. > > Regards, > > -Nathan Knight > Altera Corp.
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